2 * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
39 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
43 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO IMX_GPIO_NR(3, 28)
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
50 #define TEMPERATURE_MIN (-40)
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
55 #define TEMPERATURE_HOT 80
58 DECLARE_GLOBAL_DATA_PTR;
60 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
67 #define TX6_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \
71 #define TX6_FEC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \
75 #define TX6_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
79 #define TX6_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
85 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
87 MX6_PAD_GPIO_17__GPIO7_IO12 | TX6_DEFAULT_PAD_CTRL,
90 #if CONFIG_MXC_UART_BASE == UART1_BASE
91 MX6_PAD_SD3_DAT7__UART1_TX_DATA | TX6_DEFAULT_PAD_CTRL,
92 MX6_PAD_SD3_DAT6__UART1_RX_DATA | TX6_DEFAULT_PAD_CTRL,
93 MX6_PAD_SD3_DAT1__UART1_RTS_B | TX6_DEFAULT_PAD_CTRL,
94 MX6_PAD_SD3_DAT0__UART1_CTS_B | TX6_DEFAULT_PAD_CTRL,
96 #if CONFIG_MXC_UART_BASE == UART2_BASE
97 MX6_PAD_SD4_DAT4__UART2_RX_DATA | TX6_DEFAULT_PAD_CTRL,
98 MX6_PAD_SD4_DAT7__UART2_TX_DATA | TX6_DEFAULT_PAD_CTRL,
99 MX6_PAD_SD4_DAT5__UART2_RTS_B | TX6_DEFAULT_PAD_CTRL,
100 MX6_PAD_SD4_DAT6__UART2_CTS_B | TX6_DEFAULT_PAD_CTRL,
102 #if CONFIG_MXC_UART_BASE == UART3_BASE
103 MX6_PAD_EIM_D24__UART3_TX_DATA | TX6_DEFAULT_PAD_CTRL,
104 MX6_PAD_EIM_D25__UART3_RX_DATA | TX6_DEFAULT_PAD_CTRL,
105 MX6_PAD_SD3_RST__UART3_RTS_B | TX6_DEFAULT_PAD_CTRL,
106 MX6_PAD_SD3_DAT3__UART3_CTS_B | TX6_DEFAULT_PAD_CTRL,
109 MX6_PAD_EIM_D28__I2C1_SDA | TX6_DEFAULT_PAD_CTRL,
110 MX6_PAD_EIM_D21__I2C1_SCL | TX6_DEFAULT_PAD_CTRL,
112 /* FEC PHY GPIO functions */
113 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION |
114 TX6_DEFAULT_PAD_CTRL, /* PHY POWER */
115 MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION |
116 TX6_DEFAULT_PAD_CTRL, /* PHY RESET */
117 MX6_PAD_SD3_DAT4__GPIO7_IO01 | TX6_DEFAULT_PAD_CTRL, /* PHY INT */
120 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
122 MX6_PAD_ENET_MDC__ENET_MDC | TX6_FEC_PAD_CTRL,
123 MX6_PAD_ENET_MDIO__ENET_MDIO | TX6_FEC_PAD_CTRL,
124 MX6_PAD_GPIO_16__ENET_REF_CLK | TX6_FEC_PAD_CTRL,
125 MX6_PAD_ENET_RX_ER__ENET_RX_ER | TX6_FEC_PAD_CTRL,
126 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | TX6_FEC_PAD_CTRL,
127 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | TX6_FEC_PAD_CTRL,
128 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | TX6_FEC_PAD_CTRL,
129 MX6_PAD_ENET_TX_EN__ENET_TX_EN | TX6_FEC_PAD_CTRL,
130 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | TX6_FEC_PAD_CTRL,
131 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | TX6_FEC_PAD_CTRL,
134 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
136 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION |
138 MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION |
142 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
144 MX6_PAD_EIM_D28__I2C1_SDA | TX6_I2C_PAD_CTRL,
145 MX6_PAD_EIM_D21__I2C1_SCL | TX6_I2C_PAD_CTRL,
148 static const struct gpio const tx6qdl_gpios[] = {
149 /* These two entries are used to forcefully reinitialize the I2C bus */
150 { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
151 { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
153 { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
154 { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
155 { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
156 { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
159 static int pmic_addr __data;
161 #if defined(CONFIG_SOC_MX6Q)
162 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4
163 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4
164 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8
165 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8
166 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898
167 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c
168 #define I2C1_SEL_INPUT_VAL 0
170 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
171 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158
172 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174
173 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528
174 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544
175 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0868
176 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e086c
177 #define I2C1_SEL_INPUT_VAL 1
184 static void tx6_i2c_recover(void)
188 #define SCL_BIT (1 << (TX6_I2C1_SCL_GPIO % 32))
189 #define SDA_BIT (1 << (TX6_I2C1_SDA_GPIO % 32))
191 if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
192 (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
195 debug("Clearing I2C bus\n");
196 if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
197 printf("I2C SCL stuck LOW\n");
200 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
201 GPIO3_BASE_ADDR + GPIO_DR);
202 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
203 GPIO3_BASE_ADDR + GPIO_DIR);
205 if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
206 printf("I2C SDA stuck LOW\n");
209 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
210 GPIO3_BASE_ADDR + GPIO_DIR);
211 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
212 GPIO3_BASE_ADDR + GPIO_DR);
213 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
214 GPIO3_BASE_ADDR + GPIO_DIR);
216 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
217 ARRAY_SIZE(tx6_i2c_gpio_pads));
220 for (i = 0; i < 18; i++) {
221 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
223 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
224 writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
227 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
232 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
234 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
235 printf("I2C bus recovery succeeded\n");
237 printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
241 debug("Setting up I2C Pads\n");
242 imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
243 ARRAY_SIZE(tx6_i2c_pads));
246 /* placed in section '.data' to prevent overwriting relocation info
249 static u32 wrsr __data;
251 #define WRSR_POR (1 << 4)
252 #define WRSR_TOUT (1 << 1)
253 #define WRSR_SFTW (1 << 0)
255 static void print_reset_cause(void)
257 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
258 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
262 printf("Reset cause: ");
264 srsr = readl(&src_regs->srsr);
265 wrsr = readw(wdt_base + 4);
267 if (wrsr & WRSR_POR) {
268 printf("%sPOR", dlm);
271 if (srsr & 0x00004) {
272 printf("%sCSU", dlm);
275 if (srsr & 0x00008) {
276 printf("%sIPP USER", dlm);
279 if (srsr & 0x00010) {
280 if (wrsr & WRSR_SFTW) {
281 printf("%sSOFT", dlm);
284 if (wrsr & WRSR_TOUT) {
285 printf("%sWDOG", dlm);
289 if (srsr & 0x00020) {
290 printf("%sJTAG HIGH-Z", dlm);
293 if (srsr & 0x00040) {
294 printf("%sJTAG SW", dlm);
297 if (srsr & 0x10000) {
298 printf("%sWARM BOOT", dlm);
307 static const char __data *tx6_mod_suffix;
309 #ifdef CONFIG_IMX6_THERMAL
311 #include <imx_thermal.h>
314 static void print_temperature(void)
316 struct udevice *thermal_dev;
317 int cpu_tmp, minc, maxc, ret;
318 char const *grade_str;
319 static u32 __data thermal_calib;
321 puts("Temperature: ");
322 switch (get_cpu_temp_grade(&minc, &maxc)) {
323 case TEMP_AUTOMOTIVE:
324 grade_str = "Automotive";
326 case TEMP_INDUSTRIAL:
327 grade_str = "Industrial";
329 case TEMP_EXTCOMMERCIAL:
330 grade_str = "Extended Commercial";
333 grade_str = "Commercial";
335 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
336 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
338 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
341 printf(" at %dC", cpu_tmp);
343 puts(" - failed to read sensor data");
345 puts(" - no sensor device found");
348 if (fuse_read(1, 6, &thermal_calib) == 0) {
349 printf(" - calibration data 0x%08x\n", thermal_calib);
351 puts(" - Failed to read thermal calib fuse\n");
355 static inline void print_temperature(void)
362 u32 cpurev = get_cpu_rev();
365 if (is_cpu_type(MXC_CPU_MX6SL)) {
367 tx6_mod_suffix = "?";
368 } else if (is_cpu_type(MXC_CPU_MX6DL)) {
370 tx6_mod_suffix = "U";
371 } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
373 tx6_mod_suffix = "S";
374 } else if (is_cpu_type(MXC_CPU_MX6Q)) {
376 tx6_mod_suffix = "Q";
377 } else if (is_cpu_type(MXC_CPU_MX6QP)) {
379 tx6_mod_suffix = "QP";
382 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
384 (cpurev & 0x000F0) >> 4,
385 (cpurev & 0x0000F) >> 0,
386 mxc_get_clock(MXC_ARM_CLK) / 1000000);
390 #ifdef CONFIG_MX6_TEMPERATURE_HOT
391 check_cpu_temperature(1);
397 /* serial port not initialized at this point */
398 int board_early_init_f(void)
403 #ifndef CONFIG_MX6_TEMPERATURE_HOT
404 static bool tx6_temp_check_enabled = true;
406 #define tx6_temp_check_enabled 0
409 #ifdef CONFIG_TX6_NAND
410 #define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
412 #ifdef CONFIG_MMC_BOOT_SIZE
413 #define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
415 #define TX6_FLASH_SZ 2
417 #endif /* CONFIG_TX6_NAND */
419 #define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
421 static char tx6_mem_table[] = {
422 '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
423 '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
424 '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
425 '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
426 '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
427 '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
428 '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
429 '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
430 '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
431 '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
432 '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
433 '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
436 #ifdef CONFIG_RN5T567
438 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
439 #define VDD_CORE_VAL rn5t_mV_to_regval(1400) /* DCDC1 */
440 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
441 #define VDD_SOC_VAL rn5t_mV_to_regval(1400) /* DCDC2 */
442 #define VDD_SOC_VAL_LP rn5t_mV_to_regval(1400)
443 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
444 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
445 #define VDD_HIGH_VAL rn5t_mV_to_regval(3000) /* DCDC4 */
446 #define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3000)
447 #define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 */
448 #define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300)
449 #define VDD_IO_EXT_VAL rn5t_mV_to_regval2(3300) /* LDO2 */
450 #define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval2(3300)
452 static struct pmic_regs rn5t567_regs[] = {
453 { RN5T567_NOETIMSET, 0x5, },
454 { RN5T567_DC1DAC, VDD_CORE_VAL, },
455 { RN5T567_DC2DAC, VDD_SOC_VAL, },
456 { RN5T567_DC3DAC, VDD_DDR_VAL, },
457 { RN5T567_DC4DAC, VDD_HIGH_VAL, },
458 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
459 { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, },
460 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
461 { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
462 { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
463 { RN5T567_DC2CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
464 { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
465 { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
466 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
467 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
468 { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
469 { RN5T567_LDO2DAC, VDD_IO_EXT_VAL, },
470 { RN5T567_LDOEN1, 0x03, ~0x1f, },
471 { RN5T567_LDOEN2, 0x10, ~0x30, },
472 { RN5T567_LDODIS, 0x1c, ~0x1f, },
473 { RN5T567_INTPOL, 0, },
474 { RN5T567_INTEN, 0x3, },
475 { RN5T567_IREN, 0xf, },
476 { RN5T567_EN_GPIR, 0, },
483 struct pmic_regs *regs;
486 #ifdef CONFIG_LTC3676
487 { 0x3c, 1, NULL, 0, },
489 #ifdef CONFIG_RN5T567
490 { 0x33, 3, rn5t567_regs, ARRAY_SIZE(rn5t567_regs), },
494 static inline char tx6_mem_suffix(void)
496 size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
498 debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
499 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
501 if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
503 if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
506 return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
507 return tx6_mem_table[mem_idx];
510 static int tx6_get_mod_rev(unsigned int pmic_id)
512 if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
513 return tx6_mod_revs[pmic_id].rev;
518 static int tx6_pmic_probe(void)
522 debug("%s@%d: \n", __func__, __LINE__);
524 for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
525 u8 i2c_addr = tx6_mod_revs[i].addr;
526 int ret = i2c_probe(i2c_addr);
529 debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
532 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
537 static int tx6_mipi(void)
539 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
540 struct fuse_bank4_regs *fuse = (void *)ocotp->bank[4].fuse_regs;
541 u32 gp1 = readl(&fuse->gp1);
543 debug("Fuse gp1 @ %p = %08x\n", &fuse->gp1, gp1);
552 debug("%s@%d: \n", __func__, __LINE__);
554 pmic_id = tx6_pmic_probe();
555 if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
556 pmic_addr = tx6_mod_revs[pmic_id].addr;
558 printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
560 is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
561 tx6_mipi() ? 2 : is_lvds(), tx6_get_mod_rev(pmic_id),
566 ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
568 printf("Failed to request tx6qdl_gpios: %d\n", ret);
570 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
572 /* Address of boot parameters */
573 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
574 gd->bd->bi_arch_number = -1;
576 if (ctrlc() || (wrsr & WRSR_TOUT)) {
577 if (wrsr & WRSR_TOUT)
578 printf("WDOG RESET detected; Skipping PMIC setup\n");
580 printf("<CTRL-C> detected; safeboot enabled\n");
581 #ifndef CONFIG_MX6_TEMPERATURE_HOT
582 tx6_temp_check_enabled = false;
587 ret = tx6_pmic_init(pmic_addr, tx6_mod_revs[pmic_id].regs,
588 tx6_mod_revs[pmic_id].num_regs);
590 printf("Failed to setup PMIC voltages: %d\n", ret);
598 debug("%s@%d: \n", __func__, __LINE__);
600 /* dram_init must store complete ramsize in gd->ram_size */
601 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
602 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
606 void dram_init_banksize(void)
608 debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
609 CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
610 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
611 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
613 #if CONFIG_NR_DRAM_BANKS > 1
614 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
615 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
620 #ifdef CONFIG_FSL_ESDHC
621 #define SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \
622 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
625 static const iomux_v3_cfg_t mmc0_pads[] = {
626 MX6_PAD_SD1_CMD__SD1_CMD | SD_PAD_CTRL,
627 MX6_PAD_SD1_CLK__SD1_CLK | SD_PAD_CTRL,
628 MX6_PAD_SD1_DAT0__SD1_DATA0 | SD_PAD_CTRL,
629 MX6_PAD_SD1_DAT1__SD1_DATA1 | SD_PAD_CTRL,
630 MX6_PAD_SD1_DAT2__SD1_DATA2 | SD_PAD_CTRL,
631 MX6_PAD_SD1_DAT3__SD1_DATA3 | SD_PAD_CTRL,
633 MX6_PAD_SD3_CMD__GPIO7_IO02 | TX6_GPIO_PAD_CTRL,
636 static const iomux_v3_cfg_t mmc1_pads[] = {
637 MX6_PAD_SD2_CMD__SD2_CMD | SD_PAD_CTRL,
638 MX6_PAD_SD2_CLK__SD2_CLK | SD_PAD_CTRL,
639 MX6_PAD_SD2_DAT0__SD2_DATA0 | SD_PAD_CTRL,
640 MX6_PAD_SD2_DAT1__SD2_DATA1 | SD_PAD_CTRL,
641 MX6_PAD_SD2_DAT2__SD2_DATA2 | SD_PAD_CTRL,
642 MX6_PAD_SD2_DAT3__SD2_DATA3 | SD_PAD_CTRL,
644 MX6_PAD_SD3_CLK__GPIO7_IO03 | TX6_GPIO_PAD_CTRL,
647 #ifdef CONFIG_TX6_EMMC
648 static const iomux_v3_cfg_t mmc3_pads[] = {
649 MX6_PAD_SD4_CMD__SD4_CMD | SD_PAD_CTRL,
650 MX6_PAD_SD4_CLK__SD4_CLK | SD_PAD_CTRL,
651 MX6_PAD_SD4_DAT0__SD4_DATA0 | SD_PAD_CTRL,
652 MX6_PAD_SD4_DAT1__SD4_DATA1 | SD_PAD_CTRL,
653 MX6_PAD_SD4_DAT2__SD4_DATA2 | SD_PAD_CTRL,
654 MX6_PAD_SD4_DAT3__SD4_DATA3 | SD_PAD_CTRL,
656 MX6_PAD_NANDF_ALE__SD4_RESET | SD_PAD_CTRL,
660 static struct tx6_esdhc_cfg {
661 const iomux_v3_cfg_t *pads;
663 enum mxc_clock clkid;
664 struct fsl_esdhc_cfg cfg;
666 } tx6qdl_esdhc_cfg[] = {
667 #ifdef CONFIG_TX6_EMMC
670 .num_pads = ARRAY_SIZE(mmc3_pads),
671 .clkid = MXC_ESDHC4_CLK,
673 .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
681 .num_pads = ARRAY_SIZE(mmc0_pads),
682 .clkid = MXC_ESDHC_CLK,
684 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
687 .cd_gpio = IMX_GPIO_NR(7, 2),
691 .num_pads = ARRAY_SIZE(mmc1_pads),
692 .clkid = MXC_ESDHC2_CLK,
694 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
697 .cd_gpio = IMX_GPIO_NR(7, 3),
701 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
703 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
706 int board_mmc_getcd(struct mmc *mmc)
708 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
710 if (cfg->cd_gpio < 0)
713 debug("SD card %d is %spresent (GPIO %d)\n",
714 cfg - tx6qdl_esdhc_cfg,
715 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
717 return !gpio_get_value(cfg->cd_gpio);
720 int board_mmc_init(bd_t *bis)
724 debug("%s@%d: \n", __func__, __LINE__);
726 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
728 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
731 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
732 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
734 if (cfg->cd_gpio >= 0) {
735 ret = gpio_request_one(cfg->cd_gpio,
736 GPIOFLAG_INPUT, "MMC CD");
738 printf("Error %d requesting GPIO%d_%d\n",
739 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
744 debug("%s: Initializing MMC slot %d\n", __func__, i);
745 fsl_esdhc_initialize(bis, &cfg->cfg);
747 mmc = find_mmc_device(i);
750 if (board_mmc_getcd(mmc))
755 #endif /* CONFIG_CMD_MMC */
757 #ifdef CONFIG_FEC_MXC
763 int board_eth_init(bd_t *bis)
767 debug("%s@%d: \n", __func__, __LINE__);
769 /* delay at least 21ms for the PHY internal POR signal to deassert */
772 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
773 ARRAY_SIZE(tx6qdl_fec_pads));
775 /* Deassert RESET to the external phy */
776 gpio_set_value(TX6_FEC_RST_GPIO, 1);
778 ret = cpu_eth_init(bis);
780 printf("cpu_eth_init() failed: %d\n", ret);
785 static void tx6_init_mac(void)
789 imx_get_mac_from_fuse(0, mac);
790 if (!is_valid_ethaddr(mac)) {
791 printf("No valid MAC address programmed\n");
795 printf("MAC addr from fuse: %pM\n", mac);
796 eth_setenv_enetaddr("ethaddr", mac);
799 static inline void tx6_init_mac(void)
802 #endif /* CONFIG_FEC_MXC */
810 static inline int calc_blink_rate(void)
812 if (!tx6_temp_check_enabled)
813 return CONFIG_SYS_HZ;
815 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
816 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
817 (TEMPERATURE_HOT - TEMPERATURE_MIN);
820 void show_activity(int arg)
822 static int led_state = LED_STATE_INIT;
823 static int blink_rate;
826 if (led_state == LED_STATE_INIT) {
828 gpio_set_value(TX6_LED_GPIO, 1);
829 led_state = LED_STATE_ON;
830 blink_rate = calc_blink_rate();
832 if (get_timer(last) > blink_rate) {
833 blink_rate = calc_blink_rate();
834 last = get_timer_masked();
835 if (led_state == LED_STATE_ON) {
836 gpio_set_value(TX6_LED_GPIO, 0);
838 gpio_set_value(TX6_LED_GPIO, 1);
840 led_state = 1 - led_state;
845 static const iomux_v3_cfg_t stk5_pads[] = {
846 /* SW controlled LED on STK5 baseboard */
847 MX6_PAD_EIM_A18__GPIO2_IO20 | TX6_GPIO_PAD_CTRL,
849 /* I2C bus on DIMM pins 40/41 */
850 MX6_PAD_GPIO_6__I2C3_SDA | TX6_I2C_PAD_CTRL,
851 MX6_PAD_GPIO_3__I2C3_SCL | TX6_I2C_PAD_CTRL,
853 /* TSC200x PEN IRQ */
854 MX6_PAD_EIM_D26__GPIO3_IO26 | TX6_GPIO_PAD_CTRL,
856 /* EDT-FT5x06 Polytouch panel */
857 MX6_PAD_NANDF_CS2__GPIO6_IO15 | TX6_GPIO_PAD_CTRL, /* IRQ */
858 MX6_PAD_EIM_A16__GPIO2_IO22 | TX6_GPIO_PAD_CTRL, /* RESET */
859 MX6_PAD_EIM_A17__GPIO2_IO21 | TX6_GPIO_PAD_CTRL, /* WAKE */
862 MX6_PAD_EIM_D31__GPIO3_IO31 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
863 MX6_PAD_EIM_D30__GPIO3_IO30 | TX6_GPIO_PAD_CTRL, /* OC */
865 MX6_PAD_EIM_D23__GPIO3_IO23 | TX6_GPIO_PAD_CTRL, /* USBOTG ID */
866 MX6_PAD_GPIO_7__GPIO1_IO07 | TX6_GPIO_PAD_CTRL, /* VBUSEN */
867 MX6_PAD_GPIO_8__GPIO1_IO08 | TX6_GPIO_PAD_CTRL, /* OC */
870 static const struct gpio stk5_gpios[] = {
871 { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
873 { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
874 { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
875 { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
876 { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
877 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
881 vidinfo_t panel_info = {
882 /* set to max. size supported by SoC */
886 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
889 static struct fb_videomode tx6_fb_modes[] = {
891 /* Standard VGA timing */
896 .pixclock = KHZ2PICOS(25175),
903 .sync = FB_SYNC_CLK_LAT_FALL,
906 /* Emerging ETV570 640 x 480 display. Syncs low active,
907 * DE high active, 115.2 mm x 86.4 mm display area
908 * VGA compatible timing
914 .pixclock = KHZ2PICOS(25175),
921 .sync = FB_SYNC_CLK_LAT_FALL,
924 /* Emerging ETM0700G0DH6 800 x 480 display.
925 * 152.4 mm x 91.44 mm display area.
931 .pixclock = KHZ2PICOS(33260),
938 .sync = FB_SYNC_CLK_LAT_FALL,
940 #ifndef CONFIG_SYS_LVDS_IF
942 /* Emerging ET0350G0DH6 320 x 240 display.
943 * 70.08 mm x 52.56 mm display area.
949 .pixclock = KHZ2PICOS(6500),
956 .sync = FB_SYNC_CLK_LAT_FALL,
959 /* Emerging ET0430G0DH6 480 x 272 display.
960 * 95.04 mm x 53.856 mm display area.
966 .pixclock = KHZ2PICOS(9000),
975 /* Emerging ET0500G0DH6 800 x 480 display.
976 * 109.6 mm x 66.4 mm display area.
982 .pixclock = KHZ2PICOS(33260),
989 .sync = FB_SYNC_CLK_LAT_FALL,
992 /* Emerging ETQ570G0DH6 320 x 240 display.
993 * 115.2 mm x 86.4 mm display area.
999 .pixclock = KHZ2PICOS(6400),
1003 .upper_margin = 16, /* 15 according to datasheet */
1004 .vsync_len = 3, /* TVP -> 1>x>5 */
1005 .lower_margin = 4, /* 4.5 according to datasheet */
1006 .sync = FB_SYNC_CLK_LAT_FALL,
1010 /* HannStar HSD100PXN1
1011 * 202.7m mm x 152.06 mm display area.
1013 .name = "HSD100PXN1",
1017 .pixclock = KHZ2PICOS(65000),
1020 .right_margin = 320,
1024 .sync = FB_SYNC_CLK_LAT_FALL,
1028 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1036 .sync = FB_SYNC_CLK_LAT_FALL,
1040 static int lcd_enabled = 1;
1041 static int lcd_bl_polarity;
1043 static int lcd_backlight_polarity(void)
1045 return lcd_bl_polarity;
1048 void lcd_enable(void)
1051 * global variable from common/lcd.c
1052 * Set to 0 here to prevent messages from going to LCD
1053 * rather than serial console
1058 karo_load_splashimage(1);
1060 debug("Switching LCD on\n");
1061 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1063 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1065 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1066 lcd_backlight_polarity());
1070 void lcd_disable(void)
1073 printf("Disabling LCD\n");
1074 ipuv3_fb_shutdown();
1078 void lcd_panel_disable(void)
1081 debug("Switching LCD off\n");
1082 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1083 !lcd_backlight_polarity());
1084 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1085 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1089 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1091 MX6_PAD_EIM_D29__GPIO3_IO29 | TX6_GPIO_PAD_CTRL,
1092 /* LCD POWER_ENABLE */
1093 MX6_PAD_EIM_EB3__GPIO2_IO31 | TX6_GPIO_PAD_CTRL,
1094 /* LCD Backlight (PWM) */
1095 MX6_PAD_GPIO_1__GPIO1_IO01 | TX6_GPIO_PAD_CTRL,
1097 #ifndef CONFIG_SYS_LVDS_IF
1099 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | TX6_GPIO_PAD_CTRL,
1100 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | TX6_GPIO_PAD_CTRL,
1101 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | TX6_GPIO_PAD_CTRL,
1102 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | TX6_GPIO_PAD_CTRL,
1103 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | TX6_GPIO_PAD_CTRL,
1104 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | TX6_GPIO_PAD_CTRL,
1105 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | TX6_GPIO_PAD_CTRL,
1106 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | TX6_GPIO_PAD_CTRL,
1107 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | TX6_GPIO_PAD_CTRL,
1108 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | TX6_GPIO_PAD_CTRL,
1109 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | TX6_GPIO_PAD_CTRL,
1110 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | TX6_GPIO_PAD_CTRL,
1111 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | TX6_GPIO_PAD_CTRL,
1112 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | TX6_GPIO_PAD_CTRL,
1113 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | TX6_GPIO_PAD_CTRL,
1114 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | TX6_GPIO_PAD_CTRL,
1115 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | TX6_GPIO_PAD_CTRL,
1116 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | TX6_GPIO_PAD_CTRL,
1117 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | TX6_GPIO_PAD_CTRL,
1118 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | TX6_GPIO_PAD_CTRL,
1119 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | TX6_GPIO_PAD_CTRL,
1120 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | TX6_GPIO_PAD_CTRL,
1121 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | TX6_GPIO_PAD_CTRL,
1122 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | TX6_GPIO_PAD_CTRL,
1123 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | TX6_GPIO_PAD_CTRL, /* HSYNC */
1124 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | TX6_GPIO_PAD_CTRL, /* VSYNC */
1125 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | TX6_GPIO_PAD_CTRL, /* OE_ACD */
1126 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | TX6_GPIO_PAD_CTRL, /* LSCLK */
1130 static const struct gpio stk5_lcd_gpios[] = {
1131 { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1132 { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1133 { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1136 void lcd_ctrl_init(void *lcdbase)
1138 int color_depth = 24;
1139 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1143 struct fb_videomode *p = &tx6_fb_modes[0];
1144 struct fb_videomode fb_mode;
1145 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1148 unsigned long di_clk_rate = 65000000;
1151 debug("LCD disabled\n");
1155 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1156 debug("Disabling LCD\n");
1158 setenv("splashimage", NULL);
1162 karo_fdt_move_fdt();
1163 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1165 if (video_mode == NULL) {
1166 debug("Disabling LCD\n");
1171 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1173 debug("Using video mode from FDT\n");
1175 if (fb_mode.xres > panel_info.vl_col ||
1176 fb_mode.yres > panel_info.vl_row) {
1177 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1178 fb_mode.xres, fb_mode.yres,
1179 panel_info.vl_col, panel_info.vl_row);
1184 if (p->name != NULL)
1185 debug("Trying compiled-in video modes\n");
1186 while (p->name != NULL) {
1187 if (strcmp(p->name, vm) == 0) {
1188 debug("Using video mode: '%s'\n", p->name);
1195 debug("Trying to decode video_mode: '%s'\n", vm);
1196 while (*vm != '\0') {
1197 if (*vm >= '0' && *vm <= '9') {
1200 val = simple_strtoul(vm, &end, 0);
1203 if (val > panel_info.vl_col)
1204 val = panel_info.vl_col;
1206 panel_info.vl_col = val;
1208 } else if (!yres_set) {
1209 if (val > panel_info.vl_row)
1210 val = panel_info.vl_row;
1212 panel_info.vl_row = val;
1214 } else if (!bpp_set) {
1219 pix_fmt = IPU_PIX_FMT_LVDS888;
1233 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1234 end - vm, vm, color_depth);
1237 } else if (!refresh_set) {
1264 if (p->xres == 0 || p->yres == 0) {
1265 printf("Invalid video mode: %s\n", getenv("video_mode"));
1267 printf("Supported video modes are:");
1268 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1269 printf(" %s", p->name);
1274 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1275 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1276 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1280 panel_info.vl_col = p->xres;
1281 panel_info.vl_row = p->yres;
1283 switch (color_depth) {
1285 panel_info.vl_bpix = LCD_COLOR8;
1288 panel_info.vl_bpix = LCD_COLOR16;
1291 panel_info.vl_bpix = LCD_COLOR32;
1294 p->pixclock = KHZ2PICOS(refresh *
1295 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1296 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1298 debug("Pixel clock set to %lu.%03lu MHz\n",
1299 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1301 if (p != &fb_mode) {
1304 debug("Creating new display-timing node from '%s'\n",
1306 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1308 printf("Failed to create new display-timing node from '%s': %d\n",
1312 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1313 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1314 ARRAY_SIZE(stk5_lcd_pads));
1316 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1317 switch (lcd_bus_width) {
1319 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1323 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1328 pix_fmt = IPU_PIX_FMT_RGB565;
1334 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1339 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1340 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1344 if (lvds_chan_mask == 0) {
1345 printf("No LVDS channel active\n");
1350 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1351 if (lcd_bus_width == 24)
1352 gpr2 |= (1 << 5) | (1 << 7);
1353 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1354 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1355 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1356 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1358 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1359 gpr3 &= ~((3 << 8) | (3 << 6));
1360 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1362 if (karo_load_splashimage(0) == 0) {
1365 debug("Initializing LCD controller\n");
1366 ret = ipuv3_fb_init(p, 0, pix_fmt,
1367 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1370 printf("Failed to initialize FB driver: %d\n", ret);
1374 debug("Skipping initialization of LCD controller\n");
1380 panel_info.vl_col = 0;
1381 panel_info.vl_row = 0;
1385 #define lcd_enabled 0
1386 #endif /* CONFIG_LCD */
1388 static void stk5_board_init(void)
1392 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1394 printf("Failed to request stk5_gpios: %d\n", ret);
1397 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1400 static void stk5v3_board_init(void)
1405 static void stk5v5_board_init(void)
1411 ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1412 "Flexcan Transceiver");
1414 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1418 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21 |
1422 static void tx6qdl_set_cpu_clock(void)
1424 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1426 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1429 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1430 printf("%s detected; skipping cpu clock change\n",
1431 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1434 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1435 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1436 printf("CPU clock set to %lu.%03lu MHz\n",
1437 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1439 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1443 int board_late_init(void)
1445 const char *baseboard;
1447 debug("%s@%d: \n", __func__, __LINE__);
1451 if (tx6_temp_check_enabled)
1452 check_cpu_temperature(1);
1454 tx6qdl_set_cpu_clock();
1457 setenv_ulong("safeboot", 1);
1458 else if (wrsr & WRSR_TOUT)
1459 setenv_ulong("wdreset", 1);
1461 karo_fdt_move_fdt();
1463 baseboard = getenv("baseboard");
1467 printf("Baseboard: %s\n", baseboard);
1469 if (strncmp(baseboard, "stk5", 4) == 0) {
1470 if ((strlen(baseboard) == 4) ||
1471 strcmp(baseboard, "stk5-v3") == 0) {
1472 stk5v3_board_init();
1473 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1474 const char *otg_mode = getenv("otg_mode");
1476 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1477 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1478 otg_mode, baseboard);
1479 setenv("otg_mode", "none");
1481 stk5v5_board_init();
1483 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1487 printf("WARNING: Unsupported baseboard: '%s'\n",
1496 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1501 #ifdef CONFIG_SERIAL_TAG
1502 void get_board_serial(struct tag_serialnr *serialnr)
1504 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1505 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1507 serialnr->low = readl(&fuse->cfg0);
1508 serialnr->high = readl(&fuse->cfg1);
1512 #if defined(CONFIG_OF_BOARD_SETUP)
1513 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1514 #include <jffs2/jffs2.h>
1515 #include <mtd_node.h>
1516 static struct node_info nodes[] = {
1517 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1520 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1523 static const char *tx6_touchpanels[] = {
1529 int ft_board_setup(void *blob, bd_t *bd)
1531 const char *baseboard = getenv("baseboard");
1532 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1533 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1536 ret = fdt_increase_size(blob, 4096);
1538 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1542 karo_fdt_enable_node(blob, "stk5led", 0);
1544 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1546 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1547 ARRAY_SIZE(tx6_touchpanels));
1548 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1549 karo_fdt_fixup_flexcan(blob, stk5_v5);
1551 #ifdef CONFIG_SYS_LVDS_IF
1552 karo_fdt_update_fb_mode(blob, video_mode, "/lvds0-panel");
1553 karo_fdt_update_fb_mode(blob, video_mode, "/lvds1-panel");
1555 karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1559 #endif /* CONFIG_OF_BOARD_SETUP */