2 * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5)
38 #define TX6UL_FEC2_RST_GPIO IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO IMX_GPIO_NR(4, 27)
41 #define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9)
43 #define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
47 #ifdef CONFIG_SYS_I2C_SOFT
48 #define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL
49 #define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA
52 #define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
57 #define TEMPERATURE_MIN (-40)
59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
62 #define TEMPERATURE_HOT 80
65 DECLARE_GLOBAL_DATA_PTR;
67 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
70 #ifdef CONFIG_SECURE_BOOT
71 char __csf_data[0] __attribute__((section(".__csf_data")));
74 #define TX6UL_DEFAULT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP | \
78 #define TX6UL_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
84 #define TX6UL_I2C_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | \
88 #define TX6UL_ENET_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH | \
90 PAD_CTL_PUS_100K_UP | \
92 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
95 #define TX6UL_GPIO_IN_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW | \
99 static const iomux_v3_cfg_t const tx6ul_pads[] = {
101 #if CONFIG_MXC_UART_BASE == UART1_BASE
102 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
103 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
104 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
105 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
107 #if CONFIG_MXC_UART_BASE == UART2_BASE
108 MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
109 MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
110 MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
111 MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
113 #if CONFIG_MXC_UART_BASE == UART5_BASE
114 MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
115 MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
116 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
117 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
119 /* FEC PHY GPIO functions */
120 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
121 MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
122 MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
125 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
127 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
129 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
130 PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED),
131 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
132 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
133 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST),
134 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
135 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
136 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
137 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
138 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
139 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
140 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
143 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
144 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
145 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
146 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
147 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
148 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
149 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
150 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
151 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
152 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
153 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
156 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
158 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
159 TX6UL_I2C_PAD_CTRL, /* I2C SCL */
160 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
161 TX6UL_I2C_PAD_CTRL, /* I2C SDA */
164 static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
165 /* internal I2C set up for I2C bus recovery */
166 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
167 TX6UL_I2C_PAD_CTRL, /* I2C SCL */
168 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
169 TX6UL_I2C_PAD_CTRL, /* I2C SDA */
172 static const struct gpio const tx6ul_gpios[] = {
173 #ifdef CONFIG_SYS_I2C_SOFT
174 /* These two entries are used to forcefully reinitialize the I2C bus */
175 { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
176 { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
178 { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
179 { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
180 { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
183 static const struct gpio const tx6ul_fec2_gpios[] = {
184 { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
185 { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
192 /* run with default environment */
193 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
194 #define SCL_BANK (TX6UL_I2C1_SCL_GPIO / 32)
195 #define SDA_BANK (TX6UL_I2C1_SDA_GPIO / 32)
196 #define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
197 #define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
199 static void * const gpio_ports[] = {
200 (void *)GPIO1_BASE_ADDR,
201 (void *)GPIO2_BASE_ADDR,
202 (void *)GPIO3_BASE_ADDR,
203 (void *)GPIO4_BASE_ADDR,
204 (void *)GPIO5_BASE_ADDR,
207 static void tx6ul_i2c_recover(void)
211 struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
212 struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
214 if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
215 (readl(&sda_regs->gpio_psr) & SDA_BIT))
218 debug("Clearing I2C bus\n");
219 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
220 printf("I2C SCL stuck LOW\n");
223 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
224 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
226 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
227 MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
229 if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
230 printf("I2C SDA stuck LOW\n");
233 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
234 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
235 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
237 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
238 ARRAY_SIZE(tx6ul_i2c_gpio_pads));
242 for (i = 0; i < 18; i++) {
243 u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
245 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
246 writel(reg, &scl_regs->gpio_dr);
249 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
251 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
258 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
259 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
262 printf("I2C bus recovery succeeded\n");
264 printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
267 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
268 ARRAY_SIZE(tx6ul_i2c_pads));
272 static inline void tx6ul_i2c_recover(void)
277 /* placed in section '.data' to prevent overwriting relocation info
280 static u32 wrsr __data;
282 #define WRSR_POR (1 << 4)
283 #define WRSR_TOUT (1 << 1)
284 #define WRSR_SFTW (1 << 0)
286 static void print_reset_cause(void)
288 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
289 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
293 printf("Reset cause: ");
295 srsr = readl(&src_regs->srsr);
296 wrsr = readw(wdt_base + 4);
298 if (wrsr & WRSR_POR) {
299 printf("%sPOR", dlm);
302 if (srsr & 0x00004) {
303 printf("%sCSU", dlm);
306 if (srsr & 0x00008) {
307 printf("%sIPP USER", dlm);
310 if (srsr & 0x00010) {
311 if (wrsr & WRSR_SFTW) {
312 printf("%sSOFT", dlm);
315 if (wrsr & WRSR_TOUT) {
316 printf("%sWDOG", dlm);
320 if (srsr & 0x00020) {
321 printf("%sJTAG HIGH-Z", dlm);
324 if (srsr & 0x00040) {
325 printf("%sJTAG SW", dlm);
328 if (srsr & 0x10000) {
329 printf("%sWARM BOOT", dlm);
338 #ifdef CONFIG_IMX6_THERMAL
340 #include <imx_thermal.h>
343 static void print_temperature(void)
345 struct udevice *thermal_dev;
346 int cpu_tmp, minc, maxc, ret;
347 char const *grade_str;
348 static u32 __data thermal_calib;
350 puts("Temperature: ");
351 switch (get_cpu_temp_grade(&minc, &maxc)) {
352 case TEMP_AUTOMOTIVE:
353 grade_str = "Automotive";
355 case TEMP_INDUSTRIAL:
356 grade_str = "Industrial";
358 case TEMP_EXTCOMMERCIAL:
359 grade_str = "Extended Commercial";
362 grade_str = "Commercial";
364 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
365 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
367 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
370 printf(" at %dC", cpu_tmp);
372 puts(" - failed to read sensor data");
374 puts(" - no sensor device found");
377 if (fuse_read(1, 6, &thermal_calib) == 0) {
378 printf(" - calibration data 0x%08x\n", thermal_calib);
380 puts(" - Failed to read thermal calib fuse\n");
384 static inline void print_temperature(void)
391 u32 cpurev = get_cpu_rev();
394 if (is_cpu_type(MXC_CPU_MX6SL))
396 else if (is_cpu_type(MXC_CPU_MX6DL))
398 else if (is_cpu_type(MXC_CPU_MX6SOLO))
400 else if (is_cpu_type(MXC_CPU_MX6Q))
402 else if (is_cpu_type(MXC_CPU_MX6UL))
404 else if (is_cpu_type(MXC_CPU_MX6ULL))
407 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
409 (cpurev & 0x000F0) >> 4,
410 (cpurev & 0x0000F) >> 0,
411 mxc_get_clock(MXC_ARM_CLK) / 1000000);
415 #ifdef CONFIG_MX6_TEMPERATURE_HOT
416 check_cpu_temperature(1);
422 /* serial port not initialized at this point */
423 int board_early_init_f(void)
428 #ifndef CONFIG_MX6_TEMPERATURE_HOT
429 static bool tx6ul_temp_check_enabled = true;
431 #define tx6ul_temp_check_enabled 0
434 static inline u8 tx6ul_mem_suffix(void)
436 return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
437 IS_ENABLED(CONFIG_TX6_EMMC);
440 #ifdef CONFIG_RN5T567
442 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
443 #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
444 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
445 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
446 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
447 #define VDD_IO_EXT_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
448 #define VDD_IO_EXT_VAL_LP rn5t_mV_to_regval(3300)
449 #define VDD_IO_INT_VAL rn5t_mV_to_regval2(3300) /* LDO1 */
450 #define VDD_IO_INT_VAL_LP rn5t_mV_to_regval2(3300)
451 #define VDD_ADC_VAL rn5t_mV_to_regval2(3300) /* LDO2 */
452 #define VDD_ADC_VAL_LP rn5t_mV_to_regval2(3300)
453 #define VDD_PMIC_VAL rn5t_mV_to_regval2(2500) /* LDO3 */
454 #define VDD_PMIC_VAL_LP rn5t_mV_to_regval2(2500)
455 #define VDD_CSI_VAL rn5t_mV_to_regval2(1800) /* LDO4 */
456 #define VDD_CSI_VAL_LP rn5t_mV_to_regval2(1800)
458 static struct pmic_regs rn5t567_regs[] = {
459 { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
460 { RN5T567_DC1DAC, VDD_CORE_VAL, },
461 { RN5T567_DC3DAC, VDD_DDR_VAL, },
462 { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
463 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
464 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
465 { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
466 { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
467 { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
468 { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
469 { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
470 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
471 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
472 { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
473 { RN5T567_LDO2DAC, VDD_ADC_VAL, },
474 { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
475 { RN5T567_LDO4DAC, VDD_CSI_VAL, },
476 { RN5T567_LDOEN1, 0x0f, ~0x1f, },
477 { RN5T567_LDOEN2, 0x10, ~0x30, },
478 { RN5T567_LDODIS, 0x10, ~0x1f, },
479 { RN5T567_INTPOL, 0, },
480 { RN5T567_INTEN, 0x3, },
481 { RN5T567_IREN, 0xf, },
482 { RN5T567_EN_GPIR, 0, },
485 static int pmic_addr = 0x33;
491 u32 cpurev = get_cpu_rev();
494 if (is_cpu_type(MXC_CPU_MX6UL))
495 f = ((cpurev & 0xf0) > 0x10) ? '5' : '0';
496 else if (is_cpu_type(MXC_CPU_MX6ULL))
499 debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
501 printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
505 ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
507 printf("Failed to request tx6ul_gpios: %d\n", ret);
509 imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
511 /* Address of boot parameters */
512 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
513 gd->bd->bi_arch_number = -1;
515 if (ctrlc() || (wrsr & WRSR_TOUT)) {
516 if (wrsr & WRSR_TOUT)
517 printf("WDOG RESET detected; Skipping PMIC setup\n");
519 printf("<CTRL-C> detected; safeboot enabled\n");
520 #ifndef CONFIG_MX6_TEMPERATURE_HOT
521 tx6ul_temp_check_enabled = false;
526 ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
528 printf("Failed to setup PMIC voltages: %d\n", ret);
536 debug("%s@%d: \n", __func__, __LINE__);
538 /* dram_init must store complete ramsize in gd->ram_size */
539 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
540 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
544 void dram_init_banksize(void)
546 debug("%s@%d: \n", __func__, __LINE__);
548 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
549 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
551 #if CONFIG_NR_DRAM_BANKS > 1
552 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
553 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
558 #ifdef CONFIG_FSL_ESDHC
559 #define TX6UL_SD_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP | \
560 PAD_CTL_SPEED_MED | \
561 PAD_CTL_DSE_40ohm | \
564 static const iomux_v3_cfg_t mmc0_pads[] = {
565 MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
566 MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
567 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
568 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
569 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
570 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
572 MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
575 #ifdef CONFIG_TX6_EMMC
576 static const iomux_v3_cfg_t mmc1_pads[] = {
577 MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
578 MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
579 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
580 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
581 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
582 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
584 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
589 static struct tx6ul_esdhc_cfg {
590 const iomux_v3_cfg_t *pads;
592 enum mxc_clock clkid;
593 struct fsl_esdhc_cfg cfg;
595 } tx6ul_esdhc_cfg[] = {
596 #ifdef CONFIG_TX6_EMMC
599 .num_pads = ARRAY_SIZE(mmc1_pads),
600 .clkid = MXC_ESDHC2_CLK,
602 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
610 .num_pads = ARRAY_SIZE(mmc0_pads),
611 .clkid = MXC_ESDHC_CLK,
613 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
616 .cd_gpio = TX6UL_SD1_CD_GPIO,
620 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
622 return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
625 int board_mmc_getcd(struct mmc *mmc)
627 struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
629 if (cfg->cd_gpio < 0)
632 debug("SD card %d is %spresent (GPIO %d)\n",
633 cfg - tx6ul_esdhc_cfg,
634 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
636 return !gpio_get_value(cfg->cd_gpio);
639 int board_mmc_init(bd_t *bis)
643 debug("%s@%d: \n", __func__, __LINE__);
645 #ifndef CONFIG_ENV_IS_IN_MMC
646 if (!(gd->flags & GD_FLG_ENV_READY)) {
647 printf("deferred ...");
651 for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
653 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
656 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
657 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
659 if (cfg->cd_gpio >= 0) {
660 ret = gpio_request_one(cfg->cd_gpio,
661 GPIOFLAG_INPUT, "MMC CD");
663 printf("Error %d requesting GPIO%d_%d\n",
664 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
669 debug("%s: Initializing MMC slot %d\n", __func__, i);
670 fsl_esdhc_initialize(bis, &cfg->cfg);
672 mmc = find_mmc_device(i);
675 if (board_mmc_getcd(mmc))
680 #endif /* CONFIG_FSL_ESDHC */
689 static inline int calc_blink_rate(void)
691 if (!tx6ul_temp_check_enabled)
692 return CONFIG_SYS_HZ;
694 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
695 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
696 (TEMPERATURE_HOT - TEMPERATURE_MIN);
699 void show_activity(int arg)
701 static int led_state = LED_STATE_INIT;
702 static int blink_rate;
712 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
714 led_state = LED_STATE_ERR;
716 led_state = LED_STATE_ON;
717 blink_rate = calc_blink_rate();
722 if (get_timer(last) > blink_rate) {
723 blink_rate = calc_blink_rate();
724 last = get_timer_masked();
725 if (led_state == LED_STATE_ON) {
726 gpio_set_value(TX6UL_LED_GPIO, 0);
728 gpio_set_value(TX6UL_LED_GPIO, 1);
730 led_state = 1 - led_state;
736 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
737 MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
738 MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
739 MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
740 MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
741 MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
742 MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
745 static const iomux_v3_cfg_t stk5_pads[] = {
746 /* SW controlled LED on STK5 baseboard */
747 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
749 /* I2C bus on DIMM pins 40/41 */
750 MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
751 MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
753 /* TSC200x PEN IRQ */
754 MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
756 /* EDT-FT5x06 Polytouch panel */
757 MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
758 MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
759 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
762 MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
763 MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
766 MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
767 MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
770 static const struct gpio stk5_gpios[] = {
771 { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
773 { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
774 { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
778 vidinfo_t panel_info = {
779 /* set to max. size supported by SoC */
783 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
786 static struct fb_videomode tx6ul_fb_modes[] = {
787 #ifndef CONFIG_SYS_LVDS_IF
789 /* Standard VGA timing */
794 .pixclock = KHZ2PICOS(25175),
801 .sync = FB_SYNC_CLK_LAT_FALL,
804 /* Emerging ETV570 640 x 480 display. Syncs low active,
805 * DE high active, 115.2 mm x 86.4 mm display area
806 * VGA compatible timing
812 .pixclock = KHZ2PICOS(25175),
819 .sync = FB_SYNC_CLK_LAT_FALL,
822 /* Emerging ET0350G0DH6 320 x 240 display.
823 * 70.08 mm x 52.56 mm display area.
829 .pixclock = KHZ2PICOS(6500),
830 .left_margin = 68 - 34,
833 .upper_margin = 18 - 3,
836 .sync = FB_SYNC_CLK_LAT_FALL,
839 /* Emerging ET0430G0DH6 480 x 272 display.
840 * 95.04 mm x 53.856 mm display area.
846 .pixclock = KHZ2PICOS(9000),
855 /* Emerging ET0500G0DH6 800 x 480 display.
856 * 109.6 mm x 66.4 mm display area.
862 .pixclock = KHZ2PICOS(33260),
863 .left_margin = 216 - 128,
865 .right_margin = 1056 - 800 - 216,
866 .upper_margin = 35 - 2,
868 .lower_margin = 525 - 480 - 35,
869 .sync = FB_SYNC_CLK_LAT_FALL,
872 /* Emerging ETQ570G0DH6 320 x 240 display.
873 * 115.2 mm x 86.4 mm display area.
879 .pixclock = KHZ2PICOS(6400),
883 .upper_margin = 16, /* 15 according to datasheet */
884 .vsync_len = 3, /* TVP -> 1>x>5 */
885 .lower_margin = 4, /* 4.5 according to datasheet */
886 .sync = FB_SYNC_CLK_LAT_FALL,
889 /* Emerging ET0700G0DH6 800 x 480 display.
890 * 152.4 mm x 91.44 mm display area.
896 .pixclock = KHZ2PICOS(33260),
897 .left_margin = 216 - 128,
899 .right_margin = 1056 - 800 - 216,
900 .upper_margin = 35 - 2,
902 .lower_margin = 525 - 480 - 35,
903 .sync = FB_SYNC_CLK_LAT_FALL,
906 /* Emerging ET070001DM6 800 x 480 display.
907 * 152.4 mm x 91.44 mm display area.
909 .name = "ET070001DM6",
913 .pixclock = KHZ2PICOS(33260),
914 .left_margin = 216 - 128,
916 .right_margin = 1056 - 800 - 216,
917 .upper_margin = 35 - 2,
919 .lower_margin = 525 - 480 - 35,
924 /* HannStar HSD100PXN1
925 * 202.7m mm x 152.06 mm display area.
927 .name = "HSD100PXN1",
931 .pixclock = KHZ2PICOS(65000),
938 .sync = FB_SYNC_CLK_LAT_FALL,
942 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
950 .sync = FB_SYNC_CLK_LAT_FALL,
954 static int lcd_enabled = 1;
955 static int lcd_bl_polarity;
957 static int lcd_backlight_polarity(void)
959 return lcd_bl_polarity;
962 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
965 MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
966 /* LCD POWER_ENABLE */
967 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
968 /* LCD Backlight (PWM) */
969 MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
971 MX6_PAD_LCD_DATA00__LCDIF_DATA00,
972 MX6_PAD_LCD_DATA01__LCDIF_DATA01,
973 MX6_PAD_LCD_DATA02__LCDIF_DATA02,
974 MX6_PAD_LCD_DATA03__LCDIF_DATA03,
975 MX6_PAD_LCD_DATA04__LCDIF_DATA04,
976 MX6_PAD_LCD_DATA05__LCDIF_DATA05,
977 MX6_PAD_LCD_DATA06__LCDIF_DATA06,
978 MX6_PAD_LCD_DATA07__LCDIF_DATA07,
979 MX6_PAD_LCD_DATA08__LCDIF_DATA08,
980 MX6_PAD_LCD_DATA09__LCDIF_DATA09,
981 MX6_PAD_LCD_DATA10__LCDIF_DATA10,
982 MX6_PAD_LCD_DATA11__LCDIF_DATA11,
983 MX6_PAD_LCD_DATA12__LCDIF_DATA12,
984 MX6_PAD_LCD_DATA13__LCDIF_DATA13,
985 MX6_PAD_LCD_DATA14__LCDIF_DATA14,
986 MX6_PAD_LCD_DATA15__LCDIF_DATA15,
987 MX6_PAD_LCD_DATA16__LCDIF_DATA16,
988 MX6_PAD_LCD_DATA17__LCDIF_DATA17,
989 MX6_PAD_LCD_DATA18__LCDIF_DATA18,
990 MX6_PAD_LCD_DATA19__LCDIF_DATA19,
991 MX6_PAD_LCD_DATA20__LCDIF_DATA20,
992 MX6_PAD_LCD_DATA21__LCDIF_DATA21,
993 MX6_PAD_LCD_DATA22__LCDIF_DATA22,
994 MX6_PAD_LCD_DATA23__LCDIF_DATA23,
995 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
996 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
997 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
998 MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1002 static const struct gpio stk5_lcd_gpios[] = {
1003 { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1004 { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1005 { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1008 /* run with valid env from NAND/eMMC */
1009 void lcd_enable(void)
1012 * global variable from common/lcd.c
1013 * Set to 0 here to prevent messages from going to LCD
1014 * rather than serial console
1019 karo_load_splashimage(1);
1021 debug("Switching LCD on\n");
1022 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1024 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1026 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1027 lcd_backlight_polarity());
1031 static void lcd_disable(void)
1034 printf("Disabling LCD\n");
1035 panel_info.vl_row = 0;
1040 void lcd_ctrl_init(void *lcdbase)
1042 int color_depth = 24;
1043 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1047 struct fb_videomode *p = &tx6ul_fb_modes[0];
1048 struct fb_videomode fb_mode;
1049 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1052 debug("LCD disabled\n");
1056 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1058 setenv("splashimage", NULL);
1062 karo_fdt_move_fdt();
1063 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1065 if (video_mode == NULL) {
1070 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1072 debug("Using video mode from FDT\n");
1074 if (fb_mode.xres > panel_info.vl_col ||
1075 fb_mode.yres > panel_info.vl_row) {
1076 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1077 fb_mode.xres, fb_mode.yres,
1078 panel_info.vl_col, panel_info.vl_row);
1083 if (p->name != NULL)
1084 debug("Trying compiled-in video modes\n");
1085 while (p->name != NULL) {
1086 if (strcmp(p->name, vm) == 0) {
1087 debug("Using video mode: '%s'\n", p->name);
1094 debug("Trying to decode video_mode: '%s'\n", vm);
1095 while (*vm != '\0') {
1096 if (*vm >= '0' && *vm <= '9') {
1099 val = simple_strtoul(vm, &end, 0);
1102 if (val > panel_info.vl_col)
1103 val = panel_info.vl_col;
1105 panel_info.vl_col = val;
1107 } else if (!yres_set) {
1108 if (val > panel_info.vl_row)
1109 val = panel_info.vl_row;
1111 panel_info.vl_row = val;
1113 } else if (!bpp_set) {
1124 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1125 end - vm, vm, color_depth);
1128 } else if (!refresh_set) {
1155 if (p->xres == 0 || p->yres == 0) {
1156 printf("Invalid video mode: %s\n", getenv("video_mode"));
1158 printf("Supported video modes are:");
1159 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1160 printf(" %s", p->name);
1165 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1166 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1167 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1171 panel_info.vl_col = p->xres;
1172 panel_info.vl_row = p->yres;
1174 switch (color_depth) {
1176 panel_info.vl_bpix = LCD_COLOR8;
1179 panel_info.vl_bpix = LCD_COLOR16;
1182 panel_info.vl_bpix = LCD_COLOR32;
1185 p->pixclock = KHZ2PICOS(refresh *
1186 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1187 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1189 debug("Pixel clock set to %lu.%03lu MHz\n",
1190 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1192 if (p != &fb_mode) {
1195 debug("Creating new display-timing node from '%s'\n",
1197 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1199 printf("Failed to create new display-timing node from '%s': %d\n",
1203 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1204 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1205 ARRAY_SIZE(stk5_lcd_pads));
1207 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1208 color_depth, refresh);
1210 if (karo_load_splashimage(0) == 0) {
1213 /* setup env variable for mxsfb display driver */
1214 snprintf(vmode, sizeof(vmode),
1215 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1216 p->xres, p->yres, p->left_margin, p->right_margin,
1217 p->upper_margin, p->lower_margin, p->hsync_len,
1218 p->vsync_len, p->sync, p->pixclock, color_depth);
1219 setenv("videomode", vmode);
1221 debug("Initializing LCD controller\n");
1224 setenv("videomode", NULL);
1226 debug("Skipping initialization of LCD controller\n");
1230 #define lcd_enabled 0
1231 #endif /* CONFIG_LCD */
1233 #ifndef CONFIG_ENV_IS_IN_MMC
1234 static void tx6ul_mmc_init(void)
1237 if (board_mmc_init(gd->bd) < 0)
1238 cpu_mmc_init(gd->bd);
1239 print_mmc_devices(',');
1242 static inline void tx6ul_mmc_init(void)
1247 static void stk5_board_init(void)
1251 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1253 printf("Failed to request stk5_gpios: %d\n", ret);
1257 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1258 if (getenv_yesno("jtag_enable") != 0) {
1259 /* true if unset or set to one of: 'yYtT1' */
1260 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1263 debug("%s@%d: \n", __func__, __LINE__);
1266 static void stk5v3_board_init(void)
1268 debug("%s@%d: \n", __func__, __LINE__);
1270 debug("%s@%d: \n", __func__, __LINE__);
1274 static void stk5v5_board_init(void)
1281 ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1282 "Flexcan Transceiver");
1284 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1288 imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1289 TX6UL_GPIO_OUT_PAD_CTRL);
1292 static void tx6ul_set_cpu_clock(void)
1294 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1296 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1299 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1300 printf("%s detected; skipping cpu clock change\n",
1301 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1304 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1305 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1306 printf("CPU clock set to %lu.%03lu MHz\n",
1307 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1309 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1313 int board_late_init(void)
1315 const char *baseboard;
1317 debug("%s@%d: \n", __func__, __LINE__);
1321 if (tx6ul_temp_check_enabled)
1322 check_cpu_temperature(1);
1324 tx6ul_set_cpu_clock();
1327 setenv_ulong("safeboot", 1);
1328 else if (wrsr & WRSR_TOUT)
1329 setenv_ulong("wdreset", 1);
1331 karo_fdt_move_fdt();
1333 baseboard = getenv("baseboard");
1337 printf("Baseboard: %s\n", baseboard);
1339 if (strncmp(baseboard, "stk5", 4) == 0) {
1340 if ((strlen(baseboard) == 4) ||
1341 strcmp(baseboard, "stk5-v3") == 0) {
1342 stk5v3_board_init();
1343 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1344 const char *otg_mode = getenv("otg_mode");
1346 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1347 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1348 otg_mode, baseboard);
1349 setenv("otg_mode", "none");
1351 stk5v5_board_init();
1353 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1356 } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1357 const char *otg_mode = getenv("otg_mode");
1359 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1360 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1361 otg_mode, baseboard);
1362 setenv("otg_mode", "none");
1366 printf("WARNING: Unsupported baseboard: '%s'\n",
1373 debug("%s@%d: \n", __func__, __LINE__);
1379 #ifdef CONFIG_FEC_MXC
1385 static void tx6ul_init_mac(void)
1388 const char *baseboard = getenv("baseboard");
1390 imx_get_mac_from_fuse(0, mac);
1391 if (!is_valid_ethaddr(mac)) {
1392 printf("No valid MAC address programmed\n");
1395 printf("MAC addr from fuse: %pM\n", mac);
1396 if (!getenv("ethaddr"))
1397 eth_setenv_enetaddr("ethaddr", mac);
1399 if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1400 setenv("eth1addr", NULL);
1403 if (getenv("eth1addr"))
1405 imx_get_mac_from_fuse(1, mac);
1406 eth_setenv_enetaddr("eth1addr", mac);
1409 int board_eth_init(bd_t *bis)
1415 /* delay at least 21ms for the PHY internal POR signal to deassert */
1418 imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1419 ARRAY_SIZE(tx6ul_enet1_pads));
1421 /* Deassert RESET to the external phys */
1422 gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1424 if (getenv("ethaddr")) {
1425 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1427 printf("failed to initialize FEC0: %d\n", ret);
1431 if (getenv("eth1addr")) {
1432 ret = gpio_request_array(tx6ul_fec2_gpios,
1433 ARRAY_SIZE(tx6ul_fec2_gpios));
1435 printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1437 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1438 ARRAY_SIZE(tx6ul_enet2_pads));
1440 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1442 /* Minimum PHY reset duration */
1444 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1445 /* Wait for PHY internal POR to finish */
1448 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1450 printf("failed to initialize FEC1: %d\n", ret);
1456 #endif /* CONFIG_FEC_MXC */
1458 #ifdef CONFIG_SERIAL_TAG
1459 void get_board_serial(struct tag_serialnr *serialnr)
1461 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1462 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1464 serialnr->low = readl(&fuse->cfg0);
1465 serialnr->high = readl(&fuse->cfg1);
1469 #if defined(CONFIG_OF_BOARD_SETUP)
1470 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1471 #include <jffs2/jffs2.h>
1472 #include <mtd_node.h>
1473 static struct node_info nodes[] = {
1474 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1477 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1480 static const char *tx6ul_touchpanels[] = {
1486 int ft_board_setup(void *blob, bd_t *bd)
1488 const char *baseboard = getenv("baseboard");
1489 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1490 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1493 ret = fdt_increase_size(blob, 4096);
1495 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1499 karo_fdt_enable_node(blob, "stk5led", 0);
1501 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1503 karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1504 ARRAY_SIZE(tx6ul_touchpanels));
1505 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1506 karo_fdt_fixup_flexcan(blob, stk5_v5);
1508 karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1512 #endif /* CONFIG_OF_BOARD_SETUP */