2 #include <asm-offsets.h>
3 #include <configs/tx6.h>
4 #include <linux/linkage.h>
5 #include <asm/arch/imx-regs.h>
6 #include <generated/asm-offsets.h>
9 #error asm-offsets not included
12 #define DEBUG_LED_BIT 20
13 #define LED_GPIO_BASE GPIO2_BASE_ADDR
14 #define LED_MUX_OFFSET 0x0ec
15 #define LED_MUX_MODE 0x15
17 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
19 #ifdef PHYS_SDRAM_2_SIZE
20 #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
22 #define SDRAM_SIZE PHYS_SDRAM_1_SIZE
25 #define CCGR(m) (3 << ((m) * 2))
27 #define CPU_2_BE_32(l) \
28 ((((l) << 24) & 0xFF000000) | \
29 (((l) << 8) & 0x00FF0000) | \
30 (((l) >> 8) & 0x0000FF00) | \
31 (((l) >> 24) & 0x000000FF))
33 #define CHECK_DCD_ADDR(a) ( \
34 ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
35 ((a) >= 0x020E4000 && (a) <= 0x020E7FFF) /* IOMUXC GPR */ || \
36 ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
37 ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
38 ((a) >= 0x021B0000 && (a) <= 0x021B3FFF) /* MMDC */ || \
39 ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
40 ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
41 ((a) >= 0x80000000 && (a) <= 0xFFFF7FFF) /* SDRAM */ || \
42 ((a) >= 0x020D0000 && (a) <= 0x020D3FFF) /* EPIT */)
44 .macro mxc_dcd_item addr, val
45 .ifne CHECK_DCD_ADDR(\addr)
46 .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
48 .error "Address \addr not accessible from DCD"
52 #define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
54 #define MXC_DCD_CMD_SZ_BYTE 1
55 #define MXC_DCD_CMD_SZ_SHORT 2
56 #define MXC_DCD_CMD_SZ_WORD 4
57 #define MXC_DCD_CMD_FLAG_WRITE 0x0
58 #define MXC_DCD_CMD_FLAG_CLR 0x1
59 #define MXC_DCD_CMD_FLAG_SET 0x3
60 #define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1))
61 #define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1))
62 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1))
63 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1))
65 #define MXC_DCD_START \
66 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
71 .ifgt . - dcd_start - 1768
72 .error "DCD too large!"
79 #define MXC_DCD_CMD_WRT(type, flags) \
80 1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
82 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
83 1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
84 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
86 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
87 1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
88 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
90 #define MXC_DCD_CMD_NOP() \
91 1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
94 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
95 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
96 #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
97 #define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100)
98 #define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000)
100 .macro CK_VAL, name, clks, offs, max
104 .ifle \clks - \offs - \max
105 .set \name, \clks - \offs
107 .error "Value \clks out of range for parameter \name"
112 .macro NS_VAL, name, ns, offs, max
116 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
120 .macro CK_MAX, name, ck1, ck2, offs, max
122 CK_VAL \name, \ck1, \offs, \max
124 CK_VAL \name, \ck2, \offs, \max
128 #define MDMISC_DDR_TYPE_DDR3 0
129 #define MDMISC_DDR_TYPE_LPDDR2 1
130 #define MDMISC_DDR_TYPE_DDR2 2
132 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
134 #define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
137 #ifdef PHYS_SDRAM_2_SIZE
138 #define BANK_ADDR_BITS 2
140 #define BANK_ADDR_BITS 1
142 #define SDRAM_BURST_LENGTH 8
146 #define ADDR_MIRROR 0
147 #define DDR_TYPE MDMISC_DDR_TYPE_DDR3
149 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII or MT41K128M16JT-125 */
150 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
153 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
154 #define CL_VAL 9 // or 10
156 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
157 #define CL_VAL 7 // or 8
159 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
162 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
166 #error SDRAM clock out of range: 303 .. 800
169 #if SDRAM_SIZE <= SZ_256M
170 /* 256MiB SDRAM: NT5CB128M16FP-DII */
171 #define ROW_ADDR_BITS 14
172 #define COL_ADDR_BITS 10
175 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
176 CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
177 CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) (MT41K128M16JT: 6ns) */
178 CK_MAX tXPDLL, NS_TO_CK(24), 10, 1, 15 /* clks - 1 (0..15) */
179 NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 30ns) */
180 CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
183 CK_VAL tRCD, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
184 CK_VAL tRP, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
185 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 49ns) */
186 CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 3.5ns) */
187 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
188 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
189 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
190 CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
193 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ /* (Jedec Standard) */
194 CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
195 CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
196 CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */
198 /* 512MiB SDRAM: IM4G16D3EABG-125I */
199 #define ROW_ADDR_BITS 15
200 #define COL_ADDR_BITS 10
203 NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */
204 CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
205 CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
206 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
207 NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */
208 CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
211 CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
212 CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
213 CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */
214 CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */
215 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
216 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
217 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
218 CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
221 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
222 CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
223 CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
224 CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
228 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
229 #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
230 #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
233 CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
234 CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
235 CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
236 CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
237 CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */
238 CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */
241 CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7
242 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
243 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
250 #define MDPDC_VAL_0 ( \
255 (BOTH_CS_PD << 6) | \
260 #define MDPDC_VAL_1 (MDPDC_VAL_0 | \
265 #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
266 #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
267 #define DLL_DISABLE 0
270 .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \
271 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
272 ((tWR + 1 - 4) << 9) | \
273 ((((tCL + 3) - 4) & 0x7) << 4) | \
274 ((((tCL + 3) - 4) & 0x8) >> 1))
276 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
277 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
278 (((tWR + 1) / 2) << 9) | \
279 ((((tCL + 3) - 4) & 0x7) << 4) | \
280 ((((tCL + 3) - 4) & 0x8) >> 1))
284 ((Rtt_Nom & 1) << 2) | \
285 (((Rtt_Nom >> 1) & 1) << 6) | \
286 (((Rtt_Nom >> 2) & 1) << 9) | \
287 (DLL_DISABLE << 0) | \
290 (Rtt_WR << 9) /* dynamic ODT */ | \
291 (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
292 (1 << 6) | /* ASR: Automatic Self Refresh */ \
293 (((tCWL + 2) - 5) << 3) | \
297 #define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
298 (1 << 15) /* CON_REQ */ | \
299 (3 << 4) /* MRS command */ | \
304 #define MDCFG0_VAL ( \
312 #define MDCFG1_VAL ( \
322 #define MDCFG2_VAL ( \
328 #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
330 #define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
331 ((COL_ADDR_BITS - 9) << 20) | \
332 (BURST_LEN << 19) | \
333 ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \
334 ((-1) << (32 - BANK_ADDR_BITS)))
336 #define MDMISC_WALAT(n) (((n) & 3) << 16)
337 #define MDMISC_RALAT(n) (((n) & 7) << 6)
339 #define CK1_GATING (2 - BANK_ADDR_BITS)
341 #define MDMISC_VAL ((CK1_GATING << 21) | \
342 (ADDR_MIRROR << 19) | \
343 MDMISC_WALAT(WALAT) | \
346 MDMISC_RALAT(RALAT) | \
349 #define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
351 #define MDOTC_VAL ((tAOFPD << 27) | \
360 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
371 #ifdef CONFIG_SECURE_BOOT
378 .long CONFIG_SYS_TEXT_BASE
380 .long __uboot_img_len
384 #define DCD_VERSION 0x40
386 #define DDR_SEL_VAL 3 /* DDR3 */
387 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
388 #define DSE1_VAL 6 /* Drive Strength for DATA lines */
389 #define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
391 #define DSE1_VAL 6 /* Drive Strength for DATA lines */
392 #define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
395 #define DDR_PKE_VAL 0
397 #define DDR_SEL_SHIFT 18
398 #define DDR_MODE_SHIFT 17
406 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
407 #define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) /* differential input mode */
408 #define DSE1_MASK (DSE1_VAL << DSE_SHIFT)
409 #define DSE2_MASK (DSE2_VAL << DSE_SHIFT)
410 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
411 #define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT)
413 #define DQM_MASK (DDR_MODE_MASK | DSE2_MASK)
414 #define SDQS_MASK DSE2_MASK
415 #define SDODT_MASK (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
416 #define SDCLK_MASK (DDR_MODE_MASK | DSE2_MASK)
417 #define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
418 #define DDR_ADDR_MASK (ODT_MASK | DDR_MODE_MASK)
419 #define DDR_CTRL_MASK (DDR_MODE_MASK | DSE2_MASK)
421 #define MMDC_MDCTL 0x021b0000
422 #define MMDC_MDPDC 0x021b0004
423 #define MMDC_MDOTC 0x021b0008
424 #define MMDC_MDCFG0 0x021b000c
425 #define MMDC_MDCFG1 0x021b0010
426 #define MMDC_MDCFG2 0x021b0014
427 #define MMDC_MDMISC 0x021b0018
428 #define MMDC_MDSCR 0x021b001c
429 #define MMDC_MDREF 0x021b0020
430 #define MMDC_MDRWD 0x021b002c
431 #define MMDC_MDOR 0x021b0030
432 #define MMDC_MDASP 0x021b0040
434 #define MMDC_MAPSR 0x021b0404
436 #define MMDC_MPZQHWCTRL 0x021b0800
437 #define MMDC_MPWLGCR 0x021b0808
438 #define MMDC_MPWLDECTRL0 0x021b080c
439 #define MMDC_MPWLDLST 0x021b0814
440 #define MMDC_MPODTCTRL 0x021b0818
441 #define MMDC_MPRDDQBY0DL 0x021b081c
442 #define MMDC_MPRDDQBY1DL 0x021b0820
443 #define MMDC_MPWRDQBY0DL 0x021b082c
444 #define MMDC_MPWRDQBY1DL 0x021b0830
445 #define MMDC_MPDGCTRL0 0x021b083c
446 #define MMDC_MPDGDLST0 0x021b0844
447 #define MMDC_MPRDDLCTL 0x021b0848
448 #define MMDC_MPRDDLST 0x021b084c
449 #define MMDC_MPWRDLCTL 0x021b0850
450 #define MMDC_MPWRDLST 0x021b0854
451 #define MMDC_MPSDCTRL 0x021b0858
452 #define MMDC_MPRDDLHWCTL 0x021b0860
453 #define MMDC_MPWRDLHWCTL 0x021b0864
454 #define MMDC_MPDGHWST0 0x021b087c
455 #define MMDC_MPDGHWST1 0x021b0880
456 #define MMDC_MPPDCMPR2 0x021b0890
457 #define MMDC_MPSWDRDR0 0x021b0898
458 #define MMDC_MPSWDRDR1 0x021b089c
459 #define MMDC_MPSWDRDR2 0x021b08a0
460 #define MMDC_MPSWDRDR3 0x021b08a4
461 #define MMDC_MPSWDRDR4 0x021b08a8
462 #define MMDC_MPSWDRDR5 0x021b08ac
463 #define MMDC_MPSWDRDR6 0x021b08b0
464 #define MMDC_MPSWDRDR7 0x021b08b4
465 #define MMDC_MPMUR0 0x021b08b8
467 #define IOMUXC_GPR0 0x020e4000
468 #define IOMUXC_GPR1 0x020e4004
469 #define IOMUXC_GPR2 0x020e4008
470 #define IOMUXC_GPR3 0x020e400c
471 #define IOMUXC_GPR4 0x020e4010
472 #define IOMUXC_GPR5 0x020e4014
473 #define IOMUXC_GPR10 0x020e4028
474 #define IOMUXC_GPR14 0x020e4048
476 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0 0x020e001c
477 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1 0x020e0020
478 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5 0x020e0030
479 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6 0x020e0034
480 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA 0x020e0084
481 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA 0x020e0088
482 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK 0x020e00dc
483 #define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B 0x020e008c
484 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B 0x020e0090
485 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK 0x020e00fc
486 #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B 0x020e0178
487 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B 0x020e017c
488 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e0180
489 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0184
490 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e0188
491 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e018c
492 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e0190
493 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0194
494 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0198
495 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e019c
496 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e01a0
497 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e01a4
498 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e01a8
499 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B 0x020e01ac
500 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e01b4
502 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0 0x020e02a8
503 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1 0x020e02ac
504 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5 0x020e02bc
505 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6 0x020e02c0
506 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA 0x020e0310
507 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA 0x020e0314
508 #define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B 0x020e0318
509 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B 0x020e031c
510 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x020e042c
511 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x020e0440
512 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e0204
513 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0208
514 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e020c
515 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0210
516 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e0214
517 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0218
518 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e021c
519 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0220
520 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e0224
521 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0228
522 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e022c
523 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0230
524 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e0234
525 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0238
526 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e023c
527 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e0244
528 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e0248
529 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e024c
530 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0250
531 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x020e0254
532 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x020e0258
533 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x020e025c
534 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e0260
535 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e0264
536 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0268
537 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e026c
538 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e0270
539 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e0274
540 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e0278
541 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e027c
542 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e0280
543 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e0284
544 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e0288
546 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK 0x020e0368
547 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK 0x020e0388
548 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B 0x020e0404
549 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B 0x020e0408
550 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x020e040c
551 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x020e0410
552 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x020e0414
553 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x020e0418
554 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x020e041c
555 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x020e0420
556 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x020e0424
557 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x020e0428
558 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e0490
559 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0494
560 #define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0498
561 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e049c
562 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e04a0
563 #define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e04a4
564 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e04a8
565 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e04ac
566 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e04b0
567 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e04b4
569 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e0620
570 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0624
572 #define IOMUXC_ENET1_REF_CLK1_SELECT_INPUT 0x020e0574
573 #define IOMUXC_ENET2_REF_CLK2_SELECT_INPUT 0x020e057c
577 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
578 /* setup I2C pads for PMIC */
579 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0, 0x00000015)
580 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1, 0x00000015)
581 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0, 0x0000f0b9)
582 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1, 0x0000f0b9)
583 #ifdef CONFIG_TX6_NAND
584 /* switch NFC clock to 99MHz */
585 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR)
586 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
587 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
588 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
589 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x000336c1 */
590 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
591 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
592 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
593 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
595 /* switch LCDIF clk source to PLL5 */
596 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00011150) /* default: 0x00029150 */
597 MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */
599 /* enable all relevant clocks... */
600 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
601 /* enable UART clock depending on selected console port */
602 #if CONFIG_MXC_UART_BASE == UART1_BASE
603 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(12)) /* UART1 */
604 #elif CONFIG_MXC_UART_BASE == UART2_BASE
605 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(14)) /* UART2 */
606 #elif CONFIG_MXC_UART_BASE == UART3_BASE
607 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* UART3 */
608 #elif CONFIG_MXC_UART_BASE == UART4_BASE
609 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(12)) /* UART4 */
610 #elif CONFIG_MXC_UART_BASE == UART5_BASE
611 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(1)) /* UART5 */
613 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* default: 0xcfc03f0f APBH-DMA */
614 // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR()) /* default: 0xfcfc0000 */
615 // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR()) /* default: 0x0c3ff033 */
616 #ifdef CONFIG_SOC_MX6ULL
617 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(6)) /* default: 0xcfc03f0f ENET */
619 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(2)) /* default: 0xffff3300 ENET */
621 #ifdef CONFIG_TX6_NAND
622 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4,
623 CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* default: 0x0000f3ff GPMI BCH */
625 // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR()) /* default: 0x0c3f0c3f */
626 #ifdef CONFIG_TX6_EMMC
627 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(2) | CCGR(1)) /* default: 0x00fc3003 USDHC2 USDHC1 */
629 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(1)) /* default: 0x00fc3003 USDHC1 */
632 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
633 MXC_DCD_ITEM(0x020c80b0, 0)
634 MXC_DCD_ITEM(0x020c80c0, 1)
635 MXC_DCD_ITEM(0x020c80a0, 0x0010201b) /* set video PLL to 648MHz */
638 MXC_DCD_ITEM(IOMUXC_GPR0, 0x00000000)
639 MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET[12]_TX_CLK output */
640 MXC_DCD_ITEM(IOMUXC_GPR2, 0x00000000)
641 MXC_DCD_ITEM(IOMUXC_GPR3, 0x00000fff)
642 MXC_DCD_ITEM(IOMUXC_GPR4, 0x00000100)
643 MXC_DCD_ITEM(IOMUXC_GPR5, 0x00000000)
644 MXC_DCD_ITEM(IOMUXC_GPR10, 0x00000003)
645 /* UART1 pad config */
646 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA, 0x00000000) /* UART1 TXD */
647 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA, 0x000010b0) /* UART1 TXD */
648 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA, 0x00000000) /* UART1 RXD */
649 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA, 0x000010b0) /* UART1 RXD */
650 MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */
651 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B, 0x00000000) /* UART1 CTS */
652 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B, 0x000010b0) /* UART1 CTS */
653 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B, 0x00000000) /* UART1 RTS */
654 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B, 0x000010b0) /* UART1 RTS */
655 MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
657 #ifdef CONFIG_NAND_MXS
659 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
660 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, 0x000030b0) /* NANDF_CLE: NANDF_CLE */
661 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
662 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
663 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
664 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
665 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B, 0x00000000) /* NAND_RE_B: NANDF_RDn */
666 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B, 0x00000000) /* NAND_WE_B: NANDF_WRn */
667 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */
668 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */
669 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */
670 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */
671 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */
672 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
673 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
674 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
677 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
678 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
681 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
682 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
683 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
684 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
685 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
686 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
687 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
688 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
689 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
690 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
691 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
692 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
693 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
694 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
695 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
697 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
699 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
701 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
703 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
704 /* DRAM_SDCKE[0..1] */
705 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
706 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
707 /* DRAM_SDBA[0..2] */
708 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
709 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
710 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
711 /* DRAM_SDODT[0..1] */
712 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
713 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
715 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
716 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
718 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
720 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
722 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
724 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
726 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
728 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
730 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
732 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
734 /* SDRAM initialization */
735 #define WL_DLY_DQS_VAL 7
736 #define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
737 #define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
740 MXC_DCD_ITEM(MMDC_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
741 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MDMISC, 0x00000002)
742 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
745 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008010) /* precharge all */
746 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008040) /* MRS: ZQ calibration */
747 MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1390001)
749 MXC_DCD_ITEM(MMDC_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
751 MXC_DCD_ITEM(MMDC_MPDGCTRL0, 0x41ae012f)
753 MXC_DCD_ITEM(MMDC_MPRDDLCTL, 0x3f3f4d4c) /* DQ RD Delay default values */
754 MXC_DCD_ITEM(MMDC_MPWRDLCTL, 0x3f3f3f3f) /* DQ WR Delay default values */
756 /* MPRDDQBY[0..7]DL */
757 MXC_DCD_ITEM(MMDC_MPRDDQBY0DL, 0x33333333)
758 MXC_DCD_ITEM(MMDC_MPRDDQBY1DL, 0x33333333)
759 /* MPRDDQBY[0..7]DL */
760 MXC_DCD_ITEM(MMDC_MPWRDQBY0DL, 0x33333333)
761 MXC_DCD_ITEM(MMDC_MPWRDQBY1DL, 0x33333333)
762 #define MPMUR_FRC_MSR (1 << 11)
763 MXC_DCD_ITEM(MMDC_MPMUR0, MPMUR_FRC_MSR)
766 MXC_DCD_ITEM(MMDC_MDCTL, MDCTL_VAL)
767 #if BANK_ADDR_BITS > 1
768 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDMISC, (3 << 30))
770 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDMISC, (1 << 30))
772 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
774 /* MSDSCR Conf Req */
775 MXC_DCD_ITEM(MMDC_MDSCR, 0x00008000)
776 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDSCR, 0x00004000)
777 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
779 MXC_DCD_ITEM(MMDC_MDCFG0, MDCFG0_VAL)
780 MXC_DCD_ITEM(MMDC_MDCFG1, MDCFG1_VAL)
781 MXC_DCD_ITEM(MMDC_MDCFG2, MDCFG2_VAL)
783 MXC_DCD_ITEM(MMDC_MDRWD, 0x000026d2)
784 MXC_DCD_ITEM(MMDC_MDOR, MDOR_VAL)
785 MXC_DCD_ITEM(MMDC_MDOTC, MDOTC_VAL)
786 MXC_DCD_ITEM(MMDC_MDPDC, MDPDC_VAL_0)
787 MXC_DCD_ITEM(MMDC_MDASP, PHYS_SDRAM_1_SIZE / SZ_32M + 0x3f)
790 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
791 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
792 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
793 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
794 #if BANK_ADDR_BITS > 1
796 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
797 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
798 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
799 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
801 MXC_DCD_ITEM(MMDC_MDREF, 0x0000c000) /* disable refresh */
802 MXC_DCD_ITEM(MMDC_MDSCR, 0x00008020) /* issue one refresh cycle */
804 MXC_DCD_ITEM(MMDC_MPODTCTRL, 0x00022222)
806 /* DDR3 calibration */
807 MXC_DCD_ITEM(MMDC_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
808 MXC_DCD_ITEM(MMDC_MAPSR, 1)
811 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008010) /* precharge all */
812 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008040) /* MRS: ZQ calibration */
813 MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1390001)
815 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPZQHWCTRL, 0x00010000)
816 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
817 MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1380000)
818 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
819 #if BANK_ADDR_BITS > 1
820 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
822 /* DRAM_SDQS[0..1] pad config */
823 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
824 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
825 /* Read delay calibration */
826 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008050) /* precharge all to bank 0 */
827 MXC_DCD_ITEM(MMDC_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
828 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPRDDLHWCTL, 0x00000013)
829 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
831 /* Write delay calibration */
832 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008050) /* precharge all to bank 0 */
833 MXC_DCD_ITEM(MMDC_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
834 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPWRDLHWCTL, 0x00000013)
836 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
837 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
838 #if BANK_ADDR_BITS > 1
839 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
841 MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa138002b)
842 MXC_DCD_ITEM(MMDC_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
843 MXC_DCD_ITEM(MMDC_MAPSR, (16 << 8) | (0 << 0))
844 MXC_DCD_ITEM(MMDC_MDPDC, MDPDC_VAL_1)
846 /* MDSCR: Normal operation */
847 MXC_DCD_ITEM(MMDC_MDSCR, 0x00000000)
848 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MDSCR, 0x00004000)