2 #include <asm-offsets.h>
3 #include <configs/tx6.h>
4 #include <linux/linkage.h>
5 #include <asm/arch/imx-regs.h>
6 #include <generated/asm-offsets.h>
9 #error asm-offsets not included
12 #define DEBUG_LED_BIT 20
13 #define LED_GPIO_BASE GPIO2_BASE_ADDR
14 #define LED_MUX_OFFSET 0x0ec
15 #define LED_MUX_MODE 0x15
17 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
19 #ifdef PHYS_SDRAM_2_SIZE
20 #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
22 #define SDRAM_SIZE PHYS_SDRAM_1_SIZE
25 #define CPU_2_BE_32(l) \
26 ((((l) << 24) & 0xFF000000) | \
27 (((l) << 8) & 0x00FF0000) | \
28 (((l) >> 8) & 0x0000FF00) | \
29 (((l) >> 24) & 0x000000FF))
31 #define CHECK_DCD_ADDR(a) ( \
32 ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
33 ((a) >= 0x020E4000 && (a) <= 0x020E7FFF) /* IOMUXC GPR */ || \
34 ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
35 ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
36 ((a) >= 0x021B0000 && (a) <= 0x021B3FFF) /* MMDC */ || \
37 ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
38 ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
39 ((a) >= 0x80000000 && (a) <= 0xFFFF7FFF) /* SDRAM */ || \
40 ((a) >= 0x020D0000 && (a) <= 0x020D3FFF) /* EPIT */)
42 .macro mxc_dcd_item addr, val
43 .ifne CHECK_DCD_ADDR(\addr)
44 .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
46 .error "Address \addr not accessible from DCD"
50 #define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
52 #define MXC_DCD_CMD_SZ_BYTE 1
53 #define MXC_DCD_CMD_SZ_SHORT 2
54 #define MXC_DCD_CMD_SZ_WORD 4
55 #define MXC_DCD_CMD_FLAG_WRITE 0x0
56 #define MXC_DCD_CMD_FLAG_CLR 0x1
57 #define MXC_DCD_CMD_FLAG_SET 0x3
58 #define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1))
59 #define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1))
60 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1))
61 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1))
63 #define MXC_DCD_START \
64 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
69 .ifgt . - dcd_start - 1768
70 .error "DCD too large!"
77 #define MXC_DCD_CMD_WRT(type, flags) \
78 1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
80 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
81 1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
82 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
84 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
85 1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
86 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
88 #define MXC_DCD_CMD_NOP() \
89 1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
92 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
93 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
94 #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
95 #define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000)
97 .macro CK_VAL, name, clks, offs, max
101 .ifle \clks - \offs - \max
102 .set \name, \clks - \offs
104 .error "Value \clks out of range for parameter \name"
109 .macro NS_VAL, name, ns, offs, max
113 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
117 .macro CK_MAX, name, ck1, ck2, offs, max
119 CK_VAL \name, \ck1, \offs, \max
121 CK_VAL \name, \ck2, \offs, \max
125 #define MDMISC_DDR_TYPE_DDR3 0
126 #define MDMISC_DDR_TYPE_LPDDR2 1
127 #define MDMISC_DDR_TYPE_DDR2 2
129 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
131 #define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
134 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
135 #define BANK_ADDR_BITS 2
137 #define BANK_ADDR_BITS 1
139 #define SDRAM_BURST_LENGTH 8
143 #define ADDR_MIRROR 0
144 #define DDR_TYPE MDMISC_DDR_TYPE_DDR3
146 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII or MT41K128M16JT-125 */
147 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
150 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
151 #define CL_VAL 9 // or 10
153 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
154 #define CL_VAL 7 // or 8
156 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
159 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
163 #error SDRAM clock out of range: 303 .. 800
167 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
168 CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
169 CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) (MT41K128M16JT: 6ns) */
170 CK_MAX tXPDLL, NS_TO_CK(24), 10, 1, 15 /* clks - 1 (0..15) */
171 NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 30ns) */
172 CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
175 CK_VAL tRCD, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
176 CK_VAL tRP, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */
177 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 49ns) */
178 CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 3.5ns) */
179 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
180 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
181 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
182 CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
185 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ /* (Jedec Standard) */
186 CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
187 CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
188 CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */
191 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
192 #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
193 #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
196 CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
197 CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */
198 CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
199 CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
200 CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */
201 CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */
204 CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7
205 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
206 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
213 #define MDPDC_VAL_0 ( \
218 (BOTH_CS_PD << 6) | \
223 #define MDPDC_VAL_1 (MDPDC_VAL_0 | \
228 #define ROW_ADDR_BITS 14
229 #define COL_ADDR_BITS 10
231 #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
232 #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
233 #define DLL_DISABLE 0
236 .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \
237 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
238 ((tWR + 1 - 4) << 9) | \
239 ((((tCL + 3) - 4) & 0x7) << 4) | \
240 ((((tCL + 3) - 4) & 0x8) >> 1))
242 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
243 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
244 (((tWR + 1) / 2) << 9) | \
245 ((((tCL + 3) - 4) & 0x7) << 4) | \
246 ((((tCL + 3) - 4) & 0x8) >> 1))
250 ((Rtt_Nom & 1) << 2) | \
251 (((Rtt_Nom >> 1) & 1) << 6) | \
252 (((Rtt_Nom >> 2) & 1) << 9) | \
253 (DLL_DISABLE << 0) | \
256 (Rtt_WR << 9) /* dynamic ODT */ | \
257 (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
258 (1 << 6) | /* ASR: Automatic Self Refresh */ \
259 (((tCWL + 2) - 5) << 3) | \
263 #define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
264 (1 << 15) /* CON_REQ */ | \
265 (3 << 4) /* MRS command */ | \
270 #define MDCFG0_VAL ( \
278 #define MDCFG1_VAL ( \
288 #define MDCFG2_VAL ( \
294 #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
296 #define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
297 ((COL_ADDR_BITS - 9) << 20) | \
298 (BURST_LEN << 19) | \
299 ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \
300 ((-1) << (32 - BANK_ADDR_BITS)))
302 #define MDMISC_WALAT(n) (((n) & 3) << 16)
303 #define MDMISC_RALAT(n) (((n) & 7) << 6)
305 #define CK1_GATING (2 - BANK_ADDR_BITS)
307 #define MDMISC_VAL ((CK1_GATING << 21) | \
308 (ADDR_MIRROR << 19) | \
309 MDMISC_WALAT(WALAT) | \
312 MDMISC_RALAT(RALAT) | \
315 #define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
317 #define MDOTC_VAL ((tAOFPD << 27) | \
326 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
337 #ifdef CONFIG_SECURE_BOOT
344 .long CONFIG_SYS_TEXT_BASE
346 .long __uboot_img_len
350 #define DCD_VERSION 0x40
352 #define DDR_SEL_VAL 3 /* DDR3 */
353 #if CONFIG_SYS_SDRAM_BUS_WIDTH == 16
354 #define DSE1_VAL 6 /* Drive Strength for DATA lines */
355 #define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
357 #define DSE1_VAL 6 /* Drive Strength for DATA lines */
358 #define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
361 #define DDR_PKE_VAL 0
363 #define DDR_SEL_SHIFT 18
364 #define DDR_MODE_SHIFT 17
372 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
373 #define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) /* differential input mode */
374 #define DSE1_MASK (DSE1_VAL << DSE_SHIFT)
375 #define DSE2_MASK (DSE2_VAL << DSE_SHIFT)
376 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
377 #define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT)
379 #define DQM_MASK (DDR_MODE_MASK | DSE2_MASK)
380 #define SDQS_MASK DSE2_MASK
381 #define SDODT_MASK (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
382 #define SDCLK_MASK (DDR_MODE_MASK | DSE2_MASK)
383 #define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
384 #define DDR_ADDR_MASK (ODT_MASK | DDR_MODE_MASK)
385 #define DDR_CTRL_MASK (DDR_MODE_MASK | DSE2_MASK)
387 #define MMDC_MDCTL 0x021b0000
388 #define MMDC_MDPDC 0x021b0004
389 #define MMDC_MDOTC 0x021b0008
390 #define MMDC_MDCFG0 0x021b000c
391 #define MMDC_MDCFG1 0x021b0010
392 #define MMDC_MDCFG2 0x021b0014
393 #define MMDC_MDMISC 0x021b0018
394 #define MMDC_MDSCR 0x021b001c
395 #define MMDC_MDREF 0x021b0020
396 #define MMDC_MDRWD 0x021b002c
397 #define MMDC_MDOR 0x021b0030
398 #define MMDC_MDASP 0x021b0040
400 #define MMDC_MAPSR 0x021b0404
402 #define MMDC_MPZQHWCTRL 0x021b0800
403 #define MMDC_MPWLGCR 0x021b0808
404 #define MMDC_MPWLDECTRL0 0x021b080c
405 #define MMDC_MPWLDLST 0x021b0814
406 #define MMDC_MPODTCTRL 0x021b0818
407 #define MMDC_MPRDDQBY0DL 0x021b081c
408 #define MMDC_MPRDDQBY1DL 0x021b0820
409 #define MMDC_MPWRDQBY0DL 0x021b082c
410 #define MMDC_MPWRDQBY1DL 0x021b0830
411 #define MMDC_MPDGCTRL0 0x021b083c
412 #define MMDC_MPDGDLST0 0x021b0844
413 #define MMDC_MPRDDLCTL 0x021b0848
414 #define MMDC_MPRDDLST 0x021b084c
415 #define MMDC_MPWRDLCTL 0x021b0850
416 #define MMDC_MPWRDLST 0x021b0854
417 #define MMDC_MPSDCTRL 0x021b0858
418 #define MMDC_MPRDDLHWCTL 0x021b0860
419 #define MMDC_MPWRDLHWCTL 0x021b0864
420 #define MMDC_MPDGHWST0 0x021b087c
421 #define MMDC_MPDGHWST1 0x021b0880
422 #define MMDC_MPPDCMPR2 0x021b0890
423 #define MMDC_MPSWDRDR0 0x021b0898
424 #define MMDC_MPSWDRDR1 0x021b089c
425 #define MMDC_MPSWDRDR2 0x021b08a0
426 #define MMDC_MPSWDRDR3 0x021b08a4
427 #define MMDC_MPSWDRDR4 0x021b08a8
428 #define MMDC_MPSWDRDR5 0x021b08ac
429 #define MMDC_MPSWDRDR6 0x021b08b0
430 #define MMDC_MPSWDRDR7 0x021b08b4
431 #define MMDC_MPMUR0 0x021b08b8
433 #define IOMUXC_GPR0 0x020e4000
434 #define IOMUXC_GPR1 0x020e4004
435 #define IOMUXC_GPR2 0x020e4008
436 #define IOMUXC_GPR3 0x020e400c
437 #define IOMUXC_GPR4 0x020e4010
438 #define IOMUXC_GPR5 0x020e4014
439 #define IOMUXC_GPR10 0x020e4028
440 #define IOMUXC_GPR14 0x020e4048
442 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0 0x020e001c
443 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1 0x020e0020
444 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5 0x020e0030
445 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6 0x020e0034
446 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA 0x020e0084
447 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA 0x020e0088
448 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK 0x020e00dc
449 #define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B 0x020e008c
450 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B 0x020e0090
451 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK 0x020e00fc
452 #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B 0x020e0178
453 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B 0x020e017c
454 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e0180
455 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0184
456 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e0188
457 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e018c
458 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e0190
459 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0194
460 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0198
461 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e019c
462 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e01a0
463 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e01a4
464 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e01a8
465 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B 0x020e01ac
466 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e01b4
468 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0 0x020e02a8
469 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1 0x020e02ac
470 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5 0x020e02bc
471 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6 0x020e02c0
472 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA 0x020e0310
473 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA 0x020e0314
474 #define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B 0x020e0318
475 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B 0x020e031c
476 #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x020e042c
477 #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x020e0440
478 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e0204
479 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0208
480 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e020c
481 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0210
482 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e0214
483 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0218
484 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e021c
485 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0220
486 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e0224
487 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0228
488 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e022c
489 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0230
490 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e0234
491 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0238
492 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e023c
493 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e0244
494 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e0248
495 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e024c
496 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0250
497 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x020e0254
498 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x020e0258
499 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x020e025c
500 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e0260
501 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e0264
502 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0268
503 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e026c
504 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e0270
505 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e0274
506 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e0278
507 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e027c
508 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e0280
509 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e0284
510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e0288
512 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK 0x020e0368
513 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK 0x020e037c
514 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B 0x020e0404
515 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B 0x020e0408
516 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x020e040c
517 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x020e0410
518 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x020e0414
519 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x020e0418
520 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x020e041c
521 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x020e0420
522 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x020e0424
523 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x020e0428
524 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e0490
525 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0494
526 #define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0498
527 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e049c
528 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e04a0
529 #define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e04a4
530 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e04a8
531 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e04ac
532 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e04b0
533 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e04b4
535 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e0620
536 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0624
538 #define IOMUXC_ENET1_REF_CLK1_SELECT_INPUT 0x020e0574
539 #define IOMUXC_ENET2_REF_CLK2_SELECT_INPUT 0x020e057c
543 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
544 /* setup I2C pads for PMIC */
545 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0, 0x00000015)
546 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1, 0x00000015)
547 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0, 0x0000f0b9)
548 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1, 0x0000f0b9)
550 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK, 0x00000014)
551 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK, 0x000010b0)
552 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK, 0x00000014)
553 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK, 0x000010b0)
554 MXC_DCD_ITEM(IOMUXC_ENET1_REF_CLK1_SELECT_INPUT, 2)
555 MXC_DCD_ITEM(IOMUXC_ENET2_REF_CLK2_SELECT_INPUT, 2)
557 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6, 0x00000015)
558 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6, 0x000010b0)
560 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015)
561 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0)
562 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x000336c1 */
563 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
565 MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */
566 #define CCGR(m) (3 << ((m) * 2))
567 /* enable all relevant clocks... */
568 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
569 /* enable UART clock depending on selected console port */
570 #if CONFIG_MXC_UART_BASE == UART1_BASE
571 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(12)) /* UART1 */
572 #elif CONFIG_MXC_UART_BASE == UART2_BASE
573 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(14)) /* UART2 */
574 #elif CONFIG_MXC_UART_BASE == UART3_BASE
575 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* UART3 */
576 #elif CONFIG_MXC_UART_BASE == UART4_BASE
577 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(12)) /* UART4 */
578 #elif CONFIG_MXC_UART_BASE == UART5_BASE
579 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(1)) /* UART5 */
581 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* default: 0xcfc03f0f APBH-DMA */
582 // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR()) /* default: 0xfcfc0000 */
583 // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR()) /* default: 0x0c3ff033 */
584 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(2)) /* default: 0xffff3300 ENET */
585 #ifdef CONFIG_TX6_NAND
586 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4,
587 CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* default: 0x0000f3ff GPMI BCH */
589 // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR()) /* default: 0x0c3f0c3f */
590 #ifdef CONFIG_TX6_EMMC
591 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(2) | CCGR(1)) /* default: 0x00fc3003 USDHC2 USDHC1 */
593 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(1)) /* default: 0x00fc3003 USDHC1 */
595 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
597 MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
598 MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
599 MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
602 MXC_DCD_ITEM(IOMUXC_GPR0, 0x00000000)
603 MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET1_TX_CLK output */
604 MXC_DCD_ITEM(IOMUXC_GPR2, 0x00000000)
605 MXC_DCD_ITEM(IOMUXC_GPR3, 0x00000fff)
606 MXC_DCD_ITEM(IOMUXC_GPR4, 0x00000100)
607 MXC_DCD_ITEM(IOMUXC_GPR5, 0x00000000)
608 MXC_DCD_ITEM(IOMUXC_GPR10, 0x00000003)
609 /* UART1 pad config */
610 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA, 0x00000000) /* UART1 TXD */
611 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA, 0x000010b0) /* UART1 TXD */
612 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA, 0x00000000) /* UART1 RXD */
613 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA, 0x000010b0) /* UART1 RXD */
614 MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */
615 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B, 0x00000000) /* UART1 CTS */
616 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B, 0x000010b0) /* UART1 CTS */
617 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B, 0x00000000) /* UART1 RTS */
618 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B, 0x000010b0) /* UART1 RTS */
619 MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
621 #ifdef CONFIG_NAND_MXS
623 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
624 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, 0x000030b0) /* NANDF_CLE: NANDF_CLE */
625 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
626 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
627 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
628 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
629 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B, 0x00000000) /* NAND_RE_B: NANDF_RDn */
630 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B, 0x00000000) /* NAND_WE_B: NANDF_WRn */
631 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */
632 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */
633 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */
634 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */
635 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */
636 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
637 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
638 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
641 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
642 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
645 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
646 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
647 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
648 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
649 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
650 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
651 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
652 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
653 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
654 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
655 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
656 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
657 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
658 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
659 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
661 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
663 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
665 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
667 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
668 /* DRAM_SDCKE[0..1] */
669 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
670 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
671 /* DRAM_SDBA[0..2] */
672 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
673 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
674 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
675 /* DRAM_SDODT[0..1] */
676 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
677 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
679 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
680 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
682 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
684 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
686 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
688 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
690 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
692 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
694 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
696 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
698 /* SDRAM initialization */
699 #define WL_DLY_DQS_VAL 7
700 #define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
701 #define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
704 MXC_DCD_ITEM(MMDC_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
705 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MDMISC, 0x00000002)
706 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
709 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008010) /* precharge all */
710 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008040) /* MRS: ZQ calibration */
711 MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1390001)
713 MXC_DCD_ITEM(MMDC_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
715 MXC_DCD_ITEM(MMDC_MPDGCTRL0, 0x41ae012f)
717 MXC_DCD_ITEM(MMDC_MPRDDLCTL, 0x3f3f4d4c) /* DQ RD Delay default values */
718 MXC_DCD_ITEM(MMDC_MPWRDLCTL, 0x3f3f3f3f) /* DQ WR Delay default values */
720 /* MPRDDQBY[0..7]DL */
721 MXC_DCD_ITEM(MMDC_MPRDDQBY0DL, 0x33333333)
722 MXC_DCD_ITEM(MMDC_MPRDDQBY1DL, 0x33333333)
723 /* MPRDDQBY[0..7]DL */
724 MXC_DCD_ITEM(MMDC_MPWRDQBY0DL, 0x33333333)
725 MXC_DCD_ITEM(MMDC_MPWRDQBY1DL, 0x33333333)
726 #define MPMUR_FRC_MSR (1 << 11)
727 MXC_DCD_ITEM(MMDC_MPMUR0, MPMUR_FRC_MSR)
730 MXC_DCD_ITEM(MMDC_MDCTL, MDCTL_VAL)
731 #if BANK_ADDR_BITS > 1
732 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDMISC, (3 << 30))
734 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDMISC, (1 << 30))
736 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
738 /* MSDSCR Conf Req */
739 MXC_DCD_ITEM(MMDC_MDSCR, 0x00008000)
740 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDSCR, 0x00004000)
741 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
743 MXC_DCD_ITEM(MMDC_MDCFG0, MDCFG0_VAL)
744 MXC_DCD_ITEM(MMDC_MDCFG1, MDCFG1_VAL)
745 MXC_DCD_ITEM(MMDC_MDCFG2, MDCFG2_VAL)
747 MXC_DCD_ITEM(MMDC_MDRWD, 0x000026d2)
748 MXC_DCD_ITEM(MMDC_MDOR, MDOR_VAL)
749 MXC_DCD_ITEM(MMDC_MDOTC, MDOTC_VAL)
750 MXC_DCD_ITEM(MMDC_MDPDC, MDPDC_VAL_0)
751 MXC_DCD_ITEM(MMDC_MDASP, PHYS_SDRAM_1_SIZE / SZ_32M + 0x3f)
754 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
755 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
756 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
757 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
758 #if BANK_ADDR_BITS > 1
760 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
761 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
762 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
763 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
765 MXC_DCD_ITEM(MMDC_MDREF, 0x0000c000) /* disable refresh */
766 MXC_DCD_ITEM(MMDC_MDSCR, 0x00008020) /* issue one refresh cycle */
768 MXC_DCD_ITEM(MMDC_MPODTCTRL, 0x00022222)
770 /* DDR3 calibration */
771 MXC_DCD_ITEM(MMDC_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
772 MXC_DCD_ITEM(MMDC_MAPSR, 1)
775 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008010) /* precharge all */
776 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008040) /* MRS: ZQ calibration */
777 MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1390001)
779 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPZQHWCTRL, 0x00010000)
780 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
781 MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1380000)
782 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
783 #if BANK_ADDR_BITS > 1
784 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
786 /* DRAM_SDQS[0..1] pad config */
787 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
788 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
789 /* Read delay calibration */
790 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008050) /* precharge all to bank 0 */
791 MXC_DCD_ITEM(MMDC_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
792 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPRDDLHWCTL, 0x00000013)
793 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
795 /* Write delay calibration */
796 MXC_DCD_ITEM(MMDC_MDSCR, 0x04008050) /* precharge all to bank 0 */
797 MXC_DCD_ITEM(MMDC_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
798 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPWRDLHWCTL, 0x00000013)
800 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
801 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
802 #if BANK_ADDR_BITS > 1
803 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
805 MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa138002b)
806 MXC_DCD_ITEM(MMDC_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
807 MXC_DCD_ITEM(MMDC_MAPSR, (16 << 8) | (0 << 0))
808 MXC_DCD_ITEM(MMDC_MDPDC, MDPDC_VAL_1)
810 /* MDSCR: Normal operation */
811 MXC_DCD_ITEM(MMDC_MDSCR, 0x00000000)
812 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MDSCR, 0x00004000)