3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
37 #include <asm/arch/cpu.h>
38 #include <asm/arch/kirkwood.h>
39 #include <asm/arch/mpp.h>
41 #include "../common/common.h"
43 DECLARE_GLOBAL_DATA_PTR;
46 * BOCO FPGA definitions
49 #define REG_CTRL_H 0x02
50 #define MASK_WRL_UNITRUN 0x01
51 #define MASK_RBX_PGY_PRESENT 0x40
52 #define REG_IRQ_CIRQ2 0x2d
53 #define MASK_RBI_DEFECT_16 0x01
55 /* Multi-Purpose Pins Functionality configuration */
56 u32 kwmpp_config[] = {
65 #if defined(CONFIG_SOFT_I2C)
69 #if defined(CONFIG_HARD_I2C)
75 MPP12_GPO, /* Reserved */
78 MPP15_GPIO, /* Not used */
79 MPP16_GPIO, /* Not used */
80 MPP17_GPIO, /* Reserved */
97 MPP34_GPIO, /* CDL1 (input) */
98 MPP35_GPIO, /* CDL2 (input) */
99 MPP36_GPIO, /* MAIN_IRQ (input) */
100 MPP37_GPIO, /* BOARD_LED */
101 MPP38_GPIO, /* Piggy3 LED[1] */
102 MPP39_GPIO, /* Piggy3 LED[2] */
103 MPP40_GPIO, /* Piggy3 LED[3] */
104 MPP41_GPIO, /* Piggy3 LED[4] */
105 MPP42_GPIO, /* Piggy3 LED[5] */
106 MPP43_GPIO, /* Piggy3 LED[6] */
107 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
108 MPP45_GPIO, /* Piggy3 LED[8] */
109 MPP46_GPIO, /* Reserved */
110 MPP47_GPIO, /* Reserved */
111 MPP48_GPIO, /* Reserved */
112 MPP49_GPIO, /* SW_INTOUTn */
116 #if defined(CONFIG_MGCOGE3UN)
118 * Wait for startup OK from mgcoge3ne
120 int startup_allowed(void)
125 * Read CIRQ16 bit (bit 0)
127 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
128 printf("%s: Error reading Boco\n", __func__);
130 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
136 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
138 * These two boards have always ethernet present. Its connected to the mv
141 int ethernet_present(void)
146 int ethernet_present(void)
151 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
152 printf("%s: Error reading Boco\n", __func__);
155 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
162 int initialize_unit_leds(void)
165 * Init the unit LEDs per default they all are
166 * ok apart from bootstat
170 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
171 printf("%s: Error reading Boco\n", __func__);
174 buf |= MASK_WRL_UNITRUN;
175 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
176 printf("%s: Error writing Boco\n", __func__);
182 #if defined(CONFIG_BOOTCOUNT_LIMIT)
183 void set_bootcount_addr(void)
186 unsigned int bootcountaddr;
187 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
188 sprintf((char *)buf, "0x%x", bootcountaddr);
189 setenv("bootcountaddr", (char *)buf);
193 int misc_init_r(void)
198 str = getenv("mach_type");
200 mach_type = simple_strtoul(str, NULL, 10);
201 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
202 gd->bd->bi_arch_number = mach_type;
204 #if defined(CONFIG_MGCOGE3UN)
206 wait_for_ne = getenv("waitforne");
207 if (wait_for_ne != NULL) {
208 if (strcmp(wait_for_ne, "true") == 0) {
211 while (startup_allowed() == 0) {
215 puts("wait\b\b\b\b");
226 initialize_unit_leds();
228 #if defined(CONFIG_BOOTCOUNT_LIMIT)
229 set_bootcount_addr();
234 int board_early_init_f(void)
238 kirkwood_mpp_conf(kwmpp_config);
241 * The FLASH_GPIO_PIN switches between using a
242 * NAND or a SPI FLASH. Set this pin on start
245 tmp = readl(KW_GPIO0_BASE);
246 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
247 tmp = readl(KW_GPIO0_BASE + 4);
248 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
250 #if defined(CONFIG_SOFT_I2C)
251 /* init the GPIO for I2C Bitbang driver */
252 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
253 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
254 kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
255 kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
257 #if defined(CONFIG_SYS_EEPROM_WREN)
258 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
259 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
268 * arch number of board
270 gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
272 /* address of boot parameters */
273 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
278 #if defined(CONFIG_CMD_SF)
279 int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
283 return cmd_usage(cmdtp);
285 if ((strcmp(argv[1], "off") == 0)) {
286 printf("SPI FLASH disabled, NAND enabled\n");
287 /* Multi-Purpose Pins Functionality configuration */
288 kwmpp_config[0] = MPP0_NF_IO2;
289 kwmpp_config[1] = MPP1_NF_IO3;
290 kwmpp_config[2] = MPP2_NF_IO4;
291 kwmpp_config[3] = MPP3_NF_IO5;
293 kirkwood_mpp_conf(kwmpp_config);
294 tmp = readl(KW_GPIO0_BASE);
295 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
296 } else if ((strcmp(argv[1], "on") == 0)) {
297 printf("SPI FLASH enabled, NAND disabled\n");
298 /* Multi-Purpose Pins Functionality configuration */
299 kwmpp_config[0] = MPP0_SPI_SCn;
300 kwmpp_config[1] = MPP1_SPI_MOSI;
301 kwmpp_config[2] = MPP2_SPI_SCK;
302 kwmpp_config[3] = MPP3_SPI_MISO;
304 kirkwood_mpp_conf(kwmpp_config);
305 tmp = readl(KW_GPIO0_BASE);
306 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
308 return cmd_usage(cmdtp);
315 spitoggle, 2, 0, do_spi_toggle,
316 "En-/disable SPI FLASH access",
317 "<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
323 /* dram_init must store complete ramsize in gd->ram_size */
325 gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
330 void dram_init_banksize(void)
334 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
335 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
336 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
341 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
343 #define PHY_LED_SEL 0x18
344 #define PHY_LED0_LINK (0x5)
345 #define PHY_LED1_ACT (0x8<<4)
346 #define PHY_LED2_INT (0xe<<8)
347 #define PHY_SPEC_CTRL 0x1c
348 #define PHY_RGMII_CLK_STABLE (0x1<<10)
349 #define PHY_CLSA (0x1<<1)
351 /* Configure and enable MV88E3018 PHY */
354 char *name = "egiga0";
357 if (miiphy_set_current_dev(name))
360 /* RGMII clk transition on data stable */
361 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0)
362 printf("Error reading PHY spec ctrl reg\n");
363 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
364 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
365 printf("Error writing PHY spec ctrl reg\n");
368 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
369 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
370 printf("Error writing PHY LED reg\n");
373 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
376 /* Configure and enable MV88E1118 PHY on the piggy*/
379 char *name = "egiga0";
381 if (miiphy_set_current_dev(name))
385 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
390 #if defined(CONFIG_HUSH_INIT_VAR)
391 int hush_init_var(void)
398 #if defined(CONFIG_BOOTCOUNT_LIMIT)
399 void bootcount_store(ulong a)
401 volatile ulong *save_addr;
402 volatile ulong size = 0;
404 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
405 size += gd->bd->bi_dram[i].size;
407 save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
408 writel(a, save_addr);
409 writel(BOOTCOUNT_MAGIC, &save_addr[1]);
412 ulong bootcount_load(void)
414 volatile ulong *save_addr;
415 volatile ulong size = 0;
417 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
418 size += gd->bd->bi_dram[i].size;
420 save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
421 if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
424 return readl(save_addr);
428 #if defined(CONFIG_SOFT_I2C)
429 void set_sda(int state)
435 void set_scl(int state)
448 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
452 #if defined(CONFIG_POST)
454 #define KM_POST_EN_L 44
455 #define POST_WORD_OFF 8
457 int post_hotkeys_pressed(void)
459 return !kw_gpio_get_value(KM_POST_EN_L);
462 ulong post_word_load(void)
464 volatile void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
465 return in_le32(addr);
468 void post_word_store(ulong value)
470 volatile void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
471 out_le32(addr, value);
474 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
476 *vstart = CONFIG_SYS_SDRAM_BASE;
478 /* we go up to relocation plus a 1 MB margin */
479 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
485 #if defined(CONFIG_SYS_EEPROM_WREN)
486 int eeprom_write_enable(unsigned dev_addr, int state)
488 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
490 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);