2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
30 #include "../common/common.h"
32 const qe_iop_conf_t qe_iop_conf_tab[] = {
33 /* port pin dir open_drain assign */
36 {0, 1, 3, 0, 2}, /* MDIO */
37 {0, 2, 1, 0, 1}, /* MDC */
40 {1, 14, 1, 0, 1}, /* TxD0 */
41 {1, 15, 1, 0, 1}, /* TxD1 */
42 {1, 20, 2, 0, 1}, /* RxD0 */
43 {1, 21, 2, 0, 1}, /* RxD1 */
44 {1, 18, 1, 0, 1}, /* TX_EN */
45 {1, 26, 2, 0, 1}, /* RX_DV */
46 {1, 27, 2, 0, 1}, /* RX_ER */
47 {1, 24, 2, 0, 1}, /* COL */
48 {1, 25, 2, 0, 1}, /* CRS */
49 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
50 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
53 {5, 0, 1, 0, 2}, /* UART2_SOUT */
54 {5, 2, 1, 0, 1}, /* UART2_RTS */
55 {5, 3, 2, 0, 2}, /* UART2_SIN */
56 {5, 1, 2, 0, 3}, /* UART2_CTS */
59 {0, 0, 0, 0, QE_IOP_TAB_END},
62 static int board_init_i2c_busses (void)
64 I2C_MUX_DEVICE *dev = NULL;
67 /* Set up the Bus for the DTTs */
68 buf = (unsigned char *) getenv ("dtt_bus");
70 dev = i2c_mux_ident_muxstring (buf);
72 printf ("Error couldn't add Bus for DTT\n");
73 printf ("please setup dtt_bus to where your\n");
74 printf ("DTT is found.\n");
79 int board_early_init_r (void)
81 void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
85 * Because of errata in the UCCs, we have to write to the reserved
86 * registers to slow the clocks down.
94 /* enable the PHY on the PIGGY */
95 setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
100 int misc_init_r (void)
102 /* add board specific i2c busses */
103 board_init_i2c_busses ();
107 int fixed_sdram(void)
109 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
114 msize = CONFIG_SYS_DDR_SIZE;
115 for (ddr_size = msize << 20, ddr_size_log2 = 0;
116 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
121 im->sysconf.ddrlaw[0].ar =
122 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
124 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
125 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
126 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
127 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
128 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
129 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
130 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
131 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
132 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
133 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
134 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
135 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
137 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
142 phys_size_t initdram (int board_type)
144 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
145 extern void ddr_enable_ecc (unsigned int dram_size);
147 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
150 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
153 /* DDR SDRAM - Main SODIMM */
154 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
155 msize = fixed_sdram ();
157 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
159 * Initialize DDR ECC byte
161 ddr_enable_ecc (msize * 1024 * 1024);
164 /* return total bus SDRAM size(bytes) -- DDR */
165 return (msize * 1024 * 1024);
168 int checkboard (void)
170 puts ("Board: Keymile kmeter1");
171 if (ethernet_present ())
172 puts (" with PIGGY.");
177 #if defined(CONFIG_OF_BOARD_SETUP)
178 void ft_board_setup (void *blob, bd_t *bd)
180 ft_cpu_setup (blob, bd);
184 #if defined(CONFIG_HUSH_INIT_VAR)
185 extern int ivm_read_eeprom (void);
186 int hush_init_var (void)