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i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework
[karo-tx-uboot.git] / board / kmc / kzm9g / kzm9g.c
1 /*
2  * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
3  * (C) Copyright 2012 Renesas Solutions Corp.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/gpio.h>
12 #include <netdev.h>
13 #include <i2c.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 #define CS0BCR_D (0x06C00400)
18 #define CS4BCR_D (0x16c90400)
19 #define CS0WCR_D (0x55062C42)
20 #define CS4WCR_D (0x1e071dc3)
21
22 #define CMNCR_BROMMD0   (1 << 21)
23 #define CMNCR_BROMMD1   (1 << 22)
24 #define CMNCR_BROMMD    (CMNCR_BROMMD0|CMNCR_BROMMD1)
25 #define VCLKCR1_D       (0x27)
26
27 #define SMSTPCR1_CMT0   (1 << 24)
28 #define SMSTPCR1_I2C0   (1 << 16)
29 #define SMSTPCR3_USB    (1 << 22)
30 #define SMSTPCR3_I2C1   (1 << 23)
31
32 #define PORT32CR (0xE6051020)
33 #define PORT33CR (0xE6051021)
34 #define PORT34CR (0xE6051022)
35 #define PORT35CR (0xE6051023)
36
37 static int cmp_loop(u32 *addr, u32 data, u32 cmp)
38 {
39         int err = -1;
40         int timeout = 100;
41         u32 value;
42
43         while (timeout > 0) {
44                 value = readl(addr);
45                 if ((value & data) == cmp) {
46                         err = 0;
47                         break;
48                 }
49                 timeout--;
50         }
51
52         return err;
53 }
54
55 /* SBSC Init function */
56 static void sbsc_init(struct sh73a0_sbsc *sbsc)
57 {
58         writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
59         writel(0x5, &sbsc->sdgencnt);
60         cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
61
62         writel(0xacc90159, &sbsc->sdcr0);
63         writel(0x00010059, &sbsc->sdcr1);
64         writel(0x50874114, &sbsc->sdwcrc0);
65         writel(0x33199b37, &sbsc->sdwcrc1);
66         writel(0x008f2313, &sbsc->sdwcrc2);
67         writel(0x31020707, &sbsc->sdwcr00);
68         writel(0x0017040a, &sbsc->sdwcr01);
69         writel(0x31020707, &sbsc->sdwcr10);
70         writel(0x0017040a, &sbsc->sdwcr11);
71         writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */
72         writel(0x30000000, &sbsc->sdwcr2);
73
74         writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
75         cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
76
77         writel(0x00002710, &sbsc->sdgencnt);
78         cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
79
80         writel(0x0000003f, &sbsc->sdmracr0);
81         writel(0x0, SDMRA1A);
82         writel(0x000001f4, &sbsc->sdgencnt);
83         cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
84
85         writel(0x0000ff0a, &sbsc->sdmracr0);
86         if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
87                 writel(0x0, SDMRA3A);
88         else
89                 writel(0x0, SDMRA3B);
90
91         writel(0x00000032, &sbsc->sdgencnt);
92         cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
93
94         if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
95                 writel(0x00002201, &sbsc->sdmracr0);
96                 writel(0x0, SDMRA1A);
97                 writel(0x00000402, &sbsc->sdmracr0);
98                 writel(0x0, SDMRA1A);
99                 writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
100                 writel(0x0, SDMRA1A);
101                 writel(0x0, SDMRA2A);
102         } else {
103                 writel(0x00002201, &sbsc->sdmracr0);
104                 writel(0x0, SDMRA1B);
105                 writel(0x00000402, &sbsc->sdmracr0);
106                 writel(0x0, SDMRA1B);
107                 writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
108                 writel(0x0, SDMRA1B);
109                 writel(0x0, SDMRA2B);
110         }
111
112         writel(0x88800004, &sbsc->sdmrtmpcr);
113         writel(0x00000004, &sbsc->sdmrtmpmsk);
114         writel(0xa55a0032, &sbsc->rtcor);
115         writel(0xa55a000c, &sbsc->rtcorh);
116         writel(0xa55a2048, &sbsc->rtcsr);
117         writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
118         writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
119         writel(0xfff20000, &sbsc->zqccr);
120
121         /* SCBS2 only */
122         if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
123                 writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
124                 writel(0xa5390000, &sbsc->dphycnt1);
125                 writel(0x00001200, &sbsc->dphycnt0);
126                 writel(0x07ce0000, &sbsc->dphycnt1);
127                 writel(0x00001247, &sbsc->dphycnt0);
128                 cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
129                 writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
130         }
131 }
132
133 void s_init(void)
134 {
135         struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
136         struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
137         struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
138                 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
139         struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
140         struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
141         struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
142         struct sh73a0_hpb_bscr *hpb_bscr =
143                 (struct sh73a0_hpb_bscr *)HPBSCR_BASE;
144
145         /* Watchdog init */
146         writew(0xA507, &rwdt->rwtcsra0);
147
148         /* Secure control register Init */
149         #define LIFEC_SEC_SRC_BIT       (1 << 15)
150         writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
151
152         clrbits_le32(&cpg->smstpcr3, (1 << 15));
153         clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
154         clrbits_le32(&cpg->smstpcr2, (1 << 18));
155         clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
156         writel(0x0, &cpg->pllecr);
157
158         cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
159         cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
160
161         writel(0x2D000000, &cpg->pll0cr);
162         writel(0x17100000, &cpg->pll1cr);
163         writel(0x96235880, &cpg->frqcrb);
164         cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
165
166         writel(0xB, &cpg->flckcr);
167         clrbits_le32(&cpg->smstpcr0, (1 << 1));
168
169         clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
170         writel(0x0514, &hpb_bscr->smgpiotime);
171         writel(0x0514, &hpb_bscr->smcmt2time);
172         writel(0x0514, &hpb_bscr->smcpgtime);
173         writel(0x0514, &hpb_bscr->smsysctime);
174
175         writel(0x00092000, &cpg->dvfscr4);
176         writel(0x000000DC, &cpg->dvfscr5);
177         writel(0x0, &cpg->pllecr);
178         cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
179
180         /* FRQCR Init */
181         writel(0x0012453C, &cpg->frqcra);
182         writel(0x80431350, &cpg->frqcrb);    /* ETM TRCLK  78MHz */
183         cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
184         writel(0x00000B0B, &cpg->frqcrd);
185         cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
186
187         /* Clock Init */
188         writel(0x00000003, PCLKCR);
189         writel(0x0000012F, &cpg->vclkcr1);
190         writel(0x00000119, &cpg->vclkcr2);
191         writel(0x00000119, &cpg->vclkcr3);
192         writel(0x00000002, &cpg->zbckcr);
193         writel(0x00000005, &cpg->flckcr);
194         writel(0x00000080, &cpg->sd0ckcr);
195         writel(0x00000080, &cpg->sd1ckcr);
196         writel(0x00000080, &cpg->sd2ckcr);
197         writel(0x0000003F, &cpg->fsiackcr);
198         writel(0x0000003F, &cpg->fsibckcr);
199         writel(0x00000080, &cpg->subckcr);
200         writel(0x0000000B, &cpg->spuackcr);
201         writel(0x0000000B, &cpg->spuvckcr);
202         writel(0x0000013F, &cpg->msuckcr);
203         writel(0x00000080, &cpg->hsickcr);
204         writel(0x0000003F, &cpg->mfck1cr);
205         writel(0x0000003F, &cpg->mfck2cr);
206         writel(0x00000107, &cpg->dsitckcr);
207         writel(0x00000313, &cpg->dsi0pckcr);
208         writel(0x0000130D, &cpg->dsi1pckcr);
209         writel(0x2A800E0E, &cpg->dsi0phycr);
210         writel(0x1E000000, &cpg->pll0cr);
211         writel(0x2D000000, &cpg->pll0cr);
212         writel(0x17100000, &cpg->pll1cr);
213         writel(0x27000080, &cpg->pll2cr);
214         writel(0x1D000000, &cpg->pll3cr);
215         writel(0x00080000, &cpg->pll0stpcr);
216         writel(0x000120C0, &cpg->pll1stpcr);
217         writel(0x00012000, &cpg->pll2stpcr);
218         writel(0x00000030, &cpg->pll3stpcr);
219
220         writel(0x0000000B, &cpg->pllecr);
221         cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
222
223         writel(0x000120F0, &cpg->dvfscr3);
224         writel(0x00000020, &cpg->mpmode);
225         writel(0x0000028A, &cpg->vrefcr);
226         writel(0xE4628087, &cpg->rmstpcr0);
227         writel(0xFFFFFFFF, &cpg->rmstpcr1);
228         writel(0x53FFFFFF, &cpg->rmstpcr2);
229         writel(0xFFFFFFFF, &cpg->rmstpcr3);
230         writel(0x00800D3D, &cpg->rmstpcr4);
231         writel(0xFFFFF3FF, &cpg->rmstpcr5);
232         writel(0x00000000, &cpg->smstpcr2);
233         writel(0x00040000, &cpg_srcr->srcr2);
234
235         clrbits_le32(&cpg->pllecr, (1 << 3));
236         cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
237
238         writel(0x00000001, &hpb->hpbctrl6);
239         cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
240
241         writel(0x00001414, &cpg->frqcrd);
242         cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
243
244         writel(0x1d000000, &cpg->pll3cr);
245         setbits_le32(&cpg->pllecr, (1 << 3));
246         cmp_loop(&cpg->pllecr, 0x800, 0x800);
247
248         /* SBSC1 Init*/
249         sbsc_init(sbsc1);
250
251         /* SBSC2 Init*/
252         sbsc_init(sbsc2);
253
254         writel(0x00000b0b, &cpg->frqcrd);
255         cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
256         writel(0xfffffffc, &cpg->cpgxxcs4);
257 }
258
259 int board_early_init_f(void)
260 {
261         struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
262         struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
263         struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
264                 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
265
266         writel(CS0BCR_D, &bsc->cs0bcr);
267         writel(CS4BCR_D, &bsc->cs4bcr);
268         writel(CS0WCR_D, &bsc->cs0wcr);
269         writel(CS4WCR_D, &bsc->cs4wcr);
270
271         clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
272
273         clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
274         clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
275         clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
276         clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
277         writel(VCLKCR1_D, &cpg->vclkcr1);
278
279         /* Setup SCIF4 / workaround */
280         writeb(0x12, PORT32CR);
281         writeb(0x22, PORT33CR);
282         writeb(0x12, PORT34CR);
283         writeb(0x22, PORT35CR);
284
285         return 0;
286 }
287
288 void adjust_core_voltage(void)
289 {
290         u8 data;
291
292         data = 0x35;
293         i2c_set_bus_num(0);
294         i2c_write(0x40, 3, 1, &data, 1);
295 }
296
297 int board_init(void)
298 {
299         adjust_core_voltage();
300         sh73a0_pinmux_init();
301
302     /* SCIFA 4 */
303         gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
304         gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
305         gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
306         gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
307
308         /* Ethernet/SMSC */
309         gpio_request(GPIO_PORT224, NULL);
310         gpio_direction_input(GPIO_PORT224);
311
312         /* SMSC/USB */
313         gpio_request(GPIO_FN_CS4_, NULL);
314
315         /* MMCIF */
316         gpio_request(GPIO_FN_MMCCLK0, NULL);
317         gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
318         gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
319         gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
320         gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
321         gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
322         gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
323         gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
324         gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
325         gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
326
327         /* SDHI */
328         gpio_request(GPIO_FN_SDHIWP0, NULL);
329         gpio_request(GPIO_FN_SDHICD0, NULL);
330         gpio_request(GPIO_FN_SDHICMD0, NULL);
331         gpio_request(GPIO_FN_SDHICLK0,  NULL);
332         gpio_request(GPIO_FN_SDHID0_3,  NULL);
333         gpio_request(GPIO_FN_SDHID0_2,  NULL);
334         gpio_request(GPIO_FN_SDHID0_1,  NULL);
335         gpio_request(GPIO_FN_SDHID0_0,  NULL);
336         gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
337         gpio_request(GPIO_PORT15, NULL);
338         gpio_direction_output(GPIO_PORT15, 1);
339
340         /* I2C */
341         gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
342         gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
343         gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
344         gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
345
346         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
347
348         return 0;
349 }
350
351 const struct rmobile_sysinfo sysinfo = {
352         CONFIG_RMOBILE_BOARD_STRING
353 };
354
355 int dram_init(void)
356 {
357         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
358         return 0;
359 }
360
361 int board_eth_init(bd_t *bis)
362 {
363         int ret = 0;
364 #ifdef CONFIG_SMC911X
365         ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
366 #endif
367         return ret;
368 }
369
370 void reset_cpu(ulong addr)
371 {
372         /* Soft Power On Reset */
373         writel((1 << 31), RESCNT2);
374 }