3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
32 ulong flash_get_size(ulong base, int banknum);
33 int misc_init_r_kbd(void);
35 int board_early_init_f(void)
37 u32 sdr0_pfc1, sdr0_pfc2;
40 /* PLB Write pipelining disabled. Denali Core workaround */
41 mtdcr(PLB0_ACR, 0xDE000000);
42 mtdcr(PLB1_ACR, 0xDE000000);
44 /*--------------------------------------------------------------------
45 * Setup the interrupt controller polarities, triggers, etc.
46 *-------------------------------------------------------------------*/
47 mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
48 mtdcr(UIC0ER, 0x00000000); /* disable all */
49 mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
50 mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
51 mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
52 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
53 mtdcr(UIC0SR, 0xffffffff); /* clear all */
55 mtdcr(UIC1SR, 0xffffffff); /* clear all */
56 mtdcr(UIC1ER, 0x00000000); /* disable all */
57 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
58 mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
59 mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
60 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
61 mtdcr(UIC1SR, 0xffffffff); /* clear all */
63 mtdcr(UIC2SR, 0xffffffff); /* clear all */
64 mtdcr(UIC2ER, 0x00000000); /* disable all */
65 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
66 mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
67 mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
68 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
69 mtdcr(UIC2SR, 0xffffffff); /* clear all */
71 /* Trace Pins are disabled. SDR0_PFC0 Register */
72 mtsdr(SDR0_PFC0, 0x0);
74 /* select Ethernet pins */
75 mfsdr(SDR0_PFC1, sdr0_pfc1);
77 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
78 SDR0_PFC1_SELECT_CONFIG_6;
79 mfsdr(SDR0_PFC2, sdr0_pfc2);
80 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
81 SDR0_PFC2_SELECT_CONFIG_6;
83 /* enable SPI (SCP) */
84 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
86 mtsdr(SDR0_PFC2, sdr0_pfc2);
87 mtsdr(SDR0_PFC1, sdr0_pfc1);
89 mtsdr(SDR0_PFC4, 0x80000000);
91 /* PCI arbiter disabled */
92 /* PCI Host Configuration disbaled */
93 mfsdr(SDR0_PCI0, reg);
95 mtsdr(SDR0_PCI0, 0x00000000 | reg);
97 gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
99 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
100 gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);
102 reg = 0; /* reuse as counter */
103 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
104 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
105 & ~CONFIG_SYS_DSPIC_TEST_MASK);
106 while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
109 gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
110 if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
111 /* set "boot error" flag */
112 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
113 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
114 CONFIG_SYS_DSPIC_TEST_MASK);
120 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
121 * upon reset, and with the first reset upon powerup, the addresses are
122 * not latched reliable, since the IRQ line is multiplexed with an
123 * MDIO address. A 2nd reset at this time will make sure, that the
124 * correct address is latched.
126 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
127 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
129 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
130 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
132 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
133 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
138 /*---------------------------------------------------------------------------+
140 +---------------------------------------------------------------------------*/
141 int misc_init_r(void)
146 unsigned long usb2d0cr = 0;
147 unsigned long usb2phy0cr, usb2h0cr = 0;
148 unsigned long sdr0_pfc1;
154 /* Re-do sizing to get full correct info */
156 /* adjust flash start and offset */
157 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
158 gd->bd->bi_flashoffset = 0;
161 switch (gd->bd->bi_flashsize) {
187 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
191 * Re-check to get correct base address
193 flash_get_size(gd->bd->bi_flashstart, 0);
195 /* Monitor protection ON by default */
196 (void)flash_protect(FLAG_PROTECT_SET,
197 -CONFIG_SYS_MONITOR_LEN,
201 /* Env protection ON by default */
202 (void)flash_protect(FLAG_PROTECT_SET,
203 CONFIG_ENV_ADDR_REDUND,
204 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
211 mfsdr(SDR0_PFC1, sdr0_pfc1);
212 mfsdr(SDR0_USB0, usb2d0cr);
213 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
214 mfsdr(SDR0_USB2H0CR, usb2h0cr);
216 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
217 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
218 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
219 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
220 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
221 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
222 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
223 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
224 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
225 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
227 /* An 8-bit/60MHz interface is the only possible alternative
228 when connecting the Device to the PHY */
229 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
230 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
232 mtsdr(SDR0_PFC1, sdr0_pfc1);
233 mtsdr(SDR0_USB0, usb2d0cr);
234 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
235 mtsdr(SDR0_USB2H0CR, usb2h0cr);
241 mtsdr(SDR0_SRST1, 0x00000000);
243 mtsdr(SDR0_SRST0, 0x00000000);
245 printf("USB: Host(int phy) Device(ext phy)\n");
248 * Clear PLB4A0_ACR[WRP]
249 * This fix will make the MAL burst disabling patch for the Linux
250 * EMAC driver obsolete.
252 reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
253 mtdcr(PLB4_ACR, reg);
256 * Init matrix keyboard
265 char *s = getenv("serial#");
267 printf("Board: lwmon5");
278 /*************************************************************************
281 * This routine is called just prior to registering the hose and gives
282 * the board the opportunity to check things. Returning a value of zero
283 * indicates that things are bad & PCI initialization should be aborted.
285 * Different boards may wish to customize the pci controller structure
286 * (add regions, override default access routines, etc) or perform
287 * certain pre-initialization actions.
289 ************************************************************************/
290 #if defined(CONFIG_PCI)
291 int pci_pre_init(struct pci_controller *hose)
295 /*-------------------------------------------------------------------------+
296 | Set priority for all PLB3 devices to 0.
297 | Set PLB3 arbiter to fair mode.
298 +-------------------------------------------------------------------------*/
299 mfsdr(SD0_AMP1, addr);
300 mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
301 addr = mfdcr(PLB3_ACR);
302 mtdcr(PLB3_ACR, addr | 0x80000000);
304 /*-------------------------------------------------------------------------+
305 | Set priority for all PLB4 devices to 0.
306 +-------------------------------------------------------------------------*/
307 mfsdr(SD0_AMP0, addr);
308 mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
309 addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
310 mtdcr(PLB4_ACR, addr);
312 /*-------------------------------------------------------------------------+
313 | Set Nebula PLB4 arbiter to fair mode.
314 +-------------------------------------------------------------------------*/
316 addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
317 addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
318 addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
319 addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
320 mtdcr(PLB0_ACR, addr);
323 addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
324 addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
325 addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
326 addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
327 mtdcr(PLB1_ACR, addr);
331 #endif /* defined(CONFIG_PCI) */
333 /*************************************************************************
336 ************************************************************************/
337 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
338 void pci_master_init(struct pci_controller *hose)
340 unsigned short temp_short;
342 /*--------------------------------------------------------------------------+
343 | Write the PowerPC440 EP PCI Configuration regs.
344 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
345 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
346 +--------------------------------------------------------------------------*/
347 pci_read_config_word(0, PCI_COMMAND, &temp_short);
348 pci_write_config_word(0, PCI_COMMAND,
349 temp_short | PCI_COMMAND_MASTER |
352 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
354 void hw_watchdog_reset(void)
357 #if defined(CONFIG_WD_MAX_RATE)
358 unsigned long long ct = get_ticks();
361 * Don't allow watch-dog triggering more frequently than
362 * the predefined value CONFIG_WD_MAX_RATE [ticks].
364 if (ct >= gd->wdt_last) {
365 if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
368 /* Time base counter had been reset */
369 if (((unsigned long long)(-1) - gd->wdt_last + ct) <
373 gd->wdt_last = get_ticks();
377 * Toggle watchdog output
379 val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
380 gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
383 int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
390 if ((strcmp(argv[1], "on") == 0)) {
391 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
392 } else if ((strcmp(argv[1], "off") == 0)) {
393 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
404 eepromwp, 2, 0, do_eeprom_wp,
405 "eeprom write protect off/on",
406 "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
409 #if defined(CONFIG_VIDEO)
410 #include <video_fb.h>
413 extern GraphicDevice mb862xx;
415 static const gdc_regs init_regs [] =
417 {0x0100, 0x00000f00},
418 {0x0020, 0x801401df},
419 {0x0024, 0x00000000},
420 {0x0028, 0x00000000},
421 {0x002c, 0x00000000},
422 {0x0110, 0x00000000},
423 {0x0114, 0x00000000},
424 {0x0118, 0x01df0280},
425 {0x0004, 0x031f0000},
426 {0x0008, 0x027f027f},
427 {0x000c, 0x015f028f},
428 {0x0010, 0x020c0000},
429 {0x0014, 0x01df01ea},
430 {0x0018, 0x00000000},
431 {0x001c, 0x01e00280},
432 {0x0100, 0x80010f00},
436 const gdc_regs *board_get_regs (void)
441 /* Returns Lime base address */
442 unsigned int board_video_init (void)
445 * Reset Lime controller
447 gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
449 gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
451 mb862xx.winSizeX = 640;
452 mb862xx.winSizeY = 480;
453 mb862xx.gdfBytesPP = 2;
454 mb862xx.gdfIndex = GDF_15BIT_555RGB;
456 return CONFIG_SYS_LIME_BASE_0;
459 #define DEFAULT_BRIGHTNESS 0x64
461 static void board_backlight_brightness(int brightness)
463 if (brightness > 0) {
464 /* pwm duty, lamp on */
465 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
466 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
469 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
470 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
474 void board_backlight_switch (int flag)
480 param = getenv("brightness");
481 rc = param ? simple_strtol(param, NULL, 10) : -1;
483 rc = DEFAULT_BRIGHTNESS;
487 board_backlight_brightness(rc);
490 #if defined(CONFIG_CONSOLE_EXTRA_INFO)
492 * Return text to be printed besides the logo.
494 void video_get_info_str (int line_number, char *info)
496 if (line_number == 1) {
497 strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
503 #endif /* CONFIG_VIDEO */
505 void board_reset(void)
507 gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);