3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * (C) Copyright 2001-2004
6 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
7 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/processor.h>
16 /* ------------------------------------------------------------------------- */
19 #define DBG(x...) printf(x)
24 #define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (cpu output)*/
25 #define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (cpu output) */
26 #define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (cpu output) */
27 #define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (cpu input) */
28 #define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (cpu input) */
30 #define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
31 #define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
32 #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
39 #define FPGA_WRITE_1 { \
40 SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \
41 SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \
42 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
43 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
45 #define FPGA_WRITE_0 { \
46 SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set clock to 0 */ \
47 SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \
48 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 ); /* set clock to 1 */ \
49 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
51 #define FPGA_WRITE_1 { \
52 SET_FPGA(OLD_VAL | FPGA_PRG | 0 | FPGA_DATA); /* set data to 1 */ \
53 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
55 #define FPGA_WRITE_0 { \
56 SET_FPGA(OLD_VAL | FPGA_PRG | 0 | 0 ); /* set data to 0 */ \
57 SET_FPGA(OLD_VAL | FPGA_PRG | FPGA_CLK | 0 );} /* set data to 1 */
60 static int fpga_boot(unsigned char *fpgadata, int size)
66 /* display infos on fpgaimage */
69 len = fpgadata[index];
70 DBG("FPGA: %s\n", &(fpgadata[index+1]));
74 /* search for preamble 0xFFFFFFFF */
76 if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
77 (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
78 break; /* preamble found */
83 DBG("FPGA: configdata starts at position 0x%x\n",index);
84 DBG("FPGA: length of fpga-data %d\n", size-index);
87 * Setup port pins for fpga programming
89 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
91 DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
92 DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
95 * Init fpga by asserting and deasserting PROGRAM*
97 SET_FPGA(0 | FPGA_CLK | FPGA_DATA); /* set prog active */
99 /* Wait for FPGA init line low */
101 while (FPGA_INIT_STATE) {
102 udelay(1000); /* wait 1ms */
103 /* Check for timeout - 100us max, so use 3ms */
105 DBG("FPGA: Booting failed!\n");
106 return ERROR_FPGA_PRG_INIT_LOW;
110 DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
111 DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
113 /* deassert PROGRAM* */
114 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set prog inactive */
116 /* Wait for FPGA end of init period . */
118 while (!(FPGA_INIT_STATE)) {
119 udelay(1000); /* wait 1ms */
120 /* Check for timeout */
122 DBG("FPGA: Booting failed!\n");
123 return ERROR_FPGA_PRG_INIT_HIGH;
127 DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
128 DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
130 DBG("write configuration data into fpga\n");
131 /* write configuration-data into fpga... */
134 * Load uncompressed image into fpga
136 for (i=index; i<size; i++) {
137 for (j=0; j<8; j++) {
138 if ((fpgadata[i] & 0x80) == 0x80) {
147 DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
148 DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
151 * Check if fpga's DONE signal - correctly booted ?
154 /* Wait for FPGA end of programming period . */
156 while (!(FPGA_DONE_STATE)) {
157 udelay(1000); /* wait 1ms */
158 /* Check for timeout */
160 DBG("FPGA: Booting failed!\n");
161 return ERROR_FPGA_PRG_DONE;
165 DBG("FPGA: Booting successful!\n");