2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
12 #include <asm/addrspace.h>
13 #include <asm/regdef.h>
14 #include <asm/malta.h>
16 #ifdef CONFIG_SYS_BIG_ENDIAN
17 #define CPU_TO_GT32(_x) ((_x))
19 #define CPU_TO_GT32(_x) ( \
20 (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
21 (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
32 * Load BAR registers of GT64120 as done by YAMON
34 * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
35 * to the barebox mailing list.
36 * The subject of the original patch:
37 * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
39 * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
41 * based on write_bootloader() in qemu.git/hw/mips_malta.c
42 * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
45 /* move GT64120 registers from 0x14000000 to 0x1be00000 */
46 li t1, KSEG1ADDR(GT_DEF_BASE)
47 li t0, CPU_TO_GT32(0xdf000000)
50 /* setup MEM-to-PCI0 mapping */
51 li t1, KSEG1ADDR(MALTA_GT_BASE)
53 /* setup PCI0 io window to 0x18000000-0x181fffff */
54 li t0, CPU_TO_GT32(0xc0000000)
55 sw t0, GT_PCI0IOLD_OFS(t1)
56 li t0, CPU_TO_GT32(0x40000000)
57 sw t0, GT_PCI0IOHD_OFS(t1)
59 /* setup PCI0 mem windows */
60 li t0, CPU_TO_GT32(0x80000000)
61 sw t0, GT_PCI0M0LD_OFS(t1)
62 li t0, CPU_TO_GT32(0x3f000000)
63 sw t0, GT_PCI0M0HD_OFS(t1)
65 li t0, CPU_TO_GT32(0xc1000000)
66 sw t0, GT_PCI0M1LD_OFS(t1)
67 li t0, CPU_TO_GT32(0x5e000000)
68 sw t0, GT_PCI0M1HD_OFS(t1)