3 * Custom IDEAS, Inc. <www.cideas.com>
4 * Jon Diekema <diekema@cideas.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */
27 #define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */
28 #define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
29 #define MAX_64x_SAMPLE_RATE 86805 /* Maximum 64x sample rate */
31 #define KHZ ((uint)1000)
32 #define MHZ ((uint)(1000 * KHZ))
34 #define MCLK_BRG 3 /* MCLK, Master CLocK for the A/D & D/A */
35 #define SCLK_BRG 7 /* SCLK, Sample CLocK for the A/D & D/A */
36 #define LRCLK_BRG 5 /* LRCLK, L/R CLocK for the A/D & D/A */
37 /* 0 == BRG1 (used for SMC1) */
38 /* 1 == BRG2 (used for SMC2) */
39 /* 2 == BRG3 (used for SCC1) */
40 /* 3 == BRG4 (MCLK) */
42 /* 5 == BRG6 (LRCLK) */
44 /* 7 == BRG8 (SCLK) */
46 #define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */
47 #define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
48 /* LRCLK = SCLK / SCLK_DIVISOR */
50 #define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */
51 #define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */
52 /* The 8260 (Mask B.3) seems to have */
53 /* problems generating SCLK from MCLK */
55 #define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */
56 /* The 8260 (Mask B.3) seems to have */
57 /* problems generating LRCLK from SCLK */
59 #define NUM_LRCLKS_TO_STABILIZE 1 /* Number of LRCLK period (sample) */
60 /* to wait for the clock to stabilize */
62 #define CPM_CLK (gd->bd->bi_cpmfreq)
64 #define BRG_INT_CLK (CPM_CLK * 2 / DFBRG)
65 /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
66 /* BRG = CPM * 2 / 4 */
69 #define CPM_BRG_EXTC_MASK ((uint)0x0000C000)
70 #define CPM_BRG_EXTC_SHIFT 14
72 #define CPM_BRG_DIV16_MASK ((uint)0x00000001)
73 #define CPM_BRG_DIV16_SHIFT 1
75 #define CPM_BRG_EXTC_BRGCLK 0
76 #define CPM_BRG_EXTC_CLK3 1
77 #define CPM_BRG_EXTC_CLK9 CPM_BRG_EXTC_CLK3
78 #define CPM_BRG_EXTC_CLK5 2
79 #define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5
81 #define IM_BRGC1 ((uint *)0xf00119f0)
82 #define IM_BRGC2 ((uint *)0xf00119f4)
83 #define IM_BRGC3 ((uint *)0xf00119f8)
84 #define IM_BRGC4 ((uint *)0xf00119fc)
85 #define IM_BRGC5 ((uint *)0xf00115f0)
86 #define IM_BRGC6 ((uint *)0xf00115f4)
87 #define IM_BRGC7 ((uint *)0xf00115f8)
88 #define IM_BRGC8 ((uint *)0xf00115fc)
91 * External declarations
94 extern int Daq64xSampling;
96 extern void Daq_BRG_Reset(uint brg);
97 extern void Daq_BRG_Run(uint brg);
99 extern void Daq_BRG_Disable(uint brg);
100 extern void Daq_BRG_Enable(uint brg);
102 extern uint Daq_BRG_Get_Div16(uint brg);
103 extern void Daq_BRG_Set_Div16(uint brg, uint div16);
105 extern uint Daq_BRG_Get_Count(uint brg);
106 extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
108 extern uint Daq_BRG_Get_ExtClk(uint brg);
109 extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
110 extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
112 extern uint Daq_BRG_Rate(uint brg);
114 extern uint Daq_Get_SampleRate(void);
116 extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
117 extern void Daq_Stop_Clocks(void);
118 extern void Daq_Start_Clocks(int sample_rate);
119 extern void Daq_Display_Clocks(void);