2 * Copyright (C) 2012 Samsung Electronics
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/mmc.h>
34 #include <asm/arch/pinmux.h>
35 #include <asm/arch/power.h>
36 #include <asm/arch/sromc.h>
37 #include <asm/arch/dp_info.h>
38 #include <power/pmic.h>
39 #include <power/max77686_pmic.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 #ifdef CONFIG_USB_EHCI_EXYNOS
44 int board_usb_vbus_init(void)
46 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
47 samsung_get_base_gpio_part1();
49 /* Enable VBUS power switch */
50 s5p_gpio_direction_output(&gpio1->x2, 6, 1);
52 /* VBUS turn ON time */
61 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
62 #ifdef CONFIG_EXYNOS_SPI
65 #ifdef CONFIG_USB_EHCI_EXYNOS
66 board_usb_vbus_init();
73 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
74 + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
75 + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
76 + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
77 + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
78 + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
79 + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
80 + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
84 #if defined(CONFIG_POWER)
85 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
90 ret = pmic_reg_read(p, reg, &val);
92 debug("%s: PMIC %d register read failed\n", __func__, reg);
96 ret = pmic_reg_write(p, reg, val);
98 debug("%s: PMIC %d register write failed\n", __func__, reg);
104 int power_init_board(void)
110 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
112 if (pmic_init(I2C_PMIC))
115 p = pmic_get("MAX77686_PMIC");
122 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
125 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
126 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
130 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
131 MAX77686_BUCK1OUT_1V)) {
132 debug("%s: PMIC %d register write failed\n", __func__,
133 MAX77686_REG_PMIC_BUCK1OUT);
137 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
138 MAX77686_BUCK1CTRL_EN))
142 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
143 MAX77686_BUCK2DVS1_1_3V)) {
144 debug("%s: PMIC %d register write failed\n", __func__,
145 MAX77686_REG_PMIC_BUCK2DVS1);
149 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
150 MAX77686_BUCK2CTRL_ON))
154 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
155 MAX77686_BUCK3DVS1_1_0125V)) {
156 debug("%s: PMIC %d register write failed\n", __func__,
157 MAX77686_REG_PMIC_BUCK3DVS1);
161 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
162 MAX77686_BUCK3CTRL_ON))
166 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
167 MAX77686_BUCK4DVS1_1_2V)) {
168 debug("%s: PMIC %d register write failed\n", __func__,
169 MAX77686_REG_PMIC_BUCK4DVS1);
173 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
174 MAX77686_BUCK3CTRL_ON))
178 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
179 MAX77686_LD02CTRL1_1_5V | EN_LDO))
183 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
184 MAX77686_LD03CTRL1_1_8V | EN_LDO))
188 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
189 MAX77686_LD05CTRL1_1_8V | EN_LDO))
193 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
194 MAX77686_LD10CTRL1_1_8V | EN_LDO))
201 void dram_init_banksize(void)
203 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
204 gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
206 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
207 gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
209 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
210 gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
212 gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
213 gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
215 gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
216 gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
218 gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
219 gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
221 gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
222 gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
224 gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
225 gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
229 #ifdef CONFIG_OF_CONTROL
230 static int decode_sromc(const void *blob, struct fdt_sromc *config)
235 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
237 debug("Could not find SROMC node\n");
241 config->bank = fdtdec_get_int(blob, node, "bank", 0);
242 config->width = fdtdec_get_int(blob, node, "width", 2);
244 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
245 FDT_SROM_TIMING_COUNT);
247 debug("Could not decode SROMC configuration\n");
248 return -FDT_ERR_NOTFOUND;
255 int board_eth_init(bd_t *bis)
257 #ifdef CONFIG_SMC911X
258 u32 smc_bw_conf, smc_bc_conf;
259 struct fdt_sromc config;
260 fdt_addr_t base_addr;
263 #ifdef CONFIG_OF_CONTROL
264 node = decode_sromc(gd->fdt_blob, &config);
266 debug("%s: Could not find sromc configuration\n", __func__);
269 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
271 debug("%s: Could not find lan9215 configuration\n", __func__);
275 /* We now have a node, so any problems from now on are errors */
276 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
277 if (base_addr == FDT_ADDR_T_NONE) {
278 debug("%s: Could not find lan9215 address\n", __func__);
282 /* Non-FDT configuration - bank number and timing parameters*/
283 config.bank = CONFIG_ENV_SROM_BANK;
286 config.timing[FDT_SROM_TACS] = 0x01;
287 config.timing[FDT_SROM_TCOS] = 0x01;
288 config.timing[FDT_SROM_TACC] = 0x06;
289 config.timing[FDT_SROM_TCOH] = 0x01;
290 config.timing[FDT_SROM_TAH] = 0x0C;
291 config.timing[FDT_SROM_TACP] = 0x09;
292 config.timing[FDT_SROM_PMC] = 0x01;
293 base_addr = CONFIG_SMC911X_BASE;
296 /* Ethernet needs data bus width of 16 bits */
297 if (config.width != 2) {
298 debug("%s: Unsupported bus width %d\n", __func__,
302 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
303 | SROMC_BYTE_ENABLE(config.bank);
305 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
306 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
307 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
308 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
309 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
310 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
311 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
313 /* Select and configure the SROMC bank */
314 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
315 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
316 return smc911x_initialize(0, base_addr);
321 #ifdef CONFIG_DISPLAY_BOARDINFO
324 printf("\nBoard: SMDK5250\n");
330 #ifdef CONFIG_GENERIC_MMC
331 int board_mmc_init(bd_t *bis)
335 err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
337 debug("SDMMC0 not configured\n");
341 err = s5p_mmc_init(0, 8);
346 static int board_uart_init(void)
350 err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
352 debug("UART0 not configured\n");
356 err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
358 debug("UART1 not configured\n");
362 err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
364 debug("UART2 not configured\n");
368 err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
370 debug("UART3 not configured\n");
377 #ifdef CONFIG_BOARD_EARLY_INIT_F
378 int board_early_init_f(void)
381 err = board_uart_init();
383 debug("UART init failed\n");
386 #ifdef CONFIG_SYS_I2C_INIT_BOARD
387 board_i2c_init(gd->fdt_blob);
394 void cfg_lcd_gpio(void)
396 struct exynos5_gpio_part1 *gpio1 =
397 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
400 s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
401 s5p_gpio_set_value(&gpio1->b2, 0, 1);
404 s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
405 s5p_gpio_set_value(&gpio1->x1, 5, 1);
407 /* Set Hotplug detect for DP */
408 s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
411 vidinfo_t panel_info = {
417 .vl_clkp = CONFIG_SYS_LOW,
418 .vl_hsp = CONFIG_SYS_LOW,
419 .vl_vsp = CONFIG_SYS_LOW,
420 .vl_dp = CONFIG_SYS_LOW,
421 .vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
423 /* wDP panel timing infomation */
431 .vl_cmd_allow_len = 0xf,
434 .cfg_gpio = cfg_lcd_gpio,
435 .backlight_on = NULL,
436 .lcd_power_on = NULL,
438 .dual_lcd_enabled = 0,
443 .interface_mode = FIMD_RGB_INTERFACE,
447 static struct edp_device_info edp_info = {
460 .lt_status = DP_LT_NONE,
464 .bist_mode = DP_DISABLE,
465 .bist_pattern = NO_PATTERN,
466 .h_sync_polarity = 0,
467 .v_sync_polarity = 0,
469 .color_space = COLOR_RGB,
470 .dynamic_range = VESA,
471 .ycbcr_coeff = COLOR_YCBCR601,
472 .color_depth = COLOR_8,
476 static struct exynos_dp_platform_data dp_platform_data = {
477 .phy_enable = set_dp_phy_ctrl,
478 .edp_dev_info = &edp_info,
481 void init_panel_info(vidinfo_t *vid)
483 vid->rgb_mode = MODE_RGB_P,
485 exynos_set_dp_platform_data(&dp_platform_data);