2 * Machine Specific Values for TRATS board based on EXYNOS4210
4 * Copyright (C) 2011 Samsung Electronics
5 * Heungjun Kim <riverful.kim@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _TRATS_SETUP_H
11 #define _TRATS_SETUP_H
14 #include <asm/arch/cpu.h>
16 /* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
17 #define MUX_HPM_SEL_MOUTAPLL 0x0
18 #define MUX_HPM_SEL_SCLKMPLL 0x1
19 #define MUX_CORE_SEL_MOUTAPLL 0x0
20 #define MUX_CORE_SEL_SCLKMPLL 0x1
21 #define MUX_MPLL_SEL_FILPLL 0x0
22 #define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
23 #define MUX_APLL_SEL_FILPLL 0x0
24 #define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
25 #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
26 | (MUX_CORE_SEL_MOUTAPLL << 16) \
27 | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
28 | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
31 #define APLL_RATIO 0x0
32 #define PCLK_DBG_RATIO 0x1
34 #define PERIPH_RATIO 0x3
35 #define COREM1_RATIO 0x7
36 #define COREM0_RATIO 0x3
37 #define CORE_RATIO 0x0
38 #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
39 | (PCLK_DBG_RATIO << 20) \
41 | (PERIPH_RATIO << 12) \
42 | (COREM1_RATIO << 8) \
43 | (COREM0_RATIO << 4) \
48 #define COPY_RATIO 0x3
49 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
52 #define CORE_TIMERS_RATIO 0x1
53 #define COPY2_RATIO 0x3
54 #define DMCP_RATIO 0x1
55 #define DMCD_RATIO 0x1
57 #define DPHY_RATIO 0x1
58 #define ACP_PCLK_RATIO 0x1
60 #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
61 | (COPY2_RATIO << 24) \
62 | (DMCP_RATIO << 20) \
63 | (DMCD_RATIO << 16) \
66 | (ACP_PCLK_RATIO << 4) \
71 #define DVSEM_RATIO 0x1
73 #define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
74 | (DVSEM_RATIO << 16) \
78 #define MUX_ONENAND_SEL_ACLK_133 0x0
79 #define MUX_ONENAND_SEL_ACLK_160 0x1
80 #define MUX_ACLK_133_SEL_SCLKMPLL 0x0
81 #define MUX_ACLK_133_SEL_SCLKAPLL 0x1
82 #define MUX_ACLK_160_SEL_SCLKMPLL 0x0
83 #define MUX_ACLK_160_SEL_SCLKAPLL 0x1
84 #define MUX_ACLK_100_SEL_SCLKMPLL 0x0
85 #define MUX_ACLK_100_SEL_SCLKAPLL 0x1
86 #define MUX_ACLK_200_SEL_SCLKMPLL 0x0
87 #define MUX_ACLK_200_SEL_SCLKAPLL 0x1
88 #define MUX_VPLL_SEL_FINPLL 0x0
89 #define MUX_VPLL_SEL_FOUTVPLL 0x1
90 #define MUX_EPLL_SEL_FINPLL 0x0
91 #define MUX_EPLL_SEL_FOUTEPLL 0x1
92 #define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
93 #define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
94 #define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \
95 | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
96 | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
97 | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
98 | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
99 | (MUX_VPLL_SEL_FOUTVPLL << 8) \
100 | (MUX_EPLL_SEL_FOUTEPLL << 4) \
101 | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
104 #define ONENAND_RATIO 0x0
105 #define ACLK_133_RATIO 0x5
106 #define ACLK_160_RATIO 0x4
107 #define ACLK_100_RATIO 0x7
108 #define ACLK_200_RATIO 0x3
109 #define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
110 | (ACLK_133_RATIO << 12)\
111 | (ACLK_160_RATIO << 8) \
112 | (ACLK_100_RATIO << 4) \
113 | (ACLK_200_RATIO << 0))
115 /* CLK_DIV_LEFTBUS */
116 #define GPL_RATIO 0x1
117 #define GDL_RATIO 0x3
118 #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
120 /* CLK_DIV_RIGHTBUS */
121 #define GPR_RATIO 0x1
122 #define GDR_RATIO 0x3
123 #define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
125 /* CLK_SRS_FSYS: 6 = SCLKMPLL */
126 #define SATA_SEL_SCLKMPLL 0
127 #define SATA_SEL_SCLKAPLL 1
129 #define MMC_SEL_XXTI 0
130 #define MMC_SEL_XUSBXTI 1
131 #define MMC_SEL_SCLK_HDMI24M 2
132 #define MMC_SEL_SCLK_USBPHY0 3
133 #define MMC_SEL_SCLK_USBPHY1 4
134 #define MMC_SEL_SCLK_HDMIPHY 5
135 #define MMC_SEL_SCLKMPLL 6
136 #define MMC_SEL_SCLKEPLL 7
137 #define MMC_SEL_SCLKVPLL 8
139 #define MMCC0_SEL MMC_SEL_SCLKMPLL
140 #define MMCC1_SEL MMC_SEL_SCLKMPLL
141 #define MMCC2_SEL MMC_SEL_SCLKMPLL
142 #define MMCC3_SEL MMC_SEL_SCLKMPLL
143 #define MMCC4_SEL MMC_SEL_SCLKMPLL
144 #define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
145 | (MMCC4_SEL << 16) \
146 | (MMCC3_SEL << 12) \
151 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
152 /* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */
153 #define MMC0_RATIO 0xF
154 #define MMC0_PRE_RATIO 0x0
155 #define MMC1_RATIO 0xF
156 #define MMC1_PRE_RATIO 0x0
157 #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
158 | (MMC1_RATIO << 16) \
159 | (MMC0_PRE_RATIO << 8) \
162 /* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */
163 #define MMC2_RATIO 0xF
164 #define MMC2_PRE_RATIO 0x0
165 #define MMC3_RATIO 0xF
166 #define MMC3_PRE_RATIO 0x0
167 #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
168 | (MMC3_RATIO << 16) \
169 | (MMC2_PRE_RATIO << 8) \
172 /* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */
173 #define MMC4_RATIO 0xF
174 #define MMC4_PRE_RATIO 0x0
175 #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
179 #define UART_SEL_XXTI 0
180 #define UART_SEL_XUSBXTI 1
181 #define UART_SEL_SCLK_HDMI24M 2
182 #define UART_SEL_SCLK_USBPHY0 3
183 #define UART_SEL_SCLK_USBPHY1 4
184 #define UART_SEL_SCLK_HDMIPHY 5
185 #define UART_SEL_SCLKMPLL 6
186 #define UART_SEL_SCLKEPLL 7
187 #define UART_SEL_SCLKVPLL 8
189 #define UART0_SEL UART_SEL_SCLKMPLL
190 #define UART1_SEL UART_SEL_SCLKMPLL
191 #define UART2_SEL UART_SEL_SCLKMPLL
192 #define UART3_SEL UART_SEL_SCLKMPLL
193 #define UART4_SEL UART_SEL_SCLKMPLL
194 #define UART5_SEL UART_SEL_SCLKMPLL
195 #define CLK_SRC_PERIL0_VAL ((UART5_SEL << 16) \
196 | (UART4_SEL << 12) \
197 | (UART3_SEL << 12) \
202 /* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */
204 #define UART0_RATIO 7
205 #define UART1_RATIO 7
206 #define UART2_RATIO 7
207 #define UART3_RATIO 4
208 #define UART4_RATIO 7
209 #define UART5_RATIO 7
210 #define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \
211 | (UART4_RATIO << 12) \
212 | (UART3_RATIO << 12) \
213 | (UART2_RATIO << 8) \
214 | (UART1_RATIO << 4) \
215 | (UART0_RATIO << 0))
218 #define SLIMBUS_RATIO 0x0
219 #define PWM_RATIO 0x8
220 #define CLK_DIV_PERIL3_VAL ((SLIMBUS_RATIO << 4) \
223 /* Required period to generate a stable clock output */
225 #define PLL_LOCKTIME 0x1C20
230 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
235 /* APLL_CON0: 800MHz */
236 #define APLL_MDIV 0xC8
237 #define APLL_PDIV 0x6
238 #define APLL_SDIV 0x1
239 #define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
242 #define APLL_AFC_ENB 0x1
243 #define APLL_AFC 0x1C
244 #define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
246 /* MPLL_CON0: 800MHz */
247 #define MPLL_MDIV 0xC8
248 #define MPLL_PDIV 0x6
249 #define MPLL_SDIV 0x1
250 #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
253 #define MPLL_AFC_ENB 0x1
254 #define MPLL_AFC 0x1C
255 #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
257 /* EPLL_CON0: 96MHz */
258 #define EPLL_MDIV 0x30
259 #define EPLL_PDIV 0x3
260 #define EPLL_SDIV 0x2
261 #define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
265 #define EPLL_CON1_VAL (EPLL_K >> 0)
267 /* VPLL_CON0: 108MHz */
268 #define VPLL_MDIV 0x35
269 #define VPLL_PDIV 0x3
270 #define VPLL_SDIV 0x2
271 #define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
274 #define VPLL_SSCG_EN DISABLE
275 #define VPLL_SEL_PF_DN_SPREAD 0x0
276 #define VPLL_MRR 0x11
279 #define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
280 | (VPLL_SEL_PF_DN_SPREAD << 29) \
289 #define BIT_CAM_CLK_PIXELASYNCM1 18
290 #define BIT_CAM_CLK_PIXELASYNCM0 17
291 #define BIT_CAM_CLK_PPMUCAMIF 16
292 #define BIT_CAM_CLK_QEFIMC3 15
293 #define BIT_CAM_CLK_QEFIMC2 14
294 #define BIT_CAM_CLK_QEFIMC1 13
295 #define BIT_CAM_CLK_QEFIMC0 12
296 #define BIT_CAM_CLK_SMMUJPEG 11
297 #define BIT_CAM_CLK_SMMUFIMC3 10
298 #define BIT_CAM_CLK_SMMUFIMC2 9
299 #define BIT_CAM_CLK_SMMUFIMC1 8
300 #define BIT_CAM_CLK_SMMUFIMC0 7
301 #define BIT_CAM_CLK_JPEG 6
302 #define BIT_CAM_CLK_CSIS1 5
303 #define BIT_CAM_CLK_CSIS0 4
304 #define BIT_CAM_CLK_FIMC3 3
305 #define BIT_CAM_CLK_FIMC2 2
306 #define BIT_CAM_CLK_FIMC1 1
307 #define BIT_CAM_CLK_FIMC0 0
308 #define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
309 | (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
310 | (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
311 | (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
312 | (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
313 | (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
314 | (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
315 | (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
316 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
317 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
318 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
319 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
320 | (CLK_EN << BIT_CAM_CLK_JPEG)\
321 | (CLK_EN << BIT_CAM_CLK_CSIS1)\
322 | (CLK_EN << BIT_CAM_CLK_CSIS0)\
323 | (CLK_EN << BIT_CAM_CLK_FIMC3)\
324 | (CLK_EN << BIT_CAM_CLK_FIMC2)\
325 | (CLK_EN << BIT_CAM_CLK_FIMC1)\
326 | (CLK_EN << BIT_CAM_CLK_FIMC0))
327 #define CLK_GATE_IP_CAM_ALL_DIS ~CLK_GATE_IP_CAM_ALL_EN
329 #define BIT_VP_CLK_PPMUTV 5
330 #define BIT_VP_CLK_SMMUTV 4
331 #define BIT_VP_CLK_HDMI 3
332 #define BIT_VP_CLK_TVENC 2
333 #define BIT_VP_CLK_MIXER 1
334 #define BIT_VP_CLK_VP 0
335 #define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\
336 | (CLK_EN << BIT_VP_CLK_SMMUTV)\
337 | (CLK_EN << BIT_VP_CLK_HDMI)\
338 | (CLK_EN << BIT_VP_CLK_TVENC)\
339 | (CLK_EN << BIT_VP_CLK_MIXER)\
340 | (CLK_EN << BIT_VP_CLK_VP))
341 #define CLK_GATE_IP_VP_ALL_DIS ~CLK_GATE_IP_VP_ALL_EN
343 #define BIT_MFC_CLK_PPMUMFC_R 4
344 #define BIT_MFC_CLK_PPMUMFC_L 3
345 #define BIT_MFC_CLK_SMMUMFC_R 2
346 #define BIT_MFC_CLK_SMMUMFC_L 1
347 #define BIT_MFC_CLK_MFC 0
348 #define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
349 | (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
350 | (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
351 | (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
352 | (CLK_EN << BIT_MFC_CLK_MFC))
353 #define CLK_GATE_IP_MFC_ALL_DIS ~CLK_GATE_IP_MFC_ALL_EN
355 #define BIT_G3D_CLK_QEG3D 2
356 #define BIT_G3D_CLK_PPMUG3D 1
357 #define BIT_G3D_CLK_G3D 0
358 #define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\
359 | (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
360 | (CLK_EN << BIT_G3D_CLK_G3D))
361 #define CLK_GATE_IP_G3D_ALL_DIS ~CLK_GATE_IP_G3D_ALL_EN
363 #define BIT_IMAGE_CLK_PPMUIMAGE 9
364 #define BIT_IMAGE_CLK_QEMDMA 8
365 #define BIT_IMAGE_CLK_QEROTATOR 7
366 #define BIT_IMAGE_CLK_QEG2D 6
367 #define BIT_IMAGE_CLK_SMMUMDMA 5
368 #define BIT_IMAGE_CLK_SMMUROTATOR 4
369 #define BIT_IMAGE_CLK_SMMUG2D 3
370 #define BIT_IMAGE_CLK_MDMA 2
371 #define BIT_IMAGE_CLK_ROTATOR 1
372 #define BIT_IMAGE_CLK_G2D 0
373 #define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
374 | (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
375 | (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
376 | (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
377 | (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
378 | (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
379 | (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
380 | (CLK_EN << BIT_IMAGE_CLK_MDMA)\
381 | (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
382 | (CLK_EN << BIT_IMAGE_CLK_G2D))
383 #define CLK_GATE_IP_IMAGE_ALL_DIS ~CLK_GATE_IP_IMAGE_ALL_EN
385 #define BIT_LCD0_CLK_PPMULCD0 5
386 #define BIT_LCD0_CLK_SMMUFIMD0 4
387 #define BIT_LCD0_CLK_DSIM0 3
388 #define BIT_LCD0_CLK_MDNIE0 2
389 #define BIT_LCD0_CLK_MIE0 1
390 #define BIT_LCD0_CLK_FIMD0 0
391 #define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
392 | (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
393 | (CLK_EN << BIT_LCD0_CLK_DSIM0)\
394 | (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
395 | (CLK_EN << BIT_LCD0_CLK_MIE0)\
396 | (CLK_EN << BIT_LCD0_CLK_FIMD0))
397 #define CLK_GATE_IP_LCD0_ALL_DIS ~CLK_GATE_IP_LCD0_ALL_EN
399 #define BIT_LCD1_CLK_PPMULCD1 5
400 #define BIT_LCD1_CLK_SMMUFIMD1 4
401 #define BIT_LCD1_CLK_DSIM1 3
402 #define BIT_LCD1_CLK_MDNIE1 2
403 #define BIT_LCD1_CLK_MIE1 1
404 #define BIT_LCD1_CLK_FIMD1 0
405 #define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
406 | (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
407 | (CLK_EN << BIT_LCD1_CLK_DSIM1)\
408 | (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
409 | (CLK_EN << BIT_LCD1_CLK_MIE1)\
410 | (CLK_EN << BIT_LCD1_CLK_FIMD1))
411 #define CLK_GATE_IP_LCD1_ALL_DIS ~CLK_GATE_IP_LCD1_ALL_EN
413 #define BIT_FSYS_CLK_SMMUPCIE 18
414 #define BIT_FSYS_CLK_PPMUFILE 17
415 #define BIT_FSYS_CLK_NFCON 16
416 #define BIT_FSYS_CLK_ONENAND 15
417 #define BIT_FSYS_CLK_PCIE 14
418 #define BIT_FSYS_CLK_USBDEVICE 13
419 #define BIT_FSYS_CLK_USBHOST 12
420 #define BIT_FSYS_CLK_SROMC 11
421 #define BIT_FSYS_CLK_SATA 10
422 #define BIT_FSYS_CLK_SDMMC4 9
423 #define BIT_FSYS_CLK_SDMMC3 8
424 #define BIT_FSYS_CLK_SDMMC2 7
425 #define BIT_FSYS_CLK_SDMMC1 6
426 #define BIT_FSYS_CLK_SDMMC0 5
427 #define BIT_FSYS_CLK_TSI 4
428 #define BIT_FSYS_CLK_SATAPHY 3
429 #define BIT_FSYS_CLK_PCIEPHY 2
430 #define BIT_FSYS_CLK_PDMA1 1
431 #define BIT_FSYS_CLK_PDMA0 0
432 #define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
433 | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
434 | (CLK_EN << BIT_FSYS_CLK_NFCON)\
435 | (CLK_EN << BIT_FSYS_CLK_ONENAND)\
436 | (CLK_EN << BIT_FSYS_CLK_PCIE)\
437 | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
438 | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
439 | (CLK_EN << BIT_FSYS_CLK_SROMC)\
440 | (CLK_EN << BIT_FSYS_CLK_SATA)\
441 | (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
442 | (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
443 | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
444 | (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
445 | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
446 | (CLK_EN << BIT_FSYS_CLK_TSI)\
447 | (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
448 | (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
449 | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
450 | (CLK_EN << BIT_FSYS_CLK_PDMA0))
451 #define CLK_GATE_IP_FSYS_ALL_DIS ~CLK_GATE_IP_FSYS_ALL_EN
453 #define BIT_GPS_CLK_SMMUGPS 1
454 #define BIT_GPS_CLK_GPS 0
455 #define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
456 | (CLK_EN << BIT_GPS_CLK_GPS))
457 #define CLK_GATE_IP_GPS_ALL_DIS ~CLK_GATE_IP_GPS_ALL_EN
459 #define BIT_PERIL_CLK_MODEMIF 28
460 #define BIT_PERIL_CLK_AC97 27
461 #define BIT_PERIL_CLK_SPDIF 26
462 #define BIT_PERIL_CLK_SLIMBUS 25
463 #define BIT_PERIL_CLK_PWM 24
464 #define BIT_PERIL_CLK_PCM2 23
465 #define BIT_PERIL_CLK_PCM1 22
466 #define BIT_PERIL_CLK_I2S2 21
467 #define BIT_PERIL_CLK_I2S1 20
468 #define BIT_PERIL_CLK_RESERVED0 19
469 #define BIT_PERIL_CLK_SPI2 18
470 #define BIT_PERIL_CLK_SPI1 17
471 #define BIT_PERIL_CLK_SPI0 16
472 #define BIT_PERIL_CLK_TSADC 15
473 #define BIT_PERIL_CLK_I2CHDMI 14
474 #define BIT_PERIL_CLK_I2C7 13
475 #define BIT_PERIL_CLK_I2C6 12
476 #define BIT_PERIL_CLK_I2C5 11
477 #define BIT_PERIL_CLK_I2C4 10
478 #define BIT_PERIL_CLK_I2C3 9
479 #define BIT_PERIL_CLK_I2C2 8
480 #define BIT_PERIL_CLK_I2C1 7
481 #define BIT_PERIL_CLK_I2C0 6
482 #define BIT_PERIL_CLK_RESERVED1 5
483 #define BIT_PERIL_CLK_UART4 4
484 #define BIT_PERIL_CLK_UART3 3
485 #define BIT_PERIL_CLK_UART2 2
486 #define BIT_PERIL_CLK_UART1 1
487 #define BIT_PERIL_CLK_UART0 0
488 #define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
489 | (CLK_EN << BIT_PERIL_CLK_AC97)\
490 | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
491 | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
492 | (CLK_EN << BIT_PERIL_CLK_PWM)\
493 | (CLK_EN << BIT_PERIL_CLK_PCM2)\
494 | (CLK_EN << BIT_PERIL_CLK_PCM1)\
495 | (CLK_EN << BIT_PERIL_CLK_I2S2)\
496 | (CLK_EN << BIT_PERIL_CLK_I2S1)\
497 | (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
498 | (CLK_EN << BIT_PERIL_CLK_SPI2)\
499 | (CLK_EN << BIT_PERIL_CLK_SPI1)\
500 | (CLK_EN << BIT_PERIL_CLK_SPI0)\
501 | (CLK_EN << BIT_PERIL_CLK_TSADC)\
502 | (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
503 | (CLK_EN << BIT_PERIL_CLK_I2C7)\
504 | (CLK_EN << BIT_PERIL_CLK_I2C6)\
505 | (CLK_EN << BIT_PERIL_CLK_I2C5)\
506 | (CLK_EN << BIT_PERIL_CLK_I2C4)\
507 | (CLK_EN << BIT_PERIL_CLK_I2C3)\
508 | (CLK_EN << BIT_PERIL_CLK_I2C2)\
509 | (CLK_EN << BIT_PERIL_CLK_I2C1)\
510 | (CLK_EN << BIT_PERIL_CLK_I2C0)\
511 | (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
512 | (CLK_EN << BIT_PERIL_CLK_UART4)\
513 | (CLK_EN << BIT_PERIL_CLK_UART3)\
514 | (CLK_EN << BIT_PERIL_CLK_UART2)\
515 | (CLK_EN << BIT_PERIL_CLK_UART1)\
516 | (CLK_EN << BIT_PERIL_CLK_UART0))
517 #define CLK_GATE_IP_PERIL_ALL_DIS ~CLK_GATE_IP_PERIL_ALL_EN
519 #define BIT_PERIR_CLK_TMU_APBIF 17
520 #define BIT_PERIR_CLK_KEYIF 16
521 #define BIT_PERIR_CLK_RTC 15
522 #define BIT_PERIR_CLK_WDT 14
523 #define BIT_PERIR_CLK_MCT 13
524 #define BIT_PERIR_CLK_SECKEY 12
525 #define BIT_PERIR_CLK_HDMI_CEC 11
526 #define BIT_PERIR_CLK_TZPC5 10
527 #define BIT_PERIR_CLK_TZPC4 9
528 #define BIT_PERIR_CLK_TZPC3 8
529 #define BIT_PERIR_CLK_TZPC2 7
530 #define BIT_PERIR_CLK_TZPC1 6
531 #define BIT_PERIR_CLK_TZPC0 5
532 #define BIT_PERIR_CLK_CMU_DMCPART 4
533 #define BIT_PERIR_CLK_RESERVED 3
534 #define BIT_PERIR_CLK_CMU_APBIF 2
535 #define BIT_PERIR_CLK_SYSREG 1
536 #define BIT_PERIR_CLK_CHIP_ID 0
537 #define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
538 | (CLK_EN << BIT_PERIR_CLK_KEYIF)\
539 | (CLK_EN << BIT_PERIR_CLK_RTC)\
540 | (CLK_EN << BIT_PERIR_CLK_WDT)\
541 | (CLK_EN << BIT_PERIR_CLK_MCT)\
542 | (CLK_EN << BIT_PERIR_CLK_SECKEY)\
543 | (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
544 | (CLK_EN << BIT_PERIR_CLK_TZPC5)\
545 | (CLK_EN << BIT_PERIR_CLK_TZPC4)\
546 | (CLK_EN << BIT_PERIR_CLK_TZPC3)\
547 | (CLK_EN << BIT_PERIR_CLK_TZPC2)\
548 | (CLK_EN << BIT_PERIR_CLK_TZPC1)\
549 | (CLK_EN << BIT_PERIR_CLK_TZPC0)\
550 | (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
551 | (CLK_EN << BIT_PERIR_CLK_RESERVED)\
552 | (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
553 | (CLK_EN << BIT_PERIR_CLK_SYSREG)\
554 | (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
555 #define CLK_GATE_IP_PERIR_ALL_DIS ~CLK_GATE_IP_PERIR_ALL_EN
557 #define BIT_BLOCK_CLK_GPS 7
558 #define BIT_BLOCK_CLK_RESERVED 6
559 #define BIT_BLOCK_CLK_LCD1 5
560 #define BIT_BLOCK_CLK_LCD0 4
561 #define BIT_BLOCK_CLK_G3D 3
562 #define BIT_BLOCK_CLK_MFC 2
563 #define BIT_BLOCK_CLK_TV 1
564 #define BIT_BLOCK_CLK_CAM 0
565 #define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\
566 | (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
567 | (CLK_EN << BIT_BLOCK_CLK_LCD1)\
568 | (CLK_EN << BIT_BLOCK_CLK_LCD0)\
569 | (CLK_EN << BIT_BLOCK_CLK_G3D)\
570 | (CLK_EN << BIT_BLOCK_CLK_MFC)\
571 | (CLK_EN << BIT_BLOCK_CLK_TV)\
572 | (CLK_EN << BIT_BLOCK_CLK_CAM))
573 #define CLK_GATE_BLOCK_ALL_DIS ~CLK_GATE_BLOCK_ALL_EN
576 * GATE CAM : All block
577 * GATE VP : All block
578 * GATE MFC : All block
579 * GATE G3D : All block
580 * GATE IMAGE : All block
581 * GATE LCD0 : All block
582 * GATE LCD1 : All block
583 * GATE FSYS : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE
584 * GATE GPS : All block
585 * GATE PERI Left : All Enable, Block - SLIMBUS, SPDIF, AC97
586 * GATE PERI Right : All Enable, Block - KEYIF
587 * GATE Block : All block
589 #define CLK_GATE_IP_CAM_VAL CLK_GATE_IP_CAM_ALL_DIS
590 #define CLK_GATE_IP_VP_VAL CLK_GATE_IP_VP_ALL_DIS
591 #define CLK_GATE_IP_MFC_VAL CLK_GATE_IP_MFC_ALL_DIS
592 #define CLK_GATE_IP_G3D_VAL CLK_GATE_IP_G3D_ALL_DIS
593 #define CLK_GATE_IP_IMAGE_VAL CLK_GATE_IP_IMAGE_ALL_DIS
594 #define CLK_GATE_IP_LCD0_VAL CLK_GATE_IP_LCD0_ALL_DIS
595 #define CLK_GATE_IP_LCD1_VAL CLK_GATE_IP_LCD1_ALL_DIS
596 #define CLK_GATE_IP_FSYS_VAL (CLK_GATE_IP_FSYS_ALL_DIS \
597 | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
598 | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
599 | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
600 | (CLK_EN << BIT_FSYS_CLK_SROMC)\
601 | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
602 | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
603 | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
604 | (CLK_EN << BIT_FSYS_CLK_PDMA0))
605 #define CLK_GATE_IP_GPS_VAL CLK_GATE_IP_GPS_ALL_DIS
606 #define CLK_GATE_IP_PERIL_VAL (CLK_GATE_IP_PERIL_ALL_DIS \
607 | ~((CLK_EN << BIT_PERIL_CLK_AC97)\
608 | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
609 | (CLK_EN << BIT_PERIL_CLK_I2C2)\
610 | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
611 #define CLK_GATE_IP_PERIR_VAL (CLK_GATE_IP_PERIR_ALL_DIS \
612 | ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))
613 #define CLK_GATE_BLOCK_VAL CLK_GATE_BLOCK_ALL_DIS
615 /* PS_HOLD: Data Hight, Output En */
618 #define EXYNOS4_PS_HOLD_CON_VAL (0x1 << BIT_DAT | 0x1 << BIT_EN)