board/sbc8560/init.S

   1 /*
   2 * Copyright (C) 2002,2003, Motorola Inc.
   3 * Xianghua Xiao <X.Xiao@motorola.com>
   4 *
   5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
   6 * Added support for Wind River SBC8560 board
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.   See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27 #include <ppc_asm.tmpl>
  28 #include <ppc_defs.h>
  29 #include <asm/cache.h>
  30 #include <asm/mmu.h>
  31 #include <config.h>
  32 #include <mpc85xx.h>
  33
  34 #define entry_start \
  35         mflr    r1      ;       \
  36         bl      0f      ;
  37
  38 #define entry_end \
  39 0:      mflr    r0      ;       \
  40         mtlr    r1      ;       \
  41         blr             ;
  42
  43 /* TLB1 entries configuration: */
  44
  45         .section        .bootpg, "ax"
  46         .globl          tlb1_entry
  47
  48 tlb1_entry:
  49         entry_start
  50
  51         .long 0x08      /* the following data table uses a few of 16 TLB entries */
  52
  53 /* TLB for CCSRBAR (IMMR) */
  54
  55         .long FSL_BOOKE_MAS0(1,1,0)
  56         .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
  57         .long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G))
  58         .long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
  59
  60 /* TLB for Local Bus stuff, just map the whole 512M */
  61 /* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
  62
  63         .long FSL_BOOKE_MAS0(1,2,0)
  64         .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
  65         .long FSL_BOOKE_MAS2(0xe0000000,(MAS2_I|MAS2_G))
  66         .long FSL_BOOKE_MAS3(0xe0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
  67
  68         .long FSL_BOOKE_MAS0(1,3,0)
  69         .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
  70         .long FSL_BOOKE_MAS2(0xf0000000,(MAS2_I|MAS2_G))
  71         .long FSL_BOOKE_MAS3(0xf0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
  72
  73 #if !defined(CONFIG_SPD_EEPROM)
  74         .long FSL_BOOKE_MAS0(1,4,0)
  75         .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
  76         .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0)
  77         .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
  78
  79         .long FSL_BOOKE_MAS0(1,5,0)
  80         .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
  81         .long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000,0)
  82         .long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
  83 #else
  84         .long FSL_BOOKE_MAS0(1,4,0)
  85         .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
  86         .long FSL_BOOKE_MAS2(0,0)
  87         .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
  88
  89         .long FSL_BOOKE_MAS0(1,5,0)
  90         .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
  91         .long FSL_BOOKE_MAS2(0,0)
  92         .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
  93 #endif
  94
  95         .long FSL_BOOKE_MAS0(1,6,0)
  96         .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
  97 #ifdef CONFIG_L2_INIT_RAM
  98         .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0)
  99 #else
 100         .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0)
 101 #endif
 102         .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 103
 104         .long FSL_BOOKE_MAS0(1,7,0)
 105         .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
 106         .long FSL_BOOKE_MAS2(CFG_PCI_MEM_PHYS,(MAS2_I|MAS2_G))
 107         .long FSL_BOOKE_MAS3(CFG_PCI_MEM_PHYS,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 108
 109 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
 110         .long FSL_BOOKE_MAS0(1,15,0)
 111         .long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
 112         .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G))
 113         .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 114 #else
 115         .long FSL_BOOKE_MAS0(1,15,0)
 116         .long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
 117         .long FSL_BOOKE_MAS2(0,0)
 118         .long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 119 #endif
 120         entry_end