2 * Board functions for TI AM335X based pxm2 board
3 * (C) Copyright 2013 Siemens Schweiz AG
4 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * u-boot:/board/ti/am335x/board.c
9 * Board functions for TI AM335X based boards
11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
13 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/omap.h>
22 #include <asm/arch/ddr_defs.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/sys_proto.h>
27 #include "../../../drivers/video/da8xx-fb.h"
36 #include "../common/factoryset.h"
39 #include <bmp_layout.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 #ifdef CONFIG_SPL_BUILD
44 static void board_init_ddr(void)
46 struct emif_regs pxm2_ddr3_emif_reg_data = {
47 .sdram_config = 0x41805332,
48 .sdram_tim1 = 0x666b3c9,
49 .sdram_tim2 = 0x243631ca,
51 .emif_ddr_phy_ctlr_1 = 0x100005,
56 struct ddr_data pxm2_ddr3_data = {
57 .datardsratio0 = 0x81204812,
59 .datafwsratio0 = 0x8020080,
60 .datawrsratio0 = 0x4010040,
61 .datauserank0delay = 1,
62 .datadldiff0 = PHY_DLL_LOCK_DIFF,
65 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
77 config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
78 &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
82 * voltage switching for MPU frequency switching.
83 * @module = mpu - 0, core - 1
84 * @vddx_op_vol_sel = vdd voltage to set
90 int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
93 unsigned int reg_offset;
96 reg_offset = PMIC_VDD1_OP_REG;
98 reg_offset = PMIC_VDD2_OP_REG;
101 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
104 buf[0] &= ~PMIC_OP_REG_CMD_MASK;
106 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
109 /* Configure VDDx OP Voltage */
110 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
113 buf[0] &= ~PMIC_OP_REG_SEL_MASK;
114 buf[0] |= vddx_op_vol_sel;
116 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
119 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
122 if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
128 #define OSC (V_OSCK/1000000)
130 const struct dpll_params dpll_mpu_pxm2 = {
131 720, OSC-1, 1, -1, -1, -1, -1};
133 void spl_siemens_board_init(void)
137 * pxm2 PMIC code. All boards currently want an MPU voltage
138 * of 1.2625V and CORE voltage of 1.1375V to operate at
141 if (i2c_probe(PMIC_CTRL_I2C_ADDR))
144 /* VDD1/2 voltage selection register access by control i/f */
145 if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
148 buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
150 if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
153 /* Frequency switching for OPP 120 */
154 if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
155 voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
156 printf("voltage update failed\n");
159 #endif /* if def CONFIG_SPL_BUILD */
161 int read_eeprom(void)
163 /* nothing ToDo here for this board */
168 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
169 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
170 static void cpsw_control(int enabled)
172 /* VTP can be added here */
177 static struct cpsw_slave_data cpsw_slaves[] = {
179 .slave_reg_ofs = 0x208,
180 .sliver_reg_ofs = 0xd80,
182 .phy_if = PHY_INTERFACE_MODE_RMII,
185 .slave_reg_ofs = 0x308,
186 .sliver_reg_ofs = 0xdc0,
188 .phy_if = PHY_INTERFACE_MODE_RMII,
192 static struct cpsw_platform_data cpsw_data = {
193 .mdio_base = CPSW_MDIO_BASE,
194 .cpsw_base = CPSW_BASE,
197 .cpdma_reg_ofs = 0x800,
199 .slave_data = cpsw_slaves,
200 .ale_reg_ofs = 0xd00,
202 .host_port_reg_ofs = 0x108,
203 .hw_stats_reg_ofs = 0x900,
204 .bd_ram_ofs = 0x2000,
205 .mac_control = (1 << 5),
206 .control = cpsw_control,
208 .version = CPSW_CTRL_VERSION_2,
210 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
212 #if defined(CONFIG_DRIVER_TI_CPSW) || \
213 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
214 int board_eth_init(bd_t *bis)
217 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
218 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
219 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
220 #ifdef CONFIG_FACTORYSET
222 if (!is_valid_ether_addr(factory_dat.mac))
223 printf("Error: no valid mac address\n");
225 eth_setenv_enetaddr("ethaddr", factory_dat.mac);
226 #endif /* #ifdef CONFIG_FACTORYSET */
228 /* Set rgmii mode and enable rmii clock to be sourced from chip */
229 writel(RGMII_MODE_ENABLE , &cdev->miisel);
231 rv = cpsw_register(&cpsw_data);
233 printf("Error %d registering CPSW switch\n", rv);
239 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
241 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
242 static struct da8xx_panel lcd_panels[] = {
243 /* AUO G156XW01 V1 */
245 .name = "AUO_G156XW01_V1",
257 /* AUO B101EVN06 V0 */
259 .name = "AUO_B101EVN06_V0",
272 * Settings from factoryset
276 .name = "factoryset",
290 static const struct display_panel disp_panel = {
297 static const struct lcd_ctrl_config lcd_cfg = {
307 .invert_line_clock = 1,
308 .invert_frm_clock = 1,
314 static int set_gpio(int gpio, int state)
316 gpio_request(gpio, "temp");
317 gpio_direction_output(gpio, state);
318 gpio_set_value(gpio, state);
323 static int enable_backlight(void)
325 set_gpio(BOARD_LCD_POWER, 1);
326 set_gpio(BOARD_BACK_LIGHT, 1);
327 set_gpio(BOARD_TOUCH_POWER, 1);
331 static int enable_pwm(void)
333 struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
334 struct pwmss_ecap_regs *ecap;
335 int ticks = PWM_TICKS;
338 ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
340 setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
341 /* TimeStam Counter register */
342 writel(0xdb9, &ecap->tsctr);
344 writel(ticks - 1, &ecap->cap3);
345 writel(ticks - 1, &ecap->cap1);
346 setbits_le16(&ecap->ecctl2,
347 (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
349 writel(duty, &ecap->cap2);
350 writel(duty, &ecap->cap4);
352 setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
356 static struct dpll_regs dpll_lcd_regs = {
357 .cm_clkmode_dpll = CM_WKUP + 0x98,
358 .cm_idlest_dpll = CM_WKUP + 0x48,
359 .cm_clksel_dpll = CM_WKUP + 0x54,
362 /* no console on this board */
363 int board_cfb_skip(void)
368 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
369 #define PLL_GET_N(v) (v & 0x7f)
371 static int get_clk(struct dpll_regs *dpll_regs)
377 val = readl(dpll_regs->cm_clksel_dpll);
380 f = (m * V_OSCK) / n;
387 return get_clk(&dpll_lcd_regs);
390 static int conf_disp_pll(int m, int n)
392 struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
393 struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
394 struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
396 u32 *const clk_domains[] = {
400 u32 *const clk_modules_explicit_en[] = {
402 &cmper->lcdcclkstctrl,
403 &cmper->epwmss0clkctrl,
406 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
407 writel(0x0, &cmdpll->clklcdcpixelclk);
409 do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
414 static int board_video_init(void)
417 conf_disp_pll(25, 2);
418 if (factory_dat.pxm50)
419 da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
421 da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
429 #include "../common/board.c"