2 * (C) Copyright 2001, 2002
3 * Dave Ellis, SIXNET, dge@sixnetio.com.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * and other contributors to U-Boot.
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <jffs2/jffs2.h>
15 #include <net.h> /* for eth_init() */
18 #ifdef CONFIG_SHOW_BOOT_PROGRESS
19 # include <status_led.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define ORMASK(size) ((-size) & OR_AM_MSK)
26 static long ram_size(ulong *, long);
28 /* ------------------------------------------------------------------------- */
30 #ifdef CONFIG_SHOW_BOOT_PROGRESS
31 void show_boot_progress (int status)
33 #if defined(CONFIG_STATUS_LED)
34 # if defined(STATUS_LED_BOOT)
35 if (status == BOOTSTAGE_ID_RUN_OS) {
36 /* ready to transfer to kernel, make sure LED is proper state */
37 status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
39 # endif /* STATUS_LED_BOOT */
40 #endif /* CONFIG_STATUS_LED */
44 /* ------------------------------------------------------------------------- */
47 * Check Board Identity:
48 * returns 0 if recognized, -1 if unknown
53 puts ("Board: SIXNET SXNI855T\n");
57 /* ------------------------------------------------------------------------- */
59 #if defined(CONFIG_CMD_PCMCIA)
60 #error "SXNI855T has no PCMCIA port"
63 /* ------------------------------------------------------------------------- */
65 #define _not_used_ 0xffffffff
67 /* UPMB table for dual UART. */
69 /* this table is for 50MHz operation, it should work at all lower speeds */
70 const uint duart_table[] =
72 /* single read. (offset 0 in upm RAM) */
73 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
74 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
76 /* burst read. (offset 8 in upm RAM) */
77 _not_used_, _not_used_, _not_used_, _not_used_,
78 _not_used_, _not_used_, _not_used_, _not_used_,
79 _not_used_, _not_used_, _not_used_, _not_used_,
80 _not_used_, _not_used_, _not_used_, _not_used_,
82 /* single write. (offset 18 in upm RAM) */
83 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
84 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
86 /* burst write. (offset 20 in upm RAM) */
87 _not_used_, _not_used_, _not_used_, _not_used_,
88 _not_used_, _not_used_, _not_used_, _not_used_,
89 _not_used_, _not_used_, _not_used_, _not_used_,
90 _not_used_, _not_used_, _not_used_, _not_used_,
92 /* refresh. (offset 30 in upm RAM) */
93 _not_used_, _not_used_, _not_used_, _not_used_,
94 _not_used_, _not_used_, _not_used_, _not_used_,
95 _not_used_, _not_used_, _not_used_, _not_used_,
97 /* exception. (offset 3c in upm RAM) */
98 _not_used_, _not_used_, _not_used_, _not_used_,
101 /* Load FPGA very early in boot sequence, since it must be
102 * loaded before the 16C2550 serial channels can be used as
105 * Note: Much of the configuration is not complete. The
106 * stack is in DPRAM since SDRAM has not been initialized,
107 * so the stack must be kept small. Global variables
108 * are still in FLASH, so they cannot be written.
109 * Only the FLASH, DPRAM, immap and FPGA can be addressed,
110 * the other chip selects may not have been initialized.
111 * The clocks have been initialized, so udelay() can be
114 #define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
115 #define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
116 #define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
117 #define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */
119 int board_postclk_init (void)
122 /* the data to load to the XCSxxXL FPGA */
123 static const unsigned char fpgadata[] = {
124 # include "fpgadata.c"
127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
128 volatile memctl8xx_t *memctl = &immap->im_memctl;
129 #define porta (immap->im_ioport.iop_padat)
130 const unsigned char* pdata;
132 /* /INITFPGA and DONEFPGA signals are inputs */
133 immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
135 /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
136 porta &= ~FPGA_PROGRAM_L;
138 /* Set FPGA as an output */
139 immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
141 /* delay a little to make sure FPGA sees it, really
142 * only need less than a microsecond.
146 /* unassert /PROGRAM */
147 porta |= FPGA_PROGRAM_L;
149 /* delay while FPGA does last erase, indicated by
150 * /INITFPGA going high. This should happen within a
153 /* ### FIXME - a timeout check would be good, maybe flash
154 * the status LED to indicate the error?
156 while ((porta & FPGA_INIT_L) == 0)
159 /* write program data to FPGA at the programming address
160 * so extra /CS1 strobes at end of configuration don't actually
161 * write to any registers.
163 fpga = 0xff; /* first write is ignored */
164 fpga = 0xff; /* fill byte */
165 fpga = 0xff; /* fill byte */
166 fpga = 0x4f; /* preamble code */
167 fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
168 fpga = 0x4b; /* field check code */
171 /* while no error write out each of the 28 byte frames */
172 while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
173 && pdata < fpgadata + sizeof(fpgadata)) {
175 fpga = 0x4f; /* preamble code */
177 /* 21 bytes of data in a frame */
178 fpga = *(pdata++); fpga = *(pdata++);
179 fpga = *(pdata++); fpga = *(pdata++);
180 fpga = *(pdata++); fpga = *(pdata++);
181 fpga = *(pdata++); fpga = *(pdata++);
182 fpga = *(pdata++); fpga = *(pdata++);
183 fpga = *(pdata++); fpga = *(pdata++);
184 fpga = *(pdata++); fpga = *(pdata++);
185 fpga = *(pdata++); fpga = *(pdata++);
186 fpga = *(pdata++); fpga = *(pdata++);
187 fpga = *(pdata++); fpga = *(pdata++);
190 fpga = 0x4b; /* field check code */
191 fpga = 0xff; /* extended write cycle */
192 fpga = 0x4b; /* extended write cycle
193 * (actually 0x4b from bitgen.exe)
195 fpga = 0xff; /* extended write cycle */
196 fpga = 0xff; /* extended write cycle */
197 fpga = 0xff; /* extended write cycle */
200 fpga = 0xff; /* startup byte */
201 fpga = 0xff; /* startup byte */
202 fpga = 0xff; /* startup byte */
203 fpga = 0xff; /* startup byte */
205 #if 0 /* ### FIXME */
206 /* If didn't load all the data or FPGA_DONE is low the load failed.
207 * Maybe someday stop here and flash the status LED? The console
208 * is not configured, so can't print an error message. Can't write
209 * global variables to set a flag (except gd?).
210 * For now it must work.
214 /* Now that the FPGA is loaded, set up the Dual UART chip
215 * selects. Must be done here since it may be used as the console.
217 upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
219 memctl->memc_mbmr = DUART_MBMR;
220 memctl->memc_or5 = DUART_OR_VALUE;
221 memctl->memc_br5 = DUART_BR5_VALUE;
222 memctl->memc_or6 = DUART_OR_VALUE;
223 memctl->memc_br6 = DUART_BR6_VALUE;
228 /* ------------------------------------------------------------------------- */
230 /* base address for SRAM, assume 32-bit port, valid */
231 #define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
233 /* up to 64MB - will be adjusted for actual size */
234 #define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \
235 | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
237 * Miscellaneous platform dependent initializations after running in RAM.
240 int misc_init_r (void)
242 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
243 volatile memctl8xx_t *memctl = &immap->im_memctl;
247 memctl->memc_or2 = NVRAM_OR_PRELIM;
248 memctl->memc_br2 = NVRAM_BR_VALUE;
250 /* Is there any SRAM? Is it 16 or 32 bits wide? */
252 /* First look for 32-bit SRAM */
253 bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
255 if (bd->bi_sramsize == 0) {
256 /* no 32-bit SRAM, but there could be 16-bit SRAM since
257 * it would report size 0 when configured for 32-bit bus.
258 * Try again with a 16-bit bus.
260 memctl->memc_br2 |= BR_PS_16;
261 bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
264 if (bd->bi_sramsize == 0) {
265 memctl->memc_br2 = 0; /* disable select since nothing there */
268 /* adjust or2 for actual size of SRAM */
269 memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
270 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
271 printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
275 /* set standard MPC8xx clock so kernel will see the time
276 * even if it doesn't have a DS1306 clock driver.
277 * This helps with experimenting with standard kernels.
283 rtc_get(&tmp); /* get time from DS1306 RTC */
285 /* convert to seconds since 1970 */
286 tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
287 tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
289 immap->im_sitk.sitk_rtck = KAPWR_KEY;
290 immap->im_sit.sit_rtc = tim;
293 /* set up ethernet address for SCC ethernet. If eth1addr
294 * is present it gets a unique address, otherwise it
295 * shares the FEC address.
297 if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
298 eth_getenv_enetaddr("ethaddr", enetaddr);
299 eth_setenv_enetaddr("eth1addr", enetaddr);
305 #if defined(CONFIG_CMD_NAND)
308 unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
310 printf ("%4lu MB\n", totlen >> 20);
314 /* ------------------------------------------------------------------------- */
317 * Check memory range for valid RAM. A simple memory test determines
318 * the actually available RAM size between addresses `base' and
321 * The memory size MUST be a power of 2 for this to work.
323 * The only memory modified is 8 bytes at offset 0. This is important
324 * since for the SRAM this location is reserved for autosizing, so if
325 * it is modified and the board is reset before ram_size() completes
326 * no damage is done. Normally even the memory at 0 is preserved. The
327 * higher SRAM addresses may contain battery backed RAM disk data which
328 * must never be corrupted.
331 static long ram_size(ulong *base, long maxsize)
333 volatile long *test_addr;
334 volatile ulong *base_addr = base;
335 ulong ofs; /* byte offset from base_addr */
336 ulong save; /* to make test non-destructive */
337 ulong save2; /* to make test non-destructive */
338 long ramsize = -1; /* size not determined yet */
340 save = *base_addr; /* save value at 0 so can restore */
341 save2 = *(base_addr+1); /* save value at 4 so can restore */
343 /* is any SRAM present? */
344 *base_addr = 0x5555aaaa;
346 /* It is important to drive the data bus with different data so
347 * it doesn't remember the value and look like RAM that isn't there.
349 *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */
351 if (*base_addr != 0x5555aaaa)
352 ramsize = 0; /* no RAM present, or defective */
354 *base_addr = 0xaaaa5555;
355 *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
356 if (*base_addr != 0xaaaa5555)
357 ramsize = 0; /* no RAM present, or defective */
360 /* now size it if any is present */
361 for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
362 test_addr = (long*)((long)base_addr + ofs); /* location to test */
364 *base_addr = ~*test_addr;
365 if (*base_addr == *test_addr)
366 ramsize = ofs; /* wrapped back to 0, so this is the size */
369 *base_addr = save; /* restore value at 0 */
370 *(base_addr+1) = save2; /* restore value at 4 */
374 /* ------------------------------------------------------------------------- */
375 /* sdram table based on the FADS manual */
376 /* for chip MB811171622A-100 */
378 /* this table is for 50MHz operation, it should work at all lower speeds */
380 const uint sdram_table[] =
382 /* single read. (offset 0 in upm RAM) */
383 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
386 /* precharge and Mode Register Set initialization (offset 5).
387 * This is also entered at offset 6 to do Mode Register Set
388 * without the precharge.
390 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
392 /* burst read. (offset 8 in upm RAM) */
393 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
394 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
395 _not_used_, _not_used_, _not_used_, _not_used_,
396 _not_used_, _not_used_, _not_used_, _not_used_,
398 /* single write. (offset 18 in upm RAM) */
399 /* FADS had 0x1f27fc04, ...
400 * but most other boards have 0x1f07fc04, which
401 * sets GPL0 from A11MPC to 0 1/4 clock earlier,
402 * like the single read.
403 * This seems better so I am going with the change.
405 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
406 _not_used_, _not_used_, _not_used_, _not_used_,
408 /* burst write. (offset 20 in upm RAM) */
409 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
410 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
411 _not_used_, _not_used_, _not_used_, _not_used_,
412 _not_used_, _not_used_, _not_used_, _not_used_,
414 /* refresh. (offset 30 in upm RAM) */
415 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
416 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
417 _not_used_, _not_used_, _not_used_, _not_used_,
419 /* exception. (offset 3c in upm RAM) */
420 0x7ffffc07, _not_used_, _not_used_, _not_used_ };
422 /* ------------------------------------------------------------------------- */
424 #define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */
426 /* precharge and set Mode Register */
427 #define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
428 MCR_MB_CS3 | /* chip select */ \
429 MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */
431 /* set Mode Register, no precharge */
432 #define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
433 MCR_MB_CS3 | /* chip select */ \
434 MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */
436 /* runs refresh loop twice so get 8 refresh cycles */
437 #define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
438 MCR_MB_CS3 | /* chip select */ \
439 MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
441 /* MAMR values work in either mamr or mbmr */
442 #define SDRAM_MAMR_BASE /* refresh at 50MHz */ \
443 ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
444 | MAMR_DSA_1_CYCL /* 1 cycle disable */ \
445 | MAMR_RLFA_1X /* Read loop 1 time */ \
446 | MAMR_WLFA_1X /* Write loop 1 time */ \
447 | MAMR_TLFA_4X) /* Timer loop 4 times */
449 #define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \
450 | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
451 | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */
454 #define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \
455 | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \
456 | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */
458 /* base address 0, 32-bit port, SDRAM UPM, valid */
459 #define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
461 /* up to 256MB, SAM, G5LS - will be adjusted for actual size */
462 #define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
464 /* This is the Mode Select Register value for the SDRAM.
466 * Burst Type: sequential
468 * Write Burst Length: burst
470 #define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */
472 /* ------------------------------------------------------------------------- */
474 phys_size_t initdram(int board_type)
476 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
477 volatile memctl8xx_t *memctl = &immap->im_memctl;
479 uint size_sdram9 = 0;
480 uint base = 0; /* SDRAM must start at 0 */
483 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
485 /* Configure the refresh (mostly). This needs to be
486 * based upon processor clock speed and optimized to provide
487 * the highest level of performance.
489 * Preliminary prescaler for refresh.
490 * This value is selected for four cycles in 31.2 us,
491 * which gives 8192 cycles in 64 milliseconds.
492 * This may be too fast, but works for any memory.
493 * It is adjusted to 4096 cycles in 64 milliseconds if
494 * possible once we know what memory we have.
496 * We have to be careful changing UPM registers after we
497 * ask it to run these commands.
499 * PTA - periodic timer period for our design is
501 * --------------- = 195
505 * 31.2us refresh interval
510 memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
511 memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
513 /* The SDRAM Mode Register value is shifted left 2 bits since
514 * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
516 memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */
517 udelay(200); /* SDRAM needs 200uS before set it up */
519 /* Now run the precharge/nop/mrs commands. */
520 memctl->memc_mcr = SDRAM_MCR_PRE;
523 /* Run 8 refresh cycles (2 sets of 4) */
524 memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */
527 /* some brands want Mode Register set after the refresh
528 * cycles. This shouldn't hurt anything for the brands
529 * that were happy with the first time we set it.
531 memctl->memc_mcr = SDRAM_MCR_MRS;
534 memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */
535 memctl->memc_or3 = SDRAM_OR_PRELIM;
536 memctl->memc_br3 = SDRAM_BR_VALUE + base;
538 /* Some brands need at least 10 DRAM accesses to stabilize.
539 * It wont hurt the brands that don't.
541 for (i=0; i<10; ++i) {
542 volatile ulong *addr = (volatile ulong *)base;
549 /* Check SDRAM memory Size in 8 column mode.
550 * For a 9 column memory we will get half the actual size.
552 size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
554 /* Check SDRAM memory Size in 9 column mode.
555 * For an 8 column memory we will see at most 4 megabytes.
557 memctl->memc_mamr = SDRAM_MAMR_9COL;
558 size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
560 if (size_sdram < size_sdram9) /* leave configuration at 9 columns */
561 size_sdram = size_sdram9;
562 else /* go back to 8 columns */
563 memctl->memc_mamr = SDRAM_MAMR_8COL;
565 /* adjust or3 for actual size of SDRAM
567 memctl->memc_or3 |= ORMASK(size_sdram);
569 /* Adjust refresh rate depending on SDRAM type.
570 * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
571 * it at the current (fast) rate.
572 * For 16, 64 and 128 MBit half the rate will do.
574 if (size_sdram <= 32 * 1024 * 1024)
575 memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */