6 * Simple Network Magic Corporation, dnevil@snmc.com
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/u-boot.h>
19 /* ------------------------------------------------------------------------- */
21 static long int dram_size (long int, long int *, long int);
23 /* ------------------------------------------------------------------------- */
25 const uint sdram_table[] =
28 * Single Read. (Offset 0 in UPMA RAM)
30 0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04,
31 0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
33 * Burst Read. (Offset 8 in UPMA RAM)
35 0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
36 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
37 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
38 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
40 * Single Write. (Offset 18 in UPMA RAM)
42 0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07,
43 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
45 * Burst Write. (Offset 20 in UPMA RAM)
47 0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
48 0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04,
49 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
50 0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
52 * Refresh (Offset 30 in UPMA RAM)
54 0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04,
55 0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04,
56 0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04,
58 * Exception. (Offset 3c in UPMA RAM)
60 0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37
63 /* ------------------------------------------------------------------------- */
67 * Check Board Identity:
69 * Test ID string (QS850, QS823, ...)
73 #if defined(CONFIG_QS850)
74 #define BOARD_IDENTITY "QS850"
75 #elif defined(CONFIG_QS823)
76 #define BOARD_IDENTITY "QS823"
78 #define BOARD_IDENTITY "QS???"
87 i = getenv_f("serial#", buf, sizeof(buf));
88 s = (i>0) ? buf : NULL;
90 if (!s || strncmp(s, BOARD_IDENTITY, 5)) {
91 puts ("### No HW ID - assuming " BOARD_IDENTITY);
107 /* ------------------------------------------------------------------------- */
108 /* SDRAM Mode Register Definitions */
110 /* Set SDRAM Burst Length to 4 (010) */
111 /* See Motorola MPC850 User Manual, Page 13-14 */
112 #define SDRAM_BURST_LENGTH (2)
114 /* Set Wrap Type to Sequential (0) */
115 /* See Motorola MPC850 User Manual, Page 13-14 */
116 #define SDRAM_WRAP_TYPE (0 << 3)
118 /* Set /CAS Latentcy to 2 clocks */
119 #define SDRAM_CAS_LATENTCY (2 << 4)
121 /* The Mode Register value must be shifted left by 2, since it is */
122 /* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */
123 #define SDRAM_MODE_REG ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2)
125 #define UPMA_RUN(loops,index) (0x80002000 + (loops<<8) + index)
127 /* Please note a value of zero = 16 loops */
128 #define REFRESH_INIT_LOOPS (0)
131 phys_size_t initdram (int board_type)
133 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
134 volatile memctl8xx_t *memctl = &immap->im_memctl;
137 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
140 * Prescaler for refresh
142 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
145 * Map controller bank 1 to the SDRAM address
147 memctl->memc_or1 = CONFIG_SYS_OR1;
148 memctl->memc_br1 = CONFIG_SYS_BR1;
151 /* perform SDRAM initialization sequence */
152 memctl->memc_mamr = CONFIG_SYS_16M_MAMR;
155 /* Program the SDRAM's Mode Register */
156 memctl->memc_mar = SDRAM_MODE_REG;
158 /* Run the Prechard Pattern at 0x3C */
159 memctl->memc_mcr = UPMA_RUN(1,0x3c);
162 /* Run the Refresh program residing at MAD index 0x30 */
163 /* This contains the CBR Refresh command with a loop */
164 /* The SDRAM must be refreshed at least 2 times */
165 /* Please note a value of zero = 16 loops */
166 memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30);
169 /* Run the Exception program residing at MAD index 0x3E */
170 /* This contains the Write Mode Register command */
171 /* The Write Mode Register command uses the value written to MAR */
172 memctl->memc_mcr = UPMA_RUN(1,0x3e);
177 * Check for 32M SDRAM Memory Size
179 size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE,
180 (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
184 * Check for 16M SDRAM Memory Size
186 if (size != SDRAM_32M_MAX_SIZE) {
187 size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE,
188 (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
196 /* ------------------------------------------------------------------------- */
199 * Check memory range for valid RAM. A simple memory test determines
200 * the actually available RAM size between addresses `base' and
201 * `base + maxsize'. Some (not all) hardware errors are detected:
202 * - short between address lines
203 * - short between data lines
206 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
208 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
209 volatile memctl8xx_t *memctl = &immap->im_memctl;
211 memctl->memc_mamr = mamr_value;
213 return (get_ram_size(base, maxsize));