2 * K2HK EVM : Board initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <fdt_support.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/clock.h>
18 #include <asm/mach-types.h>
19 #include <asm/arch/nand_defs.h>
20 #include <asm/arch/psc_defs.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 u32 device_big_endian;
26 unsigned int external_clk[ext_clk_count] = {
27 [sys_clk] = 122880000,
28 [alt_core_clk] = 125000000,
30 [tetris_clk] = 125000000,
31 [ddr3a_clk] = 100000000,
32 [ddr3b_clk] = 100000000,
33 [mcm_clk] = 312500000,
34 [pcie_clk] = 100000000,
35 [sgmii_srio_clk] = 156250000,
36 [xgmii_clk] = 156250000,
37 [usb_clk] = 100000000,
38 [rp1_clk] = 123456789 /* TODO: cannot find
42 static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
44 .mode = ASYNC_EMIF_MODE_NAND,
52 .width = ASYNC_EMIF_8,
57 static struct pll_init_data pll_config[] = {
67 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
68 CONFIG_MAX_RAM_BANK_SIZE);
69 init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
73 /* Byte swap the 32-bit data if the device is BE */
74 int cpu_to_bus(u32 *ptr, u32 length)
78 if (device_big_endian)
79 for (i = 0; i < length; i++, ptr++)
80 *ptr = __swab32(*ptr);
85 #if defined(CONFIG_BOARD_EARLY_INIT_F)
86 int board_early_init_f(void)
88 init_plls(ARRAY_SIZE(pll_config), pll_config);
95 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
100 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
101 #define K2_DDR3_START_ADDR 0x80000000
102 void ft_board_setup(void *blob, bd_t *bd)
106 char name[32], *env, *endp;
107 int lpae, nodeoffset;
111 env = getenv("mem_lpae");
112 lpae = env && simple_strtol(env, NULL, 0);
116 env = getenv("ddr3a_size");
118 ddr3a_size = simple_strtol(env, NULL, 10);
119 if ((ddr3a_size != 8) && (ddr3a_size != 4))
124 start[0] = bd->bi_dram[0].start;
125 size[0] = bd->bi_dram[0].size;
127 /* adjust memory start address for LPAE */
129 start[0] -= K2_DDR3_START_ADDR;
130 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
133 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
134 size[1] = ((u64)ddr3a_size - 2) << 30;
135 start[1] = 0x880000000;
139 /* reserve memory at start of bank */
140 sprintf(name, "mem_reserve_head");
143 start[0] += ustrtoul(env, &endp, 0);
144 size[0] -= ustrtoul(env, &endp, 0);
147 sprintf(name, "mem_reserve");
150 size[0] -= ustrtoul(env, &endp, 0);
152 fdt_fixup_memory_banks(blob, start, size, nbanks);
154 /* Fix up the initrd */
156 u64 initrd_start, initrd_end;
159 nodeoffset = fdt_path_offset(blob, "/chosen");
160 if (nodeoffset >= 0) {
161 prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
162 "linux,initrd-start", NULL);
163 prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
164 "linux,initrd-end", NULL);
165 if (prop1 && prop2) {
166 initrd_start = __be32_to_cpu(*prop1);
167 initrd_start -= K2_DDR3_START_ADDR;
168 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
169 initrd_start = __cpu_to_be64(initrd_start);
170 initrd_end = __be32_to_cpu(*prop2);
171 initrd_end -= K2_DDR3_START_ADDR;
172 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
173 initrd_end = __cpu_to_be64(initrd_end);
175 err = fdt_delprop(blob, nodeoffset,
176 "linux,initrd-start");
178 puts("error deleting initrd-start\n");
180 err = fdt_delprop(blob, nodeoffset,
183 puts("error deleting initrd-end\n");
185 err = fdt_setprop(blob, nodeoffset,
186 "linux,initrd-start",
188 sizeof(initrd_start));
190 puts("error adding initrd-start\n");
192 err = fdt_setprop(blob, nodeoffset,
197 puts("error adding linux,initrd-end\n");
203 void ft_board_setup_ex(void *blob, bd_t *bd)
207 u64 *reserve_start, size;
209 env = getenv("mem_lpae");
210 lpae = env && simple_strtol(env, NULL, 0);
214 * the initrd and other reserved memory areas are
215 * embedded in in the DTB itslef. fix up these addresses
218 reserve_start = (u64 *)((char *)blob +
219 fdt_off_mem_rsvmap(blob));
221 *reserve_start = __cpu_to_be64(*reserve_start);
222 size = __cpu_to_be64(*(reserve_start + 1));
224 *reserve_start -= K2_DDR3_START_ADDR;
226 CONFIG_SYS_LPAE_SDRAM_BASE;
228 __cpu_to_be64(*reserve_start);