3 * Texas Instruments Incorporated, <www.ti.com>
4 * Steve Sakoman <steve@sakoman.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/clocks.h>
28 #include <asm/arch/gpio.h>
31 #include "panda_mux_data.h"
33 #ifdef CONFIG_USB_EHCI
35 #include <asm/arch/ehci.h>
36 #include <asm/ehci-omap.h>
39 #define PANDA_ULPI_PHY_TYPE_GPIO 182
41 DECLARE_GLOBAL_DATA_PTR;
43 const struct omap_sysinfo sysinfo = {
44 "Board: OMAP4 Panda\n"
47 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
58 gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
59 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
64 int board_eth_init(bd_t *bis)
70 * @brief misc_init_r - Configure Panda board specific configurations
71 * such as power configurations, ethernet initialization as phase2 of
79 u32 auxclk, altclksrc;
81 /* EHCI is not supported on ES1.0 */
82 if (omap_revision() == OMAP4430_ES1_0)
85 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
86 if (omap_revision() >= OMAP4460_ES1_0 ||
87 omap_revision() <= OMAP4460_ES1_1)
88 setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
91 gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
92 phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
95 /* ULPI PHY supplied by auxclk3 derived from sys_clk */
96 debug("ULPI PHY supplied by auxclk3\n");
98 auxclk = readl(&scrm->auxclk3);
100 auxclk &= ~AUXCLK_SRCSELECT_MASK;
101 auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
102 /* Set the divisor to 2 */
103 auxclk &= ~AUXCLK_CLKDIV_MASK;
104 auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
105 /* Request auxilary clock #3 */
106 auxclk |= AUXCLK_ENABLE_MASK;
108 writel(auxclk, &scrm->auxclk3);
110 /* ULPI PHY supplied by auxclk1 derived from PER dpll */
111 debug("ULPI PHY supplied by auxclk1\n");
113 auxclk = readl(&scrm->auxclk1);
114 /* Select per DPLL */
115 auxclk &= ~AUXCLK_SRCSELECT_MASK;
116 auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
117 /* Set the divisor to 16 */
118 auxclk &= ~AUXCLK_CLKDIV_MASK;
119 auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
120 /* Request auxilary clock #3 */
121 auxclk |= AUXCLK_ENABLE_MASK;
123 writel(auxclk, &scrm->auxclk1);
126 altclksrc = readl(&scrm->altclksrc);
128 /* Activate alternate system clock supplier */
129 altclksrc &= ~ALTCLKSRC_MODE_MASK;
130 altclksrc |= ALTCLKSRC_MODE_ACTIVE;
133 altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
135 writel(altclksrc, &scrm->altclksrc);
140 void set_muxconf_regs_essential(void)
142 do_set_mux((*ctrl)->control_padconf_core_base,
143 core_padconf_array_essential,
144 sizeof(core_padconf_array_essential) /
145 sizeof(struct pad_conf_entry));
147 do_set_mux((*ctrl)->control_padconf_wkup_base,
148 wkup_padconf_array_essential,
149 sizeof(wkup_padconf_array_essential) /
150 sizeof(struct pad_conf_entry));
152 if (omap_revision() >= OMAP4460_ES1_0)
153 do_set_mux((*ctrl)->control_padconf_wkup_base,
154 wkup_padconf_array_essential_4460,
155 sizeof(wkup_padconf_array_essential_4460) /
156 sizeof(struct pad_conf_entry));
159 void set_muxconf_regs_non_essential(void)
161 do_set_mux((*ctrl)->control_padconf_core_base,
162 core_padconf_array_non_essential,
163 sizeof(core_padconf_array_non_essential) /
164 sizeof(struct pad_conf_entry));
166 if (omap_revision() < OMAP4460_ES1_0)
167 do_set_mux((*ctrl)->control_padconf_core_base,
168 core_padconf_array_non_essential_4430,
169 sizeof(core_padconf_array_non_essential_4430) /
170 sizeof(struct pad_conf_entry));
172 do_set_mux((*ctrl)->control_padconf_core_base,
173 core_padconf_array_non_essential_4460,
174 sizeof(core_padconf_array_non_essential_4460) /
175 sizeof(struct pad_conf_entry));
177 do_set_mux((*ctrl)->control_padconf_wkup_base,
178 wkup_padconf_array_non_essential,
179 sizeof(wkup_padconf_array_non_essential) /
180 sizeof(struct pad_conf_entry));
182 if (omap_revision() < OMAP4460_ES1_0)
183 do_set_mux((*ctrl)->control_padconf_wkup_base,
184 wkup_padconf_array_non_essential_4430,
185 sizeof(wkup_padconf_array_non_essential_4430) /
186 sizeof(struct pad_conf_entry));
189 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
190 int board_mmc_init(bd_t *bis)
192 return omap_mmc_init(0, 0, 0, -1, -1);
196 #ifdef CONFIG_USB_EHCI
198 static struct omap_usbhs_board_data usbhs_bdata = {
199 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
200 .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
201 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
204 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
207 unsigned int utmi_clk;
209 /* Now we can enable our port clocks */
210 utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
211 utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
212 sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
214 ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
221 int ehci_hcd_stop(int index)
223 return omap_ehci_hcd_stop();
228 * get_board_rev() - get board revision
230 u32 get_board_rev(void)