3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/processor.h>
37 typedef struct sdram_conf_s sdram_conf_t;
39 sdram_conf_t ddr_cs_conf[] = {
40 {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
41 {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
42 {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
43 {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
46 #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
48 int cas_latency(void);
51 * Autodetect onboard DDR SDRAM on 85xx platforms
53 * NOTE: Some of the hardcoded values are hardware dependant,
54 * so this should be extended for other future boards
57 long int sdram_setup(int casl)
60 volatile immap_t *immap = (immap_t *) CFG_IMMR;
61 volatile ccsr_ddr_t *ddr = &immap->im_ddr;
62 unsigned long cfg_ddr_timing1;
63 unsigned long cfg_ddr_mode;
66 * Disable memory controller.
73 cfg_ddr_timing1 = 0x47405331 | (3 << 16);
74 cfg_ddr_mode = 0x40020002 | (2 << 4);
78 cfg_ddr_timing1 = 0x47405331 | (4 << 16);
79 cfg_ddr_mode = 0x40020002 | (6 << 4);
84 cfg_ddr_timing1 = 0x47405331 | (5 << 16);
85 cfg_ddr_mode = 0x40020002 | (3 << 4);
89 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
90 ddr->cs0_config = ddr_cs_conf[0].reg;
91 ddr->timing_cfg_1 = cfg_ddr_timing1;
92 ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
93 ddr->sdram_mode = cfg_ddr_mode;
94 ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
95 ddr->err_disable = 0x0000000D;
97 asm ("sync;isync;msync");
100 ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
101 asm ("sync; isync; msync");
104 for (i=0; i<N_DDR_CS_CONF; i++) {
105 ddr->cs0_config = ddr_cs_conf[i].reg;
107 if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
109 * OK, size detected -> all done
111 return ddr_cs_conf[i].size;
115 return 0; /* nothing found ! */
118 void board_add_ram_info(int use_default)
123 casl = CONFIG_DDR_DEFAULT_CL;
125 casl = cas_latency();
143 long int initdram (int board_type)
148 #if defined(CONFIG_DDR_DLL)
150 * This DLL-Override only used on TQM8540 and TQM8560
153 volatile immap_t *immap = (immap_t *) CFG_IMMR;
154 volatile ccsr_gur_t *gur= &immap->im_gur;
160 * Work around to stabilize DDR DLL
162 gur->ddrdllcr = 0x81000000;
163 asm("sync;isync;msync");
165 while (gur->ddrdllcr != 0x81000100) {
166 gur->devdisr = gur->devdisr | 0x00010000;
167 asm("sync;isync;msync");
170 gur->devdisr = gur->devdisr & 0xfff7ffff;
171 asm("sync;isync;msync");
177 casl = cas_latency();
178 dram_size = sdram_setup(casl);
179 if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
181 * Try again with default CAS latency
183 puts("Problem with CAS lantency");
184 board_add_ram_info(1);
185 puts(", using default CL!\n");
186 casl = CONFIG_DDR_DEFAULT_CL;
187 dram_size = sdram_setup(casl);
194 #if defined(CFG_DRAM_TEST)
197 uint *pstart = (uint *) CFG_MEMTEST_START;
198 uint *pend = (uint *) CFG_MEMTEST_END;
201 printf ("SDRAM test phase 1:\n");
202 for (p = pstart; p < pend; p++)
205 for (p = pstart; p < pend; p++) {
206 if (*p != 0xaaaaaaaa) {
207 printf ("SDRAM test fails at: %08x\n", (uint) p);
212 printf ("SDRAM test phase 2:\n");
213 for (p = pstart; p < pend; p++)
216 for (p = pstart; p < pend; p++) {
217 if (*p != 0x55555555) {
218 printf ("SDRAM test fails at: %08x\n", (uint) p);
223 printf ("SDRAM test passed.\n");