board/wandboard/wandboard.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/imx-common/iomux-v3.h>
  18 #include <asm/imx-common/boot_mode.h>
  19 #include <asm/io.h>
  20 #include <asm/sizes.h>
  21 #include <common.h>
  22 #include <fsl_esdhc.h>
  23 #include <ipu_pixfmt.h>
  24 #include <mmc.h>
  25 #include <miiphy.h>
  26 #include <netdev.h>
  27 #include <linux/fb.h>
  28 #include <phy.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  33         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  34         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  37         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42
  43 #define USDHC1_CD_GPIO          IMX_GPIO_NR(1, 2)
  44 #define USDHC3_CD_GPIO          IMX_GPIO_NR(3, 9)
  45 #define ETH_PHY_RESET           IMX_GPIO_NR(3, 29)
  46
  47 int dram_init(void)
  48 {
  49         gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
  50
  51         return 0;
  52 }
  53
  54 static iomux_v3_cfg_t const uart1_pads[] = {
  55         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  56         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  57 };
  58
  59 static iomux_v3_cfg_t const usdhc1_pads[] = {
  60         MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61         MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66         /* Carrier MicroSD Card Detect */
  67         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(NO_PAD_CTRL),
  68 };
  69
  70 static iomux_v3_cfg_t const usdhc3_pads[] = {
  71         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  72         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  73         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  74         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77         /* SOM MicroSD Card Detect */
  78         MX6_PAD_EIM_DA9__GPIO3_IO09     | MUX_PAD_CTRL(NO_PAD_CTRL),
  79 };
  80
  81 static iomux_v3_cfg_t const enet_pads[] = {
  82         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97         /* AR8031 PHY Reset */
  98         MX6_PAD_EIM_D29__GPIO3_IO29             | MUX_PAD_CTRL(NO_PAD_CTRL),
  99 };
 100
 101 static void setup_iomux_uart(void)
 102 {
 103         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 104 }
 105
 106 static void setup_iomux_enet(void)
 107 {
 108         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 109
 110         /* Reset AR8031 PHY */
 111         gpio_direction_output(ETH_PHY_RESET, 0);
 112         udelay(500);
 113         gpio_set_value(ETH_PHY_RESET, 1);
 114 }
 115
 116 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 117         {USDHC3_BASE_ADDR},
 118         {USDHC1_BASE_ADDR},
 119 };
 120
 121 int board_mmc_getcd(struct mmc *mmc)
 122 {
 123         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 124         int ret = 0;
 125
 126         switch (cfg->esdhc_base) {
 127         case USDHC1_BASE_ADDR:
 128                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 129                 break;
 130         case USDHC3_BASE_ADDR:
 131                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 132                 break;
 133         }
 134
 135         return ret;
 136 }
 137
 138 int board_mmc_init(bd_t *bis)
 139 {
 140         s32 status = 0;
 141         u32 index = 0;
 142
 143         /*
 144          * Following map is done:
 145          * (U-boot device node)    (Physical Port)
 146          * mmc0                    SOM MicroSD
 147          * mmc1                    Carrier board MicroSD
 148          */
 149         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 150                 switch (index) {
 151                 case 0:
 152                         imx_iomux_v3_setup_multiple_pads(
 153                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 154                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 155                         usdhc_cfg[0].max_bus_width = 4;
 156                         gpio_direction_input(USDHC3_CD_GPIO);
 157                         break;
 158                 case 1:
 159                         imx_iomux_v3_setup_multiple_pads(
 160                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 161                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 162                         usdhc_cfg[1].max_bus_width = 4;
 163                         gpio_direction_input(USDHC1_CD_GPIO);
 164                         break;
 165                 default:
 166                         printf("Warning: you configured more USDHC controllers"
 167                                "(%d) then supported by the board (%d)\n",
 168                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 169                         return status;
 170                 }
 171
 172                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 173         }
 174
 175         return status;
 176 }
 177
 178 static int mx6_rgmii_rework(struct phy_device *phydev)
 179 {
 180         unsigned short val;
 181
 182         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 183         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 184         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 185         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 186
 187         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 188         val &= 0xffe3;
 189         val |= 0x18;
 190         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 191
 192         /* introduce tx clock delay */
 193         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 194         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 195         val |= 0x0100;
 196         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 197
 198         return 0;
 199 }
 200
 201 int board_phy_config(struct phy_device *phydev)
 202 {
 203         mx6_rgmii_rework(phydev);
 204
 205         if (phydev->drv->config)
 206                 phydev->drv->config(phydev);
 207
 208         return 0;
 209 }
 210
 211 #if defined(CONFIG_VIDEO_IPUV3)
 212 static struct fb_videomode const hdmi = {
 213         .name           = "HDMI",
 214         .refresh        = 60,
 215         .xres           = 1024,
 216         .yres           = 768,
 217         .pixclock       = 15385,
 218         .left_margin    = 220,
 219         .right_margin   = 40,
 220         .upper_margin   = 21,
 221         .lower_margin   = 7,
 222         .hsync_len      = 60,
 223         .vsync_len      = 10,
 224         .sync           = FB_SYNC_EXT,
 225         .vmode          = FB_VMODE_NONINTERLACED
 226 };
 227
 228 int board_video_skip(void)
 229 {
 230         int ret;
 231
 232         ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
 233
 234         if (ret) {
 235                 printf("HDMI cannot be configured: %d\n", ret);
 236                 return ret;
 237         }
 238
 239         imx_enable_hdmi_phy();
 240
 241         return ret;
 242 }
 243
 244 static void setup_display(void)
 245 {
 246         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 247         int reg;
 248
 249         enable_ipu_clock();
 250         imx_setup_hdmi();
 251
 252         reg = readl(&mxc_ccm->chsccdr);
 253         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 254                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 255         writel(reg, &mxc_ccm->chsccdr);
 256 }
 257 #endif /* CONFIG_VIDEO_IPUV3 */
 258
 259 int board_eth_init(bd_t *bis)
 260 {
 261         setup_iomux_enet();
 262
 263         return cpu_eth_init(bis);
 264 }
 265
 266 int board_early_init_f(void)
 267 {
 268         setup_iomux_uart();
 269 #if defined(CONFIG_VIDEO_IPUV3)
 270         setup_display();
 271 #endif
 272         return 0;
 273 }
 274
 275 /*
 276  * Do not overwrite the console
 277  * Use always serial for U-Boot console
 278  */
 279 int overwrite_console(void)
 280 {
 281         return 1;
 282 }
 283
 284 #ifdef CONFIG_CMD_BMODE
 285 static const struct boot_mode board_boot_modes[] = {
 286         /* 4 bit bus width */
 287         {"mmc0",          MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 288         {"mmc1",          MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 289         {NULL,   0},
 290 };
 291 #endif
 292
 293 int board_late_init(void)
 294 {
 295 #ifdef CONFIG_CMD_BMODE
 296         add_board_boot_modes(board_boot_modes);
 297 #endif
 298
 299         return 0;
 300 }
 301
 302 int board_init(void)
 303 {
 304         /* address of boot parameters */
 305         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 306
 307         return 0;
 308 }
 309
 310 int checkboard(void)
 311 {
 312         puts("Board: Wandboard\n");
 313
 314         return 0;
 315 }