2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
76 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
86 * Note: _armboot_end_data and _armboot_end are defined
87 * by the (board-dependent) linker script.
88 * _armboot_end_data is the first usable FLASH address after armboot
90 .globl _armboot_end_data
92 .word armboot_end_data
98 * _armboot_real_end is the first usable RAM address behind armboot
99 * and the various stacks
101 .globl _armboot_real_end
105 #ifdef CONFIG_USE_IRQ
106 /* IRQ stack memory (calculated at run-time) */
107 .globl IRQ_STACK_START
111 /* IRQ stack memory (calculated at run-time) */
112 .globl FIQ_STACK_START
119 * the actual reset code
124 * set the cpu to SVC32 mode
131 /* turn off the watchdog */
132 #if defined(CONFIG_S3C2400)
133 #define pWTCON 0x15300000
134 /* Interupt-Controller base addresses */
135 #define INTMSK 0x14400008
136 /* clock divisor register */
137 #define CLKDIVN 0x14800014
138 #elif defined(CONFIG_S3C2410)
139 #define pWTCON 0x53000000
140 /* Interupt-Controller base addresses */
141 #define INTMSK 0x4A000008
142 #define INTSUBMSK 0x4A00001C
143 /* clock divisor register */
144 #define CLKDIVN 0x4C000014
152 * mask all IRQs by setting all bits in the INTMR - default
157 #if defined(CONFIG_S3C2410)
163 /* FCLK:HCLK:PCLK = 1:2:4 */
164 /* default FCLK is 120 MHz ! */
170 * we do sys-critical inits only at reboot,
171 * not when booting from ram!
173 #ifdef CONFIG_INIT_CRITICAL
179 * relocate armboot to RAM
181 adr r0, _start /* r0 <- current position of code */
182 ldr r2, _armboot_start
184 sub r2, r3, r2 /* r2 <- size of armboot */
185 ldr r1, _TEXT_BASE /* r1 <- destination address */
186 add r2, r0, r2 /* r2 <- source end address */
189 * r0 = source address
190 * r1 = target address
191 * r2 = source end address
200 /* try doing this stuff after the relocation */
206 * mask all IRQs by setting all bits in the INTMR - default
212 /* FCLK:HCLK:PCLK = 1:2:4 */
213 /* default FCLK is 120 MHz ! */
217 /* END stuff after relocation */
220 /* set up the stack */
222 add r0, r0, #CONFIG_STACKSIZE
223 sub sp, r0, #12 /* leave 3 words for abort-stack */
225 ldr pc, _start_armboot
227 _start_armboot: .word start_armboot
231 *************************************************************************
233 * CPU_init_critical registers
235 * setup important registers
236 * setup memory timing
238 *************************************************************************
244 * flush v4 I/D caches
247 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
248 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
251 * disable MMU stuff and caches
253 mrc p15, 0, r0, c1, c0, 0
254 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
255 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
256 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
257 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
258 mcr p15, 0, r0, c1, c0, 0
262 * before relocating, we have to setup RAM timing
263 * because memory timing is board-dependend, you will
264 * find a memsetup.S in your board directory.
274 *************************************************************************
278 *************************************************************************
284 #define S_FRAME_SIZE 72
306 #define MODE_SVC 0x13
310 * use bad_save_user_regs for abort/prefetch/undef/swi ...
311 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
314 .macro bad_save_user_regs
315 sub sp, sp, #S_FRAME_SIZE
316 stmia sp, {r0 - r12} @ Calling r0-r12
318 add r2, r2, #CONFIG_STACKSIZE
320 ldmia r2, {r2 - r3} @ get pc, cpsr
321 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
325 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
329 .macro irq_save_user_regs
330 sub sp, sp, #S_FRAME_SIZE
331 stmia sp, {r0 - r12} @ Calling r0-r12
333 stmdb r8, {sp, lr}^ @ Calling SP, LR
334 str lr, [r8, #0] @ Save calling PC
336 str r6, [r8, #4] @ Save CPSR
337 str r0, [r8, #8] @ Save OLD_R0
341 .macro irq_restore_user_regs
342 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
344 ldr lr, [sp, #S_PC] @ Get PC
345 add sp, sp, #S_FRAME_SIZE
346 subs pc, lr, #4 @ return & move spsr_svc into cpsr
350 ldr r13, _armboot_end @ setup our mode stack
351 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
354 str lr, [r13] @ save caller lr / spsr
358 mov r13, #MODE_SVC @ prepare SVC-Mode
365 .macro get_irq_stack @ setup IRQ stack
366 ldr sp, IRQ_STACK_START
369 .macro get_fiq_stack @ setup FIQ stack
370 ldr sp, FIQ_STACK_START
377 undefined_instruction:
380 bl do_undefined_instruction
386 bl do_software_interrupt
406 #ifdef CONFIG_USE_IRQ
413 irq_restore_user_regs
418 /* someone ought to write a more effiction fiq_save_user_regs */
421 irq_restore_user_regs
442 #ifdef CONFIG_S3C2400
443 bl disable_interrupts
449 /* Disable watchdog */
452 /* Initialize watchdog timer count register */
455 /* Enable watchdog timer; assert reset at timer timeout */
464 #else /* ! CONFIG_S3C2400 */
466 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
467 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
468 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
469 bic ip, ip, #0x000f @ ............wcam
470 bic ip, ip, #0x2100 @ ..v....s........
471 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
473 #endif /* CONFIG_S3C2400 */