2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
83 * Note: _armboot_end_data and _armboot_end are defined
84 * by the (board-dependent) linker script.
85 * _armboot_end_data is the first usable FLASH address after armboot
87 .globl _armboot_end_data
89 .word armboot_end_data
95 * _armboot_real_end is the first usable RAM address behind armboot
96 * and the various stacks
98 .globl _armboot_real_end
102 #ifdef CONFIG_USE_IRQ
103 /* IRQ stack memory (calculated at run-time) */
104 .globl IRQ_STACK_START
108 /* IRQ stack memory (calculated at run-time) */
109 .globl FIQ_STACK_START
116 * the actual reset code
121 * set the cpu to SVC32 mode
128 /* turn off the watchdog */
129 #if defined(CONFIG_S3C2400)
130 #define pWTCON 0x15300000
131 /* Interupt-Controller base addresses */
132 #define INTMSK 0x14400008
133 /* clock divisor register */
134 #define CLKDIVN 0x14800014
135 #elif defined(CONFIG_S3C2410)
136 #define pWTCON 0x53000000
137 /* Interupt-Controller base addresses */
138 #define INTMSK 0x4A000008
139 #define INTSUBMSK 0x4A00001C
140 /* clock divisor register */
141 #define CLKDIVN 0x4C000014
149 * mask all IRQs by setting all bits in the INTMR - default
154 #if defined(CONFIG_S3C2410)
160 /* FCLK:HCLK:PCLK = 1:2:4 */
161 /* default FCLK is 120 MHz ! */
167 * we do sys-critical inits only at reboot,
168 * not when booting from ram!
170 #ifdef CONFIG_INIT_CRITICAL
176 * relocate armboot to RAM
178 adr r0, _start /* r0 <- current position of code */
179 ldr r2, _armboot_start
181 sub r2, r3, r2 /* r2 <- size of armboot */
182 ldr r1, _TEXT_BASE /* r1 <- destination address */
183 add r2, r0, r2 /* r2 <- source end address */
186 * r0 = source address
187 * r1 = target address
188 * r2 = source end address
197 /* try doing this stuff after the relocation */
203 * mask all IRQs by setting all bits in the INTMR - default
209 /* FCLK:HCLK:PCLK = 1:2:4 */
210 /* default FCLK is 120 MHz ! */
214 /* END stuff after relocation */
217 /* set up the stack */
219 add r0, r0, #CONFIG_STACKSIZE
220 sub sp, r0, #12 /* leave 3 words for abort-stack */
222 ldr pc, _start_armboot
224 _start_armboot: .word start_armboot
228 *************************************************************************
230 * CPU_init_critical registers
232 * setup important registers
233 * setup memory timing
235 *************************************************************************
241 * flush v4 I/D caches
244 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
245 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
248 * disable MMU stuff and caches
250 mrc p15, 0, r0, c1, c0, 0
251 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
252 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
253 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
254 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
255 mcr p15, 0, r0, c1, c0, 0
259 * before relocating, we have to setup RAM timing
260 * because memory timing is board-dependend, you will
261 * find a memsetup.S in your board directory.
271 *************************************************************************
275 *************************************************************************
281 #define S_FRAME_SIZE 72
303 #define MODE_SVC 0x13
307 * use bad_save_user_regs for abort/prefetch/undef/swi ...
308 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
311 .macro bad_save_user_regs
312 sub sp, sp, #S_FRAME_SIZE
313 stmia sp, {r0 - r12} @ Calling r0-r12
315 add r2, r2, #CONFIG_STACKSIZE
317 ldmia r2, {r2 - r3} @ get pc, cpsr
318 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
322 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
326 .macro irq_save_user_regs
327 sub sp, sp, #S_FRAME_SIZE
328 stmia sp, {r0 - r12} @ Calling r0-r12
330 stmdb r8, {sp, lr}^ @ Calling SP, LR
331 str lr, [r8, #0] @ Save calling PC
333 str r6, [r8, #4] @ Save CPSR
334 str r0, [r8, #8] @ Save OLD_R0
338 .macro irq_restore_user_regs
339 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
341 ldr lr, [sp, #S_PC] @ Get PC
342 add sp, sp, #S_FRAME_SIZE
343 subs pc, lr, #4 @ return & move spsr_svc into cpsr
347 ldr r13, _armboot_end @ setup our mode stack
348 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
351 str lr, [r13] @ save caller lr / spsr
355 mov r13, #MODE_SVC @ prepare SVC-Mode
362 .macro get_irq_stack @ setup IRQ stack
363 ldr sp, IRQ_STACK_START
366 .macro get_fiq_stack @ setup FIQ stack
367 ldr sp, FIQ_STACK_START
374 undefined_instruction:
377 bl do_undefined_instruction
383 bl do_software_interrupt
403 #ifdef CONFIG_USE_IRQ
410 irq_restore_user_regs
415 /* someone ought to write a more effiction fiq_save_user_regs */
418 irq_restore_user_regs
439 #ifdef CONFIG_S3C2400
440 bl disable_interrupts
446 /* Disable watchdog */
449 /* Initialize watchdog timer count register */
452 /* Enable watchdog timer; assert reset at timer timeout */
461 #else /* ! CONFIG_S3C2400 */
463 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
464 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
465 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
466 bic ip, ip, #0x000f @ ............wcam
467 bic ip, ip, #0x2100 @ ..v....s........
468 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
470 #endif /* CONFIG_S3C2400 */