2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
35 *************************************************************************
37 * Jump vector table as in table 3.1 in [1]
39 *************************************************************************
45 ldr pc, _undefined_instruction
46 ldr pc, _software_interrupt
47 ldr pc, _prefetch_abort
53 _undefined_instruction: .word undefined_instruction
54 _software_interrupt: .word software_interrupt
55 _prefetch_abort: .word prefetch_abort
56 _data_abort: .word data_abort
57 _not_used: .word not_used
61 .balignl 16,0xdeadbeef
65 *************************************************************************
67 * Startup Code (reset vector)
69 * do important init only if we don't start from memory!
70 * relocate armboot to ram
72 * jump to second stage
74 *************************************************************************
85 * These are defined in the board-specific linker script.
96 /* IRQ stack memory (calculated at run-time) */
97 .globl IRQ_STACK_START
101 /* IRQ stack memory (calculated at run-time) */
102 .globl FIQ_STACK_START
109 * the actual reset code
114 * set the cpu to SVC32 mode
121 #if CONFIG_AT91RM9200
122 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
127 #ifdef CONFIG_BOOTBINFUNC
128 /* code based on entry.S from ATMEL */
129 #define AT91C_BASE_CKGR 0xFFFFFC20
131 /* Get the CKGR Base Address */
132 ldr r1, =AT91C_BASE_CKGR
134 /* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
135 /* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
137 str r0, [r1, #CKGR_MOR]
138 /* Add loop to compensate Main Oscillator startup time */
145 /* Insure word alignment */
150 * This does a lot more than just set up the memory, which
151 * is why it's called lowlevelinit
153 bl lowlevelinit /* in memsetup.S */
155 /* ------------------------------------
156 * Read/modify/write CP15 control register
157 * -------------------------------------
158 * read cp15 control register (cp15 r1) in r0
159 * ------------------------------------
161 mrc p15, 0, r0, c1, c0, 0
162 /* Reset bit :Little Endian end fast bus mode */
164 /* Set bit :Asynchronous clock mode, Not Fast Bus */
168 /* write r0 in cp15 control register (cp15 r1) */
169 mcr p15, 0, r0, c1, c0, 0
170 #endif /* CONFIG_BOOTBINFUNC */
172 * relocate exeception table
184 /* turn off the watchdog */
185 #if defined(CONFIG_S3C2400)
186 # define pWTCON 0x15300000
187 # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
188 # define CLKDIVN 0x14800014 /* clock divisor register */
189 #elif defined(CONFIG_S3C2410)
190 # define pWTCON 0x53000000
191 # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
192 # define INTSUBMSK 0x4A00001C
193 # define CLKDIVN 0x4C000014 /* clock divisor register */
196 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
202 * mask all IRQs by setting all bits in the INTMR - default
207 # if defined(CONFIG_S3C2410)
213 /* FCLK:HCLK:PCLK = 1:2:4 */
214 /* default FCLK is 120 MHz ! */
218 #endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
221 * we do sys-critical inits only at reboot,
222 * not when booting from ram!
224 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
228 #ifdef CONFIG_AT91RM9200
229 #ifdef CONFIG_BOOTBINFUNC
230 relocate: /* relocate U-Boot to RAM */
231 adr r0, _start /* r0 <- current position of code */
232 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
233 cmp r0, r1 /* don't reloc during debug */
236 ldr r2, _armboot_start
238 sub r2, r3, r2 /* r2 <- size of armboot */
239 add r2, r0, r2 /* r2 <- source end address */
242 ldmia r0!, {r3-r10} /* copy from source address [r0] */
243 stmia r1!, {r3-r10} /* copy to target address [r1] */
244 cmp r0, r2 /* until source end addreee [r2] */
246 #endif /* CONFIG_BOOTBINFUNC */
248 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
249 relocate: /* relocate U-Boot to RAM */
250 adr r0, _start /* r0 <- current position of code */
251 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
252 cmp r0, r1 /* don't reloc during debug */
255 ldr r2, _armboot_start
257 sub r2, r3, r2 /* r2 <- size of armboot */
258 add r2, r0, r2 /* r2 <- source end address */
261 ldmia r0!, {r3-r10} /* copy from source address [r0] */
262 stmia r1!, {r3-r10} /* copy to target address [r1] */
263 cmp r0, r2 /* until source end addreee [r2] */
265 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
267 /* Set up the stack */
269 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
270 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
271 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
272 #ifdef CONFIG_USE_IRQ
273 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
275 sub sp, r0, #12 /* leave 3 words for abort-stack */
278 ldr r0, _bss_start /* find start of bss segment */
279 ldr r1, _bss_end /* stop here */
280 mov r2, #0x00000000 /* clear */
282 clbss_l:str r2, [r0] /* clear loop... */
288 /* try doing this stuff after the relocation */
294 * mask all IRQs by setting all bits in the INTMR - default
300 /* FCLK:HCLK:PCLK = 1:2:4 */
301 /* default FCLK is 120 MHz ! */
305 /* END stuff after relocation */
308 ldr pc, _start_armboot
310 _start_armboot: .word start_armboot
314 *************************************************************************
316 * CPU_init_critical registers
318 * setup important registers
319 * setup memory timing
321 *************************************************************************
325 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
328 * flush v4 I/D caches
331 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
332 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
335 * disable MMU stuff and caches
337 mrc p15, 0, r0, c1, c0, 0
338 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
339 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
340 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
341 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
342 mcr p15, 0, r0, c1, c0, 0
345 * before relocating, we have to setup RAM timing
346 * because memory timing is board-dependend, you will
347 * find a lowlevel_init.S in your board directory.
350 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)
357 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
360 *************************************************************************
364 *************************************************************************
370 #define S_FRAME_SIZE 72
392 #define MODE_SVC 0x13
396 * use bad_save_user_regs for abort/prefetch/undef/swi ...
397 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
400 .macro bad_save_user_regs
401 sub sp, sp, #S_FRAME_SIZE
402 stmia sp, {r0 - r12} @ Calling r0-r12
403 ldr r2, _armboot_start
404 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
405 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
406 ldmia r2, {r2 - r3} @ get pc, cpsr
407 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
411 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
415 .macro irq_save_user_regs
416 sub sp, sp, #S_FRAME_SIZE
417 stmia sp, {r0 - r12} @ Calling r0-r12
419 stmdb r8, {sp, lr}^ @ Calling SP, LR
420 str lr, [r8, #0] @ Save calling PC
422 str r6, [r8, #4] @ Save CPSR
423 str r0, [r8, #8] @ Save OLD_R0
427 .macro irq_restore_user_regs
428 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
430 ldr lr, [sp, #S_PC] @ Get PC
431 add sp, sp, #S_FRAME_SIZE
432 subs pc, lr, #4 @ return & move spsr_svc into cpsr
436 ldr r13, _armboot_start @ setup our mode stack
437 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
438 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
440 str lr, [r13] @ save caller lr / spsr
444 mov r13, #MODE_SVC @ prepare SVC-Mode
451 .macro get_irq_stack @ setup IRQ stack
452 ldr sp, IRQ_STACK_START
455 .macro get_fiq_stack @ setup FIQ stack
456 ldr sp, FIQ_STACK_START
463 undefined_instruction:
466 bl do_undefined_instruction
472 bl do_software_interrupt
492 #ifdef CONFIG_USE_IRQ
499 irq_restore_user_regs
504 /* someone ought to write a more effiction fiq_save_user_regs */
507 irq_restore_user_regs