3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 #include <asm/cache.h>
28 #include <u-boot/md5.h>
29 #include <asm/arch/kirkwood.h>
33 void reset_cpu(unsigned long ignored)
35 struct kwcpu_registers *cpureg =
36 (struct kwcpu_registers *)KW_CPU_REG_BASE;
38 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
39 &cpureg->rstoutn_mask);
40 writel(readl(&cpureg->sys_soft_rst) | 1,
41 &cpureg->sys_soft_rst);
46 * Generates Ramdom hex number reading some time varient system registers
47 * and using md5 algorithm
49 unsigned char get_random_hex(void)
56 * in case of 88F6281/88F6192 A0,
57 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
58 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and
59 * Does not have names at this moment (no errata available)
61 writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
62 for (i = 0; i < BUFLEN; i++) {
63 inbuf[i] = readl(KW_REG_UNDOC_0x1470);
65 md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
66 return outbuf[outbuf[7] % 0x0f];
71 * Used with the Base register to set the address window size and location.
72 * Must be programmed from LSB to MSB as sequence of ones followed by
73 * sequence of zeros. The number of ones specifies the size of the window in
74 * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
75 * NOTE: A value of 0x0 specifies 64-KByte size.
77 unsigned int kw_winctrl_calcsize(unsigned int sizeval)
81 u32 val = sizeval >> 1;
83 for (i = 0; val > 0x10000; i++) {
87 return (0x0000ffff & j);
91 * kw_config_adr_windows - Configure address Windows
93 * There are 8 address windows supported by Kirkwood Soc to addess different
94 * devices. Each window can be configured for size, BAR and remap addr
95 * Below configuration is standard for most of the cases
97 * If remap function not used, remap_lo must be set as base
99 * Reference Documentation:
100 * Mbus-L to Mbus Bridge Registers Configuration.
101 * (Sec 25.1 and 25.3 of Datasheet)
103 int kw_config_adr_windows(void)
105 struct kwwin_registers *winregs =
106 (struct kwwin_registers *)KW_CPU_WIN_BASE;
108 /* Window 0: PCIE MEM address space */
109 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
110 KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
112 writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
113 writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
114 writel(0x0, &winregs[0].remap_hi);
116 /* Window 1: PCIE IO address space */
117 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
118 KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
119 writel(KW_DEFADR_PCI_IO, &winregs[1].base);
120 writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
121 writel(0x0, &winregs[1].remap_hi);
123 /* Window 2: NAND Flash address space */
124 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
125 KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
126 writel(KW_DEFADR_NANDF, &winregs[2].base);
127 writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
128 writel(0x0, &winregs[2].remap_hi);
130 /* Window 3: SPI Flash address space */
131 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
132 KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
133 writel(KW_DEFADR_SPIF, &winregs[3].base);
134 writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
135 writel(0x0, &winregs[3].remap_hi);
137 /* Window 4: BOOT Memory address space */
138 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
139 KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
140 writel(KW_DEFADR_BOOTROM, &winregs[4].base);
142 /* Window 5: Security SRAM address space */
143 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
144 KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
145 writel(KW_DEFADR_SASRAM, &winregs[5].base);
147 /* Window 6-7: Disabled */
148 writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
149 writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
155 * kw_config_gpio - GPIO configuration
157 void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
159 struct kwgpio_registers *gpio0reg =
160 (struct kwgpio_registers *)KW_GPIO0_BASE;
161 struct kwgpio_registers *gpio1reg =
162 (struct kwgpio_registers *)KW_GPIO1_BASE;
164 /* Init GPIOS to default values as per board requirement */
165 writel(gpp0_oe_val, &gpio0reg->dout);
166 writel(gpp1_oe_val, &gpio1reg->dout);
167 writel(gpp0_oe, &gpio0reg->oe);
168 writel(gpp1_oe, &gpio1reg->oe);
172 * kw_config_mpp - Multi-Purpose Pins Functionality configuration
174 * Each MPP can be configured to different functionality through
175 * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
177 * There are maximum 64 Multi-Pourpose Pins on Kirkwood
178 * Each MPP functionality can be configuration by a 4bit value
179 * of MPP control reg, the value and associated functionality depends
180 * upon used SoC varient
182 int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
183 u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
185 u32 *mppreg = (u32 *) KW_MPP_BASE;
187 /* program mpp registers */
188 writel(mpp0_7, &mppreg[0]);
189 writel(mpp8_15, &mppreg[1]);
190 writel(mpp16_23, &mppreg[2]);
191 writel(mpp24_31, &mppreg[3]);
192 writel(mpp32_39, &mppreg[4]);
193 writel(mpp40_47, &mppreg[5]);
194 writel(mpp48_55, &mppreg[6]);
199 * SYSRSTn Duration Counter Support
201 * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
202 * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
203 * The SYSRSTn duration counter is useful for implementing a manufacturer
204 * or factory reset. Upon a long reset assertion that is greater than a
205 * pre-configured environment variable value for sysrstdelay,
206 * The counter value is stored in the SYSRSTn Length Counter Register
207 * The counter is based on the 25-MHz reference clock (40ns)
208 * It is a 29-bit counter, yielding a maximum counting duration of
209 * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
210 * it remains at this value until counter reset is triggered by setting
211 * bit 31 of KW_REG_SYSRST_CNT
213 static void kw_sysrst_action(void)
216 char *s = getenv("sysrstcmd");
219 debug("Error.. %s failed, check sysrstcmd\n",
224 debug("Starting %s process...\n", __FUNCTION__);
225 #if !defined(CONFIG_SYS_HUSH_PARSER)
226 ret = run_command (s, 0);
228 ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON
229 | FLAG_EXIT_FROM_LOOP);
232 debug("Error.. %s failed\n", __FUNCTION__);
234 debug("%s process finished\n", __FUNCTION__);
237 static void kw_sysrst_check(void)
239 u32 sysrst_cnt, sysrst_dly;
243 * no action if sysrstdelay environment variable is not defined
245 s = getenv("sysrstdelay");
249 /* read sysrstdelay value */
250 sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
252 /* read SysRst Length counter register (bits 28:0) */
253 sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
254 debug("H/w Rst hold time: %d.%d secs\n",
255 sysrst_cnt / SYSRST_CNT_1SEC_VAL,
256 sysrst_cnt % SYSRST_CNT_1SEC_VAL);
258 /* clear the counter for next valid read*/
259 writel(1 << 31, KW_REG_SYSRST_CNT);
263 * if H/w Reset key is pressed and hold for time
264 * more than sysrst_dly in seconds
266 if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
270 #if defined(CONFIG_DISPLAY_CPUINFO)
271 int print_cpuinfo(void)
273 char *name = "Unknown";
275 switch (readl(KW_REG_DEVICE_ID) & 0x03) {
283 printf("SoC: Unsupported Kirkwood\n");
286 printf("SoC: Kirkwood %s\n", name);
289 #endif /* CONFIG_DISPLAY_CPUINFO */
291 #ifdef CONFIG_ARCH_CPU_INIT
292 int arch_cpu_init(void)
295 struct kwcpu_registers *cpureg =
296 (struct kwcpu_registers *)KW_CPU_REG_BASE;
298 /* Linux expects` the internal registers to be at 0xf1000000 */
299 writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
301 /* Enable and invalidate L2 cache in write through mode */
302 writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
303 invalidate_l2_cache();
305 kw_config_adr_windows();
307 #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
309 * Configures the I/O voltage of the pads connected to Egigabit
310 * Ethernet interface to 1.8V
311 * By defult it is set to 3.3V
313 reg = readl(KW_REG_MPP_OUT_DRV_REG);
315 writel(reg, KW_REG_MPP_OUT_DRV_REG);
317 #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
319 * Set egiga port0/1 in normal functional mode
320 * This is required becasue on kirkwood by default ports are in reset mode
321 * OS egiga driver may not have provision to set them in normal mode
322 * and if u-boot is build without network support, network may fail at OS level
324 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
325 reg &= ~(1 << 4); /* Clear PortReset Bit */
326 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
327 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
328 reg &= ~(1 << 4); /* Clear PortReset Bit */
329 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
331 #ifdef CONFIG_KIRKWOOD_PCIE_INIT
333 * Enable PCI Express Port0
335 reg = readl(&cpureg->ctrl_stat);
336 reg |= (1 << 0); /* Set PEX0En Bit */
337 writel(reg, &cpureg->ctrl_stat);
341 #endif /* CONFIG_ARCH_CPU_INIT */
344 * SOC specific misc init
346 #if defined(CONFIG_ARCH_MISC_INIT)
347 int arch_misc_init(void)
351 /*CPU streaming & write allocate */
352 temp = readfr_extra_feature_reg();
353 temp &= ~(1 << 28); /* disable wr alloc */
354 writefr_extra_feature_reg(temp);
356 temp = readfr_extra_feature_reg();
357 temp &= ~(1 << 29); /* streaming disabled */
358 writefr_extra_feature_reg(temp);
360 /* L2Cache settings */
361 temp = readfr_extra_feature_reg();
362 /* Disable L2C pre fetch - Set bit 24 */
364 /* enable L2C - Set bit 22 */
366 writefr_extra_feature_reg(temp);
369 /* Change reset vector to address 0x0 */
371 set_cr(temp & ~CR_V);
373 /* checks and execute resset to factory event */
378 #endif /* CONFIG_ARCH_MISC_INIT */
380 #ifdef CONFIG_KIRKWOOD_EGIGA
381 int cpu_eth_init(bd_t *bis)
383 kirkwood_egiga_initialize(bis);