3 * Common board functions for OMAP3 based boards.
5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com>
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/mem.h>
39 #include <asm/cache.h>
41 extern omap3_sysinfo sysinfo;
43 extern u32 is_mem_sdr(void);
45 /******************************************************************************
47 * Description: spinning delay to use before udelay works
48 *****************************************************************************/
49 static inline void delay(unsigned long loops)
51 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
52 "bne 1b":"=r" (loops):"0"(loops));
55 /******************************************************************************
56 * Routine: secure_unlock
57 * Description: Setup security registers for access
59 *****************************************************************************/
60 void secure_unlock_mem(void)
62 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
63 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
64 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
65 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
66 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
68 /* Protection Module Register Target APE (PM_RT) */
69 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
70 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
71 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
72 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
74 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
75 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
76 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
78 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
79 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
80 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
81 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
84 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
85 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
86 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
88 /* SDRC region 0 public */
89 writel(UNLOCK_1, &sms_base->rg_att0);
92 /******************************************************************************
93 * Routine: secureworld_exit()
94 * Description: If chip is EMU and boot type is external
95 * configure secure registers and exit secure world
97 *****************************************************************************/
98 void secureworld_exit()
102 /* configrue non-secure access control register */
103 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
104 /* enabling co-processor CP10 and CP11 accesses in NS world */
105 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
107 * allow allocation of locked TLBs and L2 lines in NS world
108 * allow use of PLE registers in NS world also
110 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
111 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
113 /* Enable ASA in ACR register */
114 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
115 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
116 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
118 /* Exiting secure world */
119 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
120 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
121 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
124 /******************************************************************************
125 * Routine: setup_auxcr()
126 * Description: Write to AuxCR desired value using SMI.
128 *****************************************************************************/
132 volatile unsigned int j;
133 /* Save r0, r12 and restore them after usage */
134 __asm__ __volatile__("mov %0, r12":"=r"(j));
135 __asm__ __volatile__("mov %0, r0":"=r"(i));
138 * GP Device ROM code API usage here
139 * r12 = AUXCR Write function and r0 value
141 __asm__ __volatile__("mov r12, #0x3");
142 __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
144 __asm__ __volatile__("orr r0, r0, #0x10");
146 __asm__ __volatile__("orr r0, r0, #1 << 5");
147 /* SMI instruction to call ROM Code API */
148 __asm__ __volatile__(".word 0xE1600070");
149 __asm__ __volatile__("mov r0, %0":"=r"(i));
150 __asm__ __volatile__("mov r12, %0":"=r"(j));
153 /******************************************************************************
154 * Routine: try_unlock_sram()
155 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
157 *****************************************************************************/
158 void try_unlock_memory()
161 int in_sdram = is_running_in_sdram();
164 * if GP device unlock device SRAM for general use
165 * secure code breaks for Secure/Emulation device - HS/E/T
167 mode = get_device_type();
168 if (mode == GP_DEVICE)
172 * If device is EMU and boot is XIP external booting
173 * Unlock firewalls and disable L2 and put chip
174 * out of secure world
176 * Assuming memories are unlocked by the demon who put us in SDRAM
178 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
187 /******************************************************************************
189 * Description: Does early system init of muxing and clocks.
190 * - Called path is with SRAM stack.
191 *****************************************************************************/
194 int in_sdram = is_running_in_sdram();
201 * Right now flushing at low MPU speed.
202 * Need to move after clock init
204 v7_flush_dcache_all(get_device_type());
205 #ifndef CONFIG_ICACHE_OFF
215 * Writing to AuxCR in U-boot using SMI for GP DEV
216 * Currently SMI in Kernel on ES2 devices seems to have an issue
217 * Once that is resolved, we can postpone this config to kernel
219 if (get_device_type() == GP_DEVICE)
233 /******************************************************************************
234 * Routine: wait_for_command_complete
235 * Description: Wait for posting to finish on watchdog
236 *****************************************************************************/
237 void wait_for_command_complete(struct watchdog *wd_base)
241 pending = readl(&wd_base->wwps);
245 /******************************************************************************
246 * Routine: watchdog_init
247 * Description: Shut down watch dogs
248 *****************************************************************************/
249 void watchdog_init(void)
251 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
252 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
255 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
256 * either taken care of by ROM (HS/EMU) or not accessible (GP).
257 * We need to take care of WD2-MPU or take a PRCM reset. WD3
258 * should not be running and does not generate a PRCM reset.
261 sr32(&prcm_base->fclken_wkup, 5, 1, 1);
262 sr32(&prcm_base->iclken_wkup, 5, 1, 1);
263 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
265 writel(WD_UNLOCK1, &wd2_base->wspr);
266 wait_for_command_complete(wd2_base);
267 writel(WD_UNLOCK2, &wd2_base->wspr);
270 /******************************************************************************
272 * Description: sets uboots idea of sdram size
273 *****************************************************************************/
276 DECLARE_GLOBAL_DATA_PTR;
277 unsigned int size0 = 0, size1 = 0;
280 * If a second bank of DDR is attached to CS1 this is
281 * where it can be started. Early init code will init
284 if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
285 do_sdrc_init(CS1, NOT_EARLY);
286 make_cs1_contiguous();
289 size0 = get_sdr_cs_size(CS0);
290 size1 = get_sdr_cs_size(CS1);
292 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
293 gd->bd->bi_dram[0].size = size0;
294 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
295 gd->bd->bi_dram[1].size = size1;
300 /******************************************************************************
301 * Dummy function to handle errors for EABI incompatibility
302 *****************************************************************************/
307 /******************************************************************************
308 * Dummy function to handle errors for EABI incompatibility
309 *****************************************************************************/
314 #ifdef CONFIG_NAND_OMAP_GPMC
315 /******************************************************************************
316 * OMAP3 specific command to switch between NAND HW and SW ecc
317 *****************************************************************************/
318 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
322 if (strncmp(argv[1], "hw", 2) == 0)
323 omap_nand_switch_ecc(1);
324 else if (strncmp(argv[1], "sw", 2) == 0)
325 omap_nand_switch_ecc(0);
332 printf ("Usage: nandecc %s\n", cmdtp->usage);
337 nandecc, 2, 1, do_switch_ecc,
338 "nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
339 "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
342 #endif /* CONFIG_NAND_OMAP_GPMC */
344 #ifdef CONFIG_DISPLAY_BOARDINFO
346 * Print board information
348 int checkboard (void)
357 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
358 sysinfo.nand_string);
362 #endif /* CONFIG_DISPLAY_BOARDINFO */