2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
82 * These are defined in the board-specific linker script.
93 /* IRQ stack memory (calculated at run-time) */
94 .globl IRQ_STACK_START
98 /* IRQ stack memory (calculated at run-time) */
99 .globl FIQ_STACK_START
106 * the actual reset code
111 * set the cpu to SVC32 mode
115 orr r0,r0,#0xd3 /* was 13 */
118 #ifdef CONFIG_BOOTBINFUNC
121 /* Insure word alignment */
126 * This does a lot more than just set up the memory, which
127 * is why it's called lowlevelinit
129 bl lowlevelinit /* in lowlevel.S */
131 /*------------------------------------
132 Read/modify/write CP15 control register
133 -------------------------------------
134 read cp15 control register (cp15 r1) in r0
135 ------------------------------------*/
136 mrc p15, 0, r0, c1, c0, 0
137 /* Reset bit :Little Endian end fast bus mode */
139 /* Set bit :Asynchronous clock mode, Not Fast Bus */
143 /* write r0 in cp15 control register (cp15 r1) */
144 mcr p15, 0, r0, c1, c0, 0
145 #endif /* CONFIG_BOOTBINFUNC */
147 * relocate exeception table
159 * we do sys-critical inits only at reboot,
160 * not when booting from ram!
162 #ifdef CONFIG_INIT_CRITICAL
166 #ifdef CONFIG_BOOTBINFUNC
167 relocate: /* relocate U-Boot to RAM */
168 adr r0, _start /* r0 <- current position of code */
169 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
170 cmp r0, r1 /* don't reloc during debug */
173 ldr r2, _armboot_start
175 sub r2, r3, r2 /* r2 <- size of armboot */
176 add r2, r0, r2 /* r2 <- source end address */
179 ldmia r0!, {r3-r10} /* copy from source address [r0] */
180 stmia r1!, {r3-r10} /* copy to target address [r1] */
181 cmp r0, r2 /* until source end addreee [r2] */
183 #endif /* CONFIG_BOOTBINFUNC */
185 /* Set up the stack */
187 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
188 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
189 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
190 #ifdef CONFIG_USE_IRQ
191 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
193 sub sp, r0, #12 /* leave 3 words for abort-stack */
196 ldr r0, _bss_start /* find start of bss segment */
197 ldr r1, _bss_end /* stop here */
198 mov r2, #0x00000000 /* clear */
200 clbss_l:str r2, [r0] /* clear loop... */
205 ldr pc,_start_armboot
207 _start_armboot: .word start_armboot
210 *************************************************************************
212 * CPU_init_critical registers
214 *************************************************************************
218 /* do nothing for now */
223 *************************************************************************
227 *************************************************************************
233 #define S_FRAME_SIZE 72
255 #define MODE_SVC 0x13
259 * use bad_save_user_regs for abort/prefetch/undef/swi ...
260 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
263 .macro bad_save_user_regs
264 sub sp, sp, #S_FRAME_SIZE
265 stmia sp, {r0 - r12} @ Calling r0-r12
268 ldr r2, _armboot_start
269 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
270 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
271 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
272 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
276 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
280 .macro irq_save_user_regs
281 sub sp, sp, #S_FRAME_SIZE
282 stmia sp, {r0 - r12} @ Calling r0-r12
284 stmdb r8, {sp, lr}^ @ Calling SP, LR
285 str lr, [r8, #0] @ Save calling PC
287 str r6, [r8, #4] @ Save CPSR
288 str r0, [r8, #8] @ Save OLD_R0
292 .macro irq_restore_user_regs
293 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
295 ldr lr, [sp, #S_PC] @ Get PC
296 add sp, sp, #S_FRAME_SIZE
297 subs pc, lr, #4 @ return & move spsr_svc into cpsr
301 ldr r13, _armboot_start @ setup our mode stack
302 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
303 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
305 str lr, [r13] @ save caller lr / spsr
309 mov r13, #MODE_SVC @ prepare SVC-Mode
315 .macro get_irq_stack @ setup IRQ stack
316 ldr sp, IRQ_STACK_START
319 .macro get_fiq_stack @ setup FIQ stack
320 ldr sp, FIQ_STACK_START
327 undefined_instruction:
330 bl do_undefined_instruction
336 bl do_software_interrupt
356 #ifdef CONFIG_USE_IRQ
363 irq_restore_user_regs
368 /* someone ought to write a more effiction fiq_save_user_regs */
371 irq_restore_user_regs