2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
83 * These are defined in the board-specific linker script.
94 /* IRQ stack memory (calculated at run-time) */
95 .globl IRQ_STACK_START
99 /* IRQ stack memory (calculated at run-time) */
100 .globl FIQ_STACK_START
107 * the actual reset code
112 * set the cpu to SVC32 mode
119 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
120 #define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
121 #define pCLKSET 0x80000420 /* clock divisor register */
123 /* disable watchdog, set watchdog control register to
124 * all zeros (default reset)
131 * mask all IRQs by setting all bits in the INTENC register (default)
137 /* FCLK:HCLK:PCLK = 1:2:2 */
138 /* default FCLK is 200 MHz, using 14.7456 MHz fin */
141 @ ldr r1, =0x0005ee39 @ 1: 2: 4
145 * we do sys-critical inits only at reboot,
146 * not when booting from ram!
148 #ifdef CONFIG_INIT_CRITICAL
152 relocate: /* relocate U-Boot to RAM */
153 adr r0, _start /* r0 <- current position of code */
154 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
155 cmp r0, r1 /* don't reloc during debug */
158 ldr r2, _armboot_start
160 sub r2, r3, r2 /* r2 <- size of armboot */
161 add r2, r0, r2 /* r2 <- source end address */
164 ldmia r0!, {r3-r10} /* copy from source address [r0] */
165 stmia r1!, {r3-r10} /* copy to target address [r1] */
166 cmp r0, r2 /* until source end addreee [r2] */
167 blt copy_loop /* a 'ble' here actually copies */
168 /* four bytes of bss */
170 /* Set up the stack */
172 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
173 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
174 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
175 #ifdef CONFIG_USE_IRQ
176 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
178 sub sp, r0, #12 /* leave 3 words for abort-stack */
181 ldr r0, _bss_start /* find start of bss segment */
182 @add r0, r0, #4 /* start at first byte of bss */
183 /* why inc. 4 bytes past then? */
184 ldr r1, _bss_end /* stop here */
185 mov r2, #0x00000000 /* clear */
187 clbss_l:str r2, [r0] /* clear loop... */
192 ldr pc, _start_armboot
194 _start_armboot: .word start_armboot
198 *************************************************************************
200 * CPU_init_critical registers
202 * setup important registers
203 * setup memory timing
205 *************************************************************************
211 * flush v4 I/D caches
214 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
215 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
218 * disable MMU stuff and caches
220 mrc p15, 0, r0, c1, c0, 0
221 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
222 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
223 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
224 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
225 orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
226 mcr p15, 0, r0, c1, c0, 0
230 * before relocating, we have to setup RAM timing
231 * because memory timing is board-dependend, you will
232 * find a memsetup.S in your board directory.
242 *************************************************************************
246 *************************************************************************
252 #define S_FRAME_SIZE 72
274 #define MODE_SVC 0x13
278 * use bad_save_user_regs for abort/prefetch/undef/swi ...
279 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
282 .macro bad_save_user_regs
283 sub sp, sp, #S_FRAME_SIZE
284 stmia sp, {r0 - r12} @ Calling r0-r12
285 ldr r2, _armboot_start
286 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
287 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
288 ldmia r2, {r2 - r3} @ get pc, cpsr
289 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
293 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
297 .macro irq_save_user_regs
298 sub sp, sp, #S_FRAME_SIZE
299 stmia sp, {r0 - r12} @ Calling r0-r12
301 stmdb r8, {sp, lr}^ @ Calling SP, LR
302 str lr, [r8, #0] @ Save calling PC
304 str r6, [r8, #4] @ Save CPSR
305 str r0, [r8, #8] @ Save OLD_R0
309 .macro irq_restore_user_regs
310 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
312 ldr lr, [sp, #S_PC] @ Get PC
313 add sp, sp, #S_FRAME_SIZE
314 subs pc, lr, #4 @ return & move spsr_svc into cpsr
318 ldr r13, _armboot_start @ setup our mode stack
319 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
320 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
322 str lr, [r13] @ save caller lr / spsr
326 mov r13, #MODE_SVC @ prepare SVC-Mode
333 .macro get_irq_stack @ setup IRQ stack
334 ldr sp, IRQ_STACK_START
337 .macro get_fiq_stack @ setup FIQ stack
338 ldr sp, FIQ_STACK_START
345 undefined_instruction:
348 bl do_undefined_instruction
354 bl do_software_interrupt
374 #ifdef CONFIG_USE_IRQ
381 irq_restore_user_regs
386 /* someone ought to write a more effiction fiq_save_user_regs */
389 irq_restore_user_regs
410 bl disable_interrupts
412 /* Disable watchdog */
421 /* Enable the watchdog */