3 * Josef Baumgartner <josef.baumgartner@telex.de>
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
9 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
11 * Hayden Fraser (Hayden.Fraser@freescale.com)
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/immap.h>
36 #if defined(CONFIG_M5253)
38 * Breath some life into the CPU...
40 * Set up the memory map,
41 * initialize a bunch of registers,
42 * initialize the UPM's
46 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
47 mbar_writeByte(MCFSIM_SYPCR, 0x00);
48 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
49 mbar_writeByte(MCFSIM_SWSR, 0x00);
50 mbar_writeByte(MCFSIM_SWDICR, 0x00);
51 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
52 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
53 mbar_writeByte(MCFSIM_I2CICR, 0x00);
54 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
55 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
56 mbar_writeByte(MCFSIM_ICR6, 0x00);
57 mbar_writeByte(MCFSIM_ICR7, 0x00);
58 mbar_writeByte(MCFSIM_ICR8, 0x00);
59 mbar_writeByte(MCFSIM_ICR9, 0x00);
60 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
62 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
63 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
64 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
66 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
69 * Setup chip selects...
72 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
73 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
74 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
76 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
77 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
78 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
80 /* enable instruction cache now */
84 /*initialize higher level parts of CPU like timers */
90 void uart_port_conf(void)
93 switch (CFG_UART_PORT) {
102 #endif /* #if defined(CONFIG_M5253) */
104 #if defined(CONFIG_M5271)
105 void cpu_init_f(void)
107 #ifndef CONFIG_WATCHDOG
108 /* Disable the watchdog if we aren't using it */
109 mbar_writeShort(MCF_WTM_WCR, 0);
112 /* Set clockspeed to 100MHz */
113 mbar_writeShort(MCF_FMPLL_SYNCR,
114 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
115 while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
119 * initialize higher level parts of CPU like timers
126 void uart_port_conf(void)
129 switch (CFG_UART_PORT) {
131 mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
132 MCF_GPIO_PAR_UART_U0RXD);
135 mbar_writeShort(MCF_GPIO_PAR_UART,
136 MCF_GPIO_PAR_UART_U1RXD_UART1 |
137 MCF_GPIO_PAR_UART_U1TXD_UART1);
140 mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
146 #if defined(CONFIG_M5272)
148 * Breath some life into the CPU...
150 * Set up the memory map,
151 * initialize a bunch of registers,
152 * initialize the UPM's
154 void cpu_init_f(void)
156 /* if we come from RAM we assume the CPU is
157 * already initialized.
159 #ifndef CONFIG_MONITOR_IS_IN_RAM
160 volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
161 volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
162 volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
164 sysctrl->sc_scr = CFG_SCR;
165 sysctrl->sc_spr = CFG_SPR;
168 gpio->gpio_pacnt = CFG_PACNT;
169 gpio->gpio_paddr = CFG_PADDR;
170 gpio->gpio_padat = CFG_PADAT;
171 gpio->gpio_pbcnt = CFG_PBCNT;
172 gpio->gpio_pbddr = CFG_PBDDR;
173 gpio->gpio_pbdat = CFG_PBDAT;
174 gpio->gpio_pdcnt = CFG_PDCNT;
176 /* Memory Controller: */
177 csctrl->cs_br0 = CFG_BR0_PRELIM;
178 csctrl->cs_or0 = CFG_OR0_PRELIM;
180 #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
181 csctrl->cs_br1 = CFG_BR1_PRELIM;
182 csctrl->cs_or1 = CFG_OR1_PRELIM;
185 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
186 csctrl->cs_br2 = CFG_BR2_PRELIM;
187 csctrl->cs_or2 = CFG_OR2_PRELIM;
190 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
191 csctrl->cs_br3 = CFG_BR3_PRELIM;
192 csctrl->cs_or3 = CFG_OR3_PRELIM;
195 #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
196 csctrl->cs_br4 = CFG_BR4_PRELIM;
197 csctrl->cs_or4 = CFG_OR4_PRELIM;
200 #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
201 csctrl->cs_br5 = CFG_BR5_PRELIM;
202 csctrl->cs_or5 = CFG_OR5_PRELIM;
205 #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
206 csctrl->cs_br6 = CFG_BR6_PRELIM;
207 csctrl->cs_or6 = CFG_OR6_PRELIM;
210 #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
211 csctrl->cs_br7 = CFG_BR7_PRELIM;
212 csctrl->cs_or7 = CFG_OR7_PRELIM;
215 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
217 /* enable instruction cache now */
223 * initialize higher level parts of CPU like timers
230 void uart_port_conf(void)
232 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
235 switch (CFG_UART_PORT) {
237 gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
238 gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
241 gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
242 gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
246 #endif /* #if defined(CONFIG_M5272) */
248 #if defined(CONFIG_M5282)
250 * Breath some life into the CPU...
252 * Set up the memory map,
253 * initialize a bunch of registers,
254 * initialize the UPM's
256 void cpu_init_f(void)
258 #ifndef CONFIG_WATCHDOG
259 /* disable watchdog if we aren't using it */
263 #ifndef CONFIG_MONITOR_IS_IN_RAM
266 MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
267 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
269 MCFGPIO_PBCDPAR = 0xc0;
271 /* Set up the GPIO ports */
273 MCFGPIO_PEPAR = CFG_PEPAR;
276 MCFGPIO_PFPAR = CFG_PFPAR;
279 MCFGPIO_PJPAR = CFG_PJPAR;
282 MCFGPIO_PSDPAR = CFG_PSDPAR;
285 MCFGPIO_PASPAR = CFG_PASPAR;
288 MCFGPIO_PEHLPAR = CFG_PEHLPAR;
291 MCFGPIO_PQSPAR = CFG_PQSPAR;
294 MCFGPIO_PTCPAR = CFG_PTCPAR;
297 MCFGPIO_PTDPAR = CFG_PTDPAR;
300 MCFGPIO_PUAPAR = CFG_PUAPAR;
304 MCFGPIO_DDRUA = CFG_DDRUA;
307 /* This is probably a bad place to setup chip selects, but everyone
310 #if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
311 defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
314 MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
316 #if (CFG_CS0_WIDTH == 8)
317 #define CFG_CS0_PS MCFCSM_CSCR_PS_8
318 #elif (CFG_CS0_WIDTH == 16)
319 #define CFG_CS0_PS MCFCSM_CSCR_PS_16
320 #elif (CFG_CS0_WIDTH == 32)
321 #define CFG_CS0_PS MCFCSM_CSCR_PS_32
323 #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
325 MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
326 | CFG_CS0_PS | MCFCSM_CSCR_AA;
328 #if (CFG_CS0_RO != 0)
329 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
330 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
332 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
335 #waring "Chip Select 0 are not initialized/used"
338 #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
339 defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
342 MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
344 #if (CFG_CS1_WIDTH == 8)
345 #define CFG_CS1_PS MCFCSM_CSCR_PS_8
346 #elif (CFG_CS1_WIDTH == 16)
347 #define CFG_CS1_PS MCFCSM_CSCR_PS_16
348 #elif (CFG_CS1_WIDTH == 32)
349 #define CFG_CS1_PS MCFCSM_CSCR_PS_32
351 #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
353 MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
354 | CFG_CS1_PS | MCFCSM_CSCR_AA;
356 #if (CFG_CS1_RO != 0)
357 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
358 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
360 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
364 #warning "Chip Select 1 are not initialized/used"
367 #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
368 defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
371 MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
373 #if (CFG_CS2_WIDTH == 8)
374 #define CFG_CS2_PS MCFCSM_CSCR_PS_8
375 #elif (CFG_CS2_WIDTH == 16)
376 #define CFG_CS2_PS MCFCSM_CSCR_PS_16
377 #elif (CFG_CS2_WIDTH == 32)
378 #define CFG_CS2_PS MCFCSM_CSCR_PS_32
380 #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
382 MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
383 | CFG_CS2_PS | MCFCSM_CSCR_AA;
385 #if (CFG_CS2_RO != 0)
386 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
387 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
389 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
393 #warning "Chip Select 2 are not initialized/used"
396 #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
397 defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
400 MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
402 #if (CFG_CS3_WIDTH == 8)
403 #define CFG_CS3_PS MCFCSM_CSCR_PS_8
404 #elif (CFG_CS3_WIDTH == 16)
405 #define CFG_CS3_PS MCFCSM_CSCR_PS_16
406 #elif (CFG_CS3_WIDTH == 32)
407 #define CFG_CS3_PS MCFCSM_CSCR_PS_32
409 #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
411 MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
412 | CFG_CS3_PS | MCFCSM_CSCR_AA;
414 #if (CFG_CS3_RO != 0)
415 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
416 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
418 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
422 #warning "Chip Select 3 are not initialized/used"
425 #endif /* CONFIG_MONITOR_IS_IN_RAM */
427 /* defer enabling cache until boot (see do_go) */
428 /* icache_enable(); */
432 * initialize higher level parts of CPU like timers
439 void uart_port_conf(void)
442 switch (CFG_UART_PORT) {
444 MCFGPIO_PUAPAR &= 0xFc;
445 MCFGPIO_PUAPAR |= 0x03;
448 MCFGPIO_PUAPAR &= 0xF3;
449 MCFGPIO_PUAPAR |= 0x0C;
452 MCFGPIO_PASPAR &= 0xFF0F;
453 MCFGPIO_PASPAR |= 0x00A0;
459 #if defined(CONFIG_M5249)
461 * Breath some life into the CPU...
463 * Set up the memory map,
464 * initialize a bunch of registers,
465 * initialize the UPM's
467 void cpu_init_f(void)
470 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
471 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
472 * which is their primary function.
475 mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
476 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
477 mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
478 mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
479 mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
480 mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
484 * You can verify these values by using dBug's 'ird'
485 * (Internal Register Display) command
489 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
490 mbar_writeByte(MCFSIM_SYPCR, 0x00);
491 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
492 mbar_writeByte(MCFSIM_SWSR, 0x00);
493 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
494 mbar_writeByte(MCFSIM_SWDICR, 0x00);
495 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
496 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
497 mbar_writeByte(MCFSIM_I2CICR, 0x00);
498 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
499 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
500 mbar_writeByte(MCFSIM_ICR6, 0x00);
501 mbar_writeByte(MCFSIM_ICR7, 0x00);
502 mbar_writeByte(MCFSIM_ICR8, 0x00);
503 mbar_writeByte(MCFSIM_ICR9, 0x00);
504 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
506 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
507 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
508 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
509 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
511 /* Setup interrupt priorities for gpio7 */
512 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
514 /* IDE Config registers */
515 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
516 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
519 * Setup chip selects...
522 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
523 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
524 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
526 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
527 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
528 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
530 /* enable instruction cache now */
535 * initialize higher level parts of CPU like timers
542 void uart_port_conf(void)
545 switch (CFG_UART_PORT) {
552 #endif /* #if defined(CONFIG_M5249) */