2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
28 #include <asm/processor.h>
33 /* System RAM mapped over PCI */
34 #define CONFIG_PCI_MEMORY_BUS CFG_SDRAM_BASE
35 #define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
36 #define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
38 /* PCIIWCR bit fields */
39 #define IWCR_MEM (0 << 3)
40 #define IWCR_IO (1 << 3)
41 #define IWCR_READ (0 << 1)
42 #define IWCR_READLINE (1 << 1)
43 #define IWCR_READMULT (2 << 1)
44 #define IWCR_EN (1 << 0)
46 static int mpc5200_read_config_dword(struct pci_controller *hose,
47 pci_dev_t dev, int offset, u32* value)
49 *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
51 *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
53 *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
55 if (offset == 0 && *value == 0x58031057)
60 static int mpc5200_write_config_dword(struct pci_controller *hose,
61 pci_dev_t dev, int offset, u32 value)
63 *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
65 out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
67 *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
71 void pci_mpc5xxx_init (struct pci_controller *hose)
73 hose->first_busno = 0;
74 hose->last_busno = 0xff;
77 pci_set_region(hose->regions + 0,
78 CONFIG_PCI_MEMORY_BUS,
79 CONFIG_PCI_MEMORY_PHYS,
80 CONFIG_PCI_MEMORY_SIZE,
81 PCI_REGION_MEM | PCI_REGION_MEMORY);
83 /* PCI memory space */
84 pci_set_region(hose->regions + 1,
91 pci_set_region(hose->regions + 2,
97 hose->region_count = 3;
99 pci_register_hose(hose);
101 /* GPIO Multiplexing - enable PCI */
102 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
104 /* Set host bridge as pci master and enable memory decoding */
105 *(vu_long *)MPC5XXX_PCI_CMD |=
106 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
108 /* Set maximum latency timer */
109 *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
111 /* Set cache line size */
112 *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
113 (CFG_CACHELINE_SIZE / 4);
115 /* Map MBAR to PCI space */
116 *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
117 *(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
119 /* Map RAM to PCI space */
120 *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
121 *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
123 /* Enable snooping for RAM */
124 *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
125 *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
127 /* Park XLB on PCI */
128 *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
129 *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
131 /* Enable piplining */
132 *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
134 /* Disable interrupts from PCI controller */
135 *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
136 *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
138 /* Disable initiator windows */
139 *(vu_long *)MPC5XXX_PCI_IWCR = 0;
141 /* Map PCI memory to physical space */
142 *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
143 (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
144 (CONFIG_PCI_MEM_BUS >> 16);
145 *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
147 /* Map PCI I/O to physical space */
148 *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
149 (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
150 (CONFIG_PCI_IO_BUS >> 16);
151 *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
153 /* Reset the PCI bus */
154 *(vu_long *)MPC5XXX_PCI_GSCR |= 1;
156 *(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
160 pci_hose_read_config_byte_via_dword,
161 pci_hose_read_config_word_via_dword,
162 mpc5200_read_config_dword,
163 pci_hose_write_config_byte_via_dword,
164 pci_hose_write_config_word_via_dword,
165 mpc5200_write_config_dword);
169 #ifdef CONFIG_PCI_SCAN_SHOW
170 printf("PCI: Bus Dev VenId DevId Class Int\n");
173 hose->last_busno = pci_hose_scan(hose);
175 #endif /* CONFIG_PCI && CONFIG_MPC5200 */