2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
30 #include <mpc8260_irq.h>
31 #include <asm/processor.h>
32 #ifdef CONFIG_STATUS_LED
33 #include <status_led.h>
36 /****************************************************************************/
38 unsigned decrementer_count; /* count val for 1e6/HZ microseconds */
41 interrupt_handler_t *handler;
46 static struct irq_action irq_handlers[NR_IRQS];
48 static ulong ppc_cached_irq_mask[NR_MASK_WORDS];
50 /****************************************************************************/
51 /* this section was ripped out of arch/ppc/kernel/ppc8260_pic.c in the */
52 /* Linux/PPC 2.4.x source. There was no copyright notice in that file. */
54 /* The 8260 internal interrupt controller. It is usually
55 * the only interrupt controller.
56 * There are two 32-bit registers (high/low) for up to 64
57 * possible interrupts.
59 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
60 * in a simple arithmetic fashion to mask or pending registers.
61 * That is, interrupt 4 does not map to bit position 4.
62 * We create two tables, indexed by vector number, to indicate
63 * which register to use and which bit in the register to use.
65 static u_char irq_to_siureg[] = {
66 1, 1, 1, 1, 1, 1, 1, 1,
67 1, 1, 1, 1, 1, 1, 1, 1,
68 0, 0, 0, 0, 0, 0, 0, 0,
69 0, 0, 0, 0, 0, 0, 0, 0,
70 1, 1, 1, 1, 1, 1, 1, 1,
71 1, 1, 1, 1, 1, 1, 1, 1,
72 0, 0, 0, 0, 0, 0, 0, 0,
73 0, 0, 0, 0, 0, 0, 0, 0
76 static u_char irq_to_siubit[] = {
77 31, 16, 17, 18, 19, 20, 21, 22,
78 23, 24, 25, 26, 27, 28, 29, 30,
79 29, 30, 16, 17, 18, 19, 20, 21,
80 22, 23, 24, 25, 26, 27, 28, 31,
81 0, 1, 2, 3, 4, 5, 6, 7,
82 8, 9, 10, 11, 12, 13, 14, 15,
83 15, 14, 13, 12, 11, 10, 9, 8,
84 7, 6, 5, 4, 3, 2, 1, 0
87 static void m8260_mask_irq (unsigned int irq_nr)
89 volatile immap_t *immr = (immap_t *) CFG_IMMR;
93 bit = irq_to_siubit[irq_nr];
94 word = irq_to_siureg[irq_nr];
96 simr = &(immr->im_intctl.ic_simrh);
97 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
98 simr[word] = ppc_cached_irq_mask[word];
101 static void m8260_unmask_irq (unsigned int irq_nr)
103 volatile immap_t *immr = (immap_t *) CFG_IMMR;
107 bit = irq_to_siubit[irq_nr];
108 word = irq_to_siureg[irq_nr];
110 simr = &(immr->im_intctl.ic_simrh);
111 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
112 simr[word] = ppc_cached_irq_mask[word];
115 static void m8260_mask_and_ack (unsigned int irq_nr)
117 volatile immap_t *immr = (immap_t *) CFG_IMMR;
119 volatile uint *simr, *sipnr;
121 bit = irq_to_siubit[irq_nr];
122 word = irq_to_siureg[irq_nr];
124 simr = &(immr->im_intctl.ic_simrh);
125 sipnr = &(immr->im_intctl.ic_sipnrh);
126 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
127 simr[word] = ppc_cached_irq_mask[word];
128 sipnr[word] = 1 << (31 - bit);
131 static int m8260_get_irq (struct pt_regs *regs)
133 volatile immap_t *immr = (immap_t *) CFG_IMMR;
137 /* For MPC8260, read the SIVEC register and shift the bits down
138 * to get the irq number. */
139 bits = immr->im_intctl.ic_sivec;
144 /* end of code ripped out of arch/ppc/kernel/ppc8260_pic.c */
145 /****************************************************************************/
147 static __inline__ unsigned long get_msr (void)
151 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
156 static __inline__ void set_msr (unsigned long msr)
158 __asm__ __volatile__ ("mtmsr %0;sync;isync"::"r" (msr));
161 static __inline__ unsigned long get_dec (void)
165 __asm__ __volatile__ ("mfdec %0":"=r" (val):);
170 static __inline__ void set_dec (unsigned long val)
172 __asm__ __volatile__ ("mtdec %0"::"r" (val));
175 void enable_interrupts (void)
177 set_msr (get_msr () | MSR_EE);
180 /* returns flag if MSR_EE was set before */
181 int disable_interrupts (void)
183 ulong msr = get_msr ();
185 set_msr (msr & ~MSR_EE);
186 return ((msr & MSR_EE) != 0);
189 /****************************************************************************/
191 int interrupt_init (void)
193 DECLARE_GLOBAL_DATA_PTR;
195 volatile immap_t *immr = (immap_t *) CFG_IMMR;
197 decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
199 /* Initialize the default interrupt mapping priorities */
200 immr->im_intctl.ic_sicr = 0;
201 immr->im_intctl.ic_siprr = 0x05309770;
202 immr->im_intctl.ic_scprrh = 0x05309770;
203 immr->im_intctl.ic_scprrl = 0x05309770;
205 /* disable all interrupts and clear all pending bits */
206 immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
207 immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
208 immr->im_intctl.ic_sipnrh = 0xffffffff;
209 immr->im_intctl.ic_sipnrl = 0xffffffff;
213 * ensure all external interrupt sources default to trigger on
214 * high-to-low transition (i.e. edge triggered active low)
216 immr->im_intctl.ic_siexr = -1;
219 set_dec (decrementer_count);
221 set_msr (get_msr () | MSR_EE);
226 /****************************************************************************/
229 * Handle external interrupts
231 void external_interrupt (struct pt_regs *regs)
235 irq = m8260_get_irq (regs);
237 m8260_mask_and_ack (irq);
239 set_msr (get_msr () | MSR_EE);
241 if (irq_handlers[irq].handler != NULL)
242 (*irq_handlers[irq].handler) (irq_handlers[irq].arg);
244 printf ("\nBogus External Interrupt IRQ %d\n", irq);
246 * turn off the bogus interrupt, otherwise it
247 * might repeat forever
253 m8260_unmask_irq (irq);
256 /****************************************************************************/
259 * Install and free an interrupt handler.
263 irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
265 if (irq < 0 || irq >= NR_IRQS) {
266 printf ("irq_install_handler: bad irq number %d\n", irq);
270 if (irq_handlers[irq].handler != NULL)
271 printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
272 (ulong) handler, (ulong) irq_handlers[irq].handler);
274 irq_handlers[irq].handler = handler;
275 irq_handlers[irq].arg = arg;
277 m8260_unmask_irq (irq);
280 void irq_free_handler (int irq)
282 if (irq < 0 || irq >= NR_IRQS) {
283 printf ("irq_free_handler: bad irq number %d\n", irq);
287 m8260_mask_irq (irq);
289 irq_handlers[irq].handler = NULL;
290 irq_handlers[irq].arg = NULL;
293 /****************************************************************************/
295 volatile ulong timestamp = 0;
298 * timer_interrupt - gets called when the decrementer overflows,
299 * with interrupts disabled.
300 * Trivial implementation - no need to be really accurate.
302 void timer_interrupt (struct pt_regs *regs)
304 #if defined(CONFIG_WATCHDOG) || defined(CFG_HYMOD_DBLEDS)
305 volatile immap_t *immr = (immap_t *) CFG_IMMR;
306 #endif /* CONFIG_WATCHDOG */
308 /* Restore Decrementer Count */
309 set_dec (decrementer_count);
313 #if defined(CONFIG_WATCHDOG) || \
314 defined(CFG_CMA_LCD_HEARTBEAT) || \
315 defined(CFG_HYMOD_DBLEDS)
317 if ((timestamp % CFG_HZ) == 0) {
318 #if defined(CFG_CMA_LCD_HEARTBEAT)
319 extern void lcd_heartbeat (void);
320 #endif /* CFG_CMA_LCD_HEARTBEAT */
321 #if defined(CFG_HYMOD_DBLEDS)
322 volatile iop8260_t *iop = &immr->im_ioport;
323 static int shift = 0;
324 #endif /* CFG_HYMOD_DBLEDS */
326 #if defined(CFG_CMA_LCD_HEARTBEAT)
328 #endif /* CFG_CMA_LCD_HEARTBEAT */
330 #if defined(CONFIG_WATCHDOG)
331 reset_8260_watchdog (immr);
332 #endif /* CONFIG_WATCHDOG */
334 #if defined(CFG_HYMOD_DBLEDS)
335 /* hymod daughter board LEDs */
339 (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
340 #endif /* CFG_HYMOD_DBLEDS */
342 #endif /* CONFIG_WATCHDOG || CFG_CMA_LCD_HEARTBEAT */
344 #ifdef CONFIG_STATUS_LED
345 status_led_tick (timestamp);
346 #endif /* CONFIG_STATUS_LED */
349 /****************************************************************************/
351 void reset_timer (void)
356 ulong get_timer (ulong base)
358 return (timestamp - base);
361 void set_timer (ulong t)
366 /****************************************************************************/
368 #if (CONFIG_COMMANDS & CFG_CMD_IRQ)
370 /* ripped this out of ppc4xx/interrupts.c */
372 /*******************************************************************************
374 * irqinfo - print information about PCI devices
378 do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
382 re_enable = disable_interrupts ();
384 printf ("\nInterrupt-Information:\n");
385 printf ("Nr Routine Arg Count\n");
387 for (irq = 0; irq < 32; irq++)
388 if (irq_handlers[irq].handler != NULL)
389 printf ("%02d %08lx %08lx %ld\n", irq,
390 (ulong) irq_handlers[irq].handler,
391 (ulong) irq_handlers[irq].arg,
392 irq_handlers[irq].count);
395 enable_interrupts ();
398 #endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */