2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
29 #include <mpc8260_irq.h>
30 #include <asm/processor.h>
32 /****************************************************************************/
35 interrupt_handler_t *handler;
40 static struct irq_action irq_handlers[NR_IRQS];
42 static ulong ppc_cached_irq_mask[NR_MASK_WORDS];
44 /****************************************************************************/
45 /* this section was ripped out of arch/ppc/kernel/ppc8260_pic.c in the */
46 /* Linux/PPC 2.4.x source. There was no copyright notice in that file. */
48 /* The 8260 internal interrupt controller. It is usually
49 * the only interrupt controller.
50 * There are two 32-bit registers (high/low) for up to 64
51 * possible interrupts.
53 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
54 * in a simple arithmetic fashion to mask or pending registers.
55 * That is, interrupt 4 does not map to bit position 4.
56 * We create two tables, indexed by vector number, to indicate
57 * which register to use and which bit in the register to use.
59 static u_char irq_to_siureg[] = {
60 1, 1, 1, 1, 1, 1, 1, 1,
61 1, 1, 1, 1, 1, 1, 1, 1,
62 0, 0, 0, 0, 0, 0, 0, 0,
63 0, 0, 0, 0, 0, 0, 0, 0,
64 1, 1, 1, 1, 1, 1, 1, 1,
65 1, 1, 1, 1, 1, 1, 1, 1,
66 0, 0, 0, 0, 0, 0, 0, 0,
67 0, 0, 0, 0, 0, 0, 0, 0
70 static u_char irq_to_siubit[] = {
71 31, 16, 17, 18, 19, 20, 21, 22,
72 23, 24, 25, 26, 27, 28, 29, 30,
73 29, 30, 16, 17, 18, 19, 20, 21,
74 22, 23, 24, 25, 26, 27, 28, 31,
75 0, 1, 2, 3, 4, 5, 6, 7,
76 8, 9, 10, 11, 12, 13, 14, 15,
77 15, 14, 13, 12, 11, 10, 9, 8,
78 7, 6, 5, 4, 3, 2, 1, 0
81 static void m8260_mask_irq (unsigned int irq_nr)
83 volatile immap_t *immr = (immap_t *) CFG_IMMR;
87 bit = irq_to_siubit[irq_nr];
88 word = irq_to_siureg[irq_nr];
90 simr = &(immr->im_intctl.ic_simrh);
91 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
92 simr[word] = ppc_cached_irq_mask[word];
95 static void m8260_unmask_irq (unsigned int irq_nr)
97 volatile immap_t *immr = (immap_t *) CFG_IMMR;
101 bit = irq_to_siubit[irq_nr];
102 word = irq_to_siureg[irq_nr];
104 simr = &(immr->im_intctl.ic_simrh);
105 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
106 simr[word] = ppc_cached_irq_mask[word];
109 static void m8260_mask_and_ack (unsigned int irq_nr)
111 volatile immap_t *immr = (immap_t *) CFG_IMMR;
113 volatile uint *simr, *sipnr;
115 bit = irq_to_siubit[irq_nr];
116 word = irq_to_siureg[irq_nr];
118 simr = &(immr->im_intctl.ic_simrh);
119 sipnr = &(immr->im_intctl.ic_sipnrh);
120 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
121 simr[word] = ppc_cached_irq_mask[word];
122 sipnr[word] = 1 << (31 - bit);
125 static int m8260_get_irq (struct pt_regs *regs)
127 volatile immap_t *immr = (immap_t *) CFG_IMMR;
131 /* For MPC8260, read the SIVEC register and shift the bits down
132 * to get the irq number. */
133 bits = immr->im_intctl.ic_sivec;
138 /* end of code ripped out of arch/ppc/kernel/ppc8260_pic.c */
139 /****************************************************************************/
141 int interrupt_init_cpu (unsigned *decrementer_count)
143 DECLARE_GLOBAL_DATA_PTR;
145 volatile immap_t *immr = (immap_t *) CFG_IMMR;
147 *decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
149 /* Initialize the default interrupt mapping priorities */
150 immr->im_intctl.ic_sicr = 0;
151 immr->im_intctl.ic_siprr = 0x05309770;
152 immr->im_intctl.ic_scprrh = 0x05309770;
153 immr->im_intctl.ic_scprrl = 0x05309770;
155 /* disable all interrupts and clear all pending bits */
156 immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
157 immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
158 immr->im_intctl.ic_sipnrh = 0xffffffff;
159 immr->im_intctl.ic_sipnrl = 0xffffffff;
163 * ensure all external interrupt sources default to trigger on
164 * high-to-low transition (i.e. edge triggered active low)
166 immr->im_intctl.ic_siexr = -1;
172 /****************************************************************************/
175 * Handle external interrupts
177 void external_interrupt (struct pt_regs *regs)
181 irq = m8260_get_irq (regs);
183 m8260_mask_and_ack (irq);
185 enable_interrupts ();
187 if (irq_handlers[irq].handler != NULL)
188 (*irq_handlers[irq].handler) (irq_handlers[irq].arg);
190 printf ("\nBogus External Interrupt IRQ %d\n", irq);
192 * turn off the bogus interrupt, otherwise it
193 * might repeat forever
199 m8260_unmask_irq (irq);
202 /****************************************************************************/
205 * Install and free an interrupt handler.
209 irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
211 if (irq < 0 || irq >= NR_IRQS) {
212 printf ("irq_install_handler: bad irq number %d\n", irq);
216 if (irq_handlers[irq].handler != NULL)
217 printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
218 (ulong) handler, (ulong) irq_handlers[irq].handler);
220 irq_handlers[irq].handler = handler;
221 irq_handlers[irq].arg = arg;
223 m8260_unmask_irq (irq);
226 void irq_free_handler (int irq)
228 if (irq < 0 || irq >= NR_IRQS) {
229 printf ("irq_free_handler: bad irq number %d\n", irq);
233 m8260_mask_irq (irq);
235 irq_handlers[irq].handler = NULL;
236 irq_handlers[irq].arg = NULL;
239 /****************************************************************************/
241 void timer_interrupt_cpu (struct pt_regs *regs)
243 /* nothing to do here */
247 /****************************************************************************/
249 #if (CONFIG_COMMANDS & CFG_CMD_IRQ)
251 /* ripped this out of ppc4xx/interrupts.c */
253 /*******************************************************************************
255 * irqinfo - print information about PCI devices
259 do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
263 re_enable = disable_interrupts ();
265 puts ("\nInterrupt-Information:\n"
266 "Nr Routine Arg Count\n");
268 for (irq = 0; irq < 32; irq++)
269 if (irq_handlers[irq].handler != NULL)
270 printf ("%02d %08lx %08lx %ld\n", irq,
271 (ulong) irq_handlers[irq].handler,
272 (ulong) irq_handlers[irq].arg,
273 irq_handlers[irq].count);
276 enable_interrupts ();
279 #endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */