2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
37 DECLARE_GLOBAL_DATA_PTR;
41 volatile immap_t *immr;
42 ulong clock = gd->cpu_clk;
48 const struct cpu_type {
51 } cpu_type_list [] = {
59 CPU_TYPE_ENTRY(8347_TBGA_),
60 CPU_TYPE_ENTRY(8347_PBGA_),
62 CPU_TYPE_ENTRY(8358_TBGA_),
63 CPU_TYPE_ENTRY(8358_PBGA_),
70 immr = (immap_t *)CONFIG_SYS_IMMR;
74 switch (pvr & 0xffff0000) {
92 printf("Unknown core, ");
95 spridr = immr->sysconf.spridr;
97 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
98 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
100 puts(cpu_type_list[i].name);
101 if (IS_E_PROCESSOR(spridr))
103 if (REVID_MAJOR(spridr) >= 2)
105 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
106 REVID_MINOR(spridr));
110 if (i == ARRAY_SIZE(cpu_type_list))
111 printf("(SPRIDR %08x unknown), ", spridr);
113 printf(" at %s MHz, ", strmhz(buf, clock));
115 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
122 * Program a UPM with the code supplied in the table.
124 * The 'dummy' variable is used to increment the MAD. 'dummy' is
125 * supposed to be a pointer to the memory of the device being
126 * programmed by the UPM. The data in the MDR is written into
127 * memory and the MAD is incremented every time there's a write
128 * to 'dummy'. Unfortunately, the current prototype for this
129 * function doesn't allow for passing the address of this
130 * device, and changing the prototype will break a number lots
131 * of other code, so we need to use a round-about way of finding
132 * the value for 'dummy'.
134 * The value can be extracted from the base address bits of the
135 * Base Register (BR) associated with the specific UPM. To find
136 * that BR, we need to scan all 8 BRs until we find the one that
137 * has its MSEL bits matching the UPM we want. Once we know the
138 * right BR, we can extract the base address bits from it.
140 * The MxMR and the BR and OR of the chosen bank should all be
141 * configured before calling this function.
144 * upm: 0=UPMA, 1=UPMB, 2=UPMC
145 * table: Pointer to an array of values to program
146 * size: Number of elements in the array. Must be 64 or less.
148 void upmconfig (uint upm, uint *table, uint size)
150 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
151 volatile fsl_lbus_t *lbus = &immap->lbus;
152 volatile uchar *dummy = NULL;
153 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
154 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
157 /* Scan all the banks to determine the base address of the device */
158 for (i = 0; i < 8; i++) {
159 if ((lbus->bank[i].br & BR_MSEL) == msel) {
160 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
166 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
170 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
171 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
173 for (i = 0; i < size; i++) {
174 lbus->mdr = table[i];
175 __asm__ __volatile__ ("sync");
176 *dummy = 0; /* Write the value to memory and increment MAD */
177 __asm__ __volatile__ ("sync");
178 while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
181 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
187 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
190 #ifndef MPC83xx_RESET
194 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
197 /* Interrupts and MMU off */
198 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
200 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
201 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
203 /* enable Reset Control Reg */
204 immap->reset.rpr = 0x52535445;
205 __asm__ __volatile__ ("sync");
206 __asm__ __volatile__ ("isync");
208 /* confirm Reset Control Reg is enabled */
209 while(!((immap->reset.rcer) & RCER_CRE));
211 printf("Resetting the board.");
216 /* perform reset, only one bit */
217 immap->reset.rcr = RCR_SWHR;
219 #else /* ! MPC83xx_RESET */
221 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
223 /* Interrupts and MMU off */
224 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
226 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
227 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
230 * Trying to execute the next instruction at a non-existing address
231 * should cause a machine check, resulting in reset
233 addr = CONFIG_SYS_RESET_ADDRESS;
235 printf("resetting the board.");
237 ((void (*)(void)) addr) ();
238 #endif /* MPC83xx_RESET */
245 * Get timebase clock frequency (like cpu_clk in Hz)
248 unsigned long get_tbclk(void)
252 tbclk = (gd->bus_clk + 3L) / 4L;
258 #if defined(CONFIG_WATCHDOG)
259 void watchdog_reset (void)
261 int re_enable = disable_interrupts();
263 /* Reset the 83xx watchdog */
264 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
265 immr->wdt.swsrr = 0x556c;
266 immr->wdt.swsrr = 0xaa39;
269 enable_interrupts ();
273 #if defined(CONFIG_DDR_ECC)
276 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
277 volatile dma83xx_t *dma = &immap->dma;
278 volatile u32 status = swab32(dma->dmasr0);
279 volatile u32 dmamr0 = swab32(dma->dmamr0);
283 /* initialize DMASARn, DMADAR and DMAABCRn */
284 dma->dmadar0 = (u32)0;
285 dma->dmasar0 = (u32)0;
288 __asm__ __volatile__ ("sync");
289 __asm__ __volatile__ ("isync");
292 dmamr0 &= ~DMA_CHANNEL_START;
293 dma->dmamr0 = swab32(dmamr0);
294 __asm__ __volatile__ ("sync");
295 __asm__ __volatile__ ("isync");
297 /* while the channel is busy, spin */
298 while(status & DMA_CHANNEL_BUSY) {
299 status = swab32(dma->dmasr0);
302 debug("DMA-init end\n");
307 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
308 volatile dma83xx_t *dma = &immap->dma;
309 volatile u32 status = swab32(dma->dmasr0);
310 volatile u32 byte_count = swab32(dma->dmabcr0);
312 /* while the channel is busy, spin */
313 while (status & DMA_CHANNEL_BUSY) {
314 status = swab32(dma->dmasr0);
317 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
318 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
324 int dma_xfer(void *dest, u32 count, void *src)
326 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
327 volatile dma83xx_t *dma = &immap->dma;
330 /* initialize DMASARn, DMADAR and DMAABCRn */
331 dma->dmadar0 = swab32((u32)dest);
332 dma->dmasar0 = swab32((u32)src);
333 dma->dmabcr0 = swab32(count);
335 __asm__ __volatile__ ("sync");
336 __asm__ __volatile__ ("isync");
338 /* init direct transfer, clear CS bit */
339 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
340 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
341 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
343 dma->dmamr0 = swab32(dmamr0);
345 __asm__ __volatile__ ("sync");
346 __asm__ __volatile__ ("isync");
348 /* set CS to start DMA transfer */
349 dmamr0 |= DMA_CHANNEL_START;
350 dma->dmamr0 = swab32(dmamr0);
351 __asm__ __volatile__ ("sync");
352 __asm__ __volatile__ ("isync");
354 return ((int)dma_check());
356 #endif /*CONFIG_DDR_ECC*/
359 * Initializes on-chip ethernet controllers.
360 * to override, implement board_eth_init()
362 int cpu_eth_init(bd_t *bis)
364 #if defined(CONFIG_TSEC_ENET)
365 tsec_standard_init(bis);