2 * Copyright (C) Freescale Semiconductor, Inc. 2007
4 * Author: Scott Wood <scottwood@freescale.com>,
5 * with some bits from older board-specific PCI initialization.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/mpc8349_pci.h>
30 #ifdef CONFIG_83XX_GENERIC_PCI
33 DECLARE_GLOBAL_DATA_PTR;
35 static struct pci_controller pci_hose[MAX_BUSES];
36 static int pci_num_buses;
38 static void pci_init_bus(int bus, struct pci_region *reg)
40 volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
41 volatile pot83xx_t *pot = immr->ios.pot;
42 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
43 struct pci_controller *hose = &pci_hose[bus];
51 /* Setup outbound translation windows */
52 for (i = 0; i < 3; i++, reg++, pot++) {
56 hose->regions[i] = *reg;
59 pot->potar = reg->bus_start >> 12;
60 pot->pobar = reg->phys_start >> 12;
61 pot->pocmr = ~(reg->size - 1) >> 12;
63 if (reg->flags & PCI_REGION_IO)
64 pot->pocmr |= POCMR_IO;
65 #ifdef CONFIG_83XX_PCI_STREAMING
66 else if (reg->flags & PCI_REGION_PREFETCH)
67 pot->pocmr |= POCMR_SE;
71 pot->pocmr |= POCMR_DST;
73 pot->pocmr |= POCMR_EN;
76 /* Point inbound translation at RAM */
79 pci_ctrl->piebar1 = 0;
80 pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
81 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
83 i = hose->region_count++;
84 hose->regions[i].bus_start = 0;
85 hose->regions[i].phys_start = 0;
86 hose->regions[i].size = gd->ram_size;
87 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
89 hose->first_busno = 0;
90 hose->last_busno = 0xff;
92 pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80,
93 CFG_IMMR + 0x8304 + bus * 0x80);
95 pci_register_hose(hose);
98 * Write to Command register
101 dev = PCI_BDF(hose->first_busno, 0, 0);
102 pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16);
103 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
104 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
107 * Clear non-reserved bits in status register.
109 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
110 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
111 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
113 #ifdef CONFIG_PCI_SCAN_SHOW
114 printf("PCI: Bus Dev VenId DevId Class Int\n");
119 hose->last_busno = pci_hose_scan(hose);
123 * The caller must have already set OCCR, and the PCI_LAW BARs
124 * must have been set to cover all of the requested regions.
126 * If fewer than three regions are requested, then the region
127 * list is terminated with a region of size 0.
129 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
131 volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
134 if (num_buses > MAX_BUSES) {
135 printf("%d PCI buses requsted, %d supported\n",
136 num_buses, MAX_BUSES);
138 num_buses = MAX_BUSES;
141 pci_num_buses = num_buses;
144 * Release PCI RST Output signal.
145 * Power on to RST high must be at least 100 ms as per PCI spec.
146 * On warm boots only 1 ms is required.
148 udelay(warmboot ? 1000 : 100000);
150 for (i = 0; i < num_buses; i++)
151 immr->pci_ctrl[i].gcr = 1;
154 * RST high to first config access must be at least 2^25 cycles
155 * as per PCI spec. This could be cut in half if we know we're
156 * running at 66MHz. This could be insufficiently long if we're
157 * running the PCI bus at significantly less than 33MHz.
161 for (i = 0; i < num_buses; i++)
162 pci_init_bus(i, reg[i]);
165 #ifdef CONFIG_OF_FLAT_TREE
166 void ft_pci_setup(void *blob, bd_t *bd)
171 if (pci_num_buses < 1)
174 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
176 p[0] = pci_hose[0].first_busno;
177 p[1] = pci_hose[0].last_busno;
180 if (pci_num_buses < 2)
183 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
185 p[0] = pci_hose[1].first_busno;
186 p[1] = pci_hose[1].last_busno;
189 #endif /* CONFIG_OF_FLAT_TREE */
191 #endif /* CONFIG_83XX_GENERIC_PCI */