2 * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 DECLARE_GLOBAL_DATA_PTR;
46 char buf1[32], buf2[32];
47 #ifdef CONFIG_DDR_CLK_FREQ
48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
50 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
57 ver = SVR_SOC_VER(svr);
60 major &= 0x7; /* the msb of this nibble is a mfg code */
64 #if (CONFIG_NUM_CPUS > 1)
65 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
66 printf("CPU%d: ", pic->whoami);
71 cpu = identify_cpu(ver);
75 if (IS_E_PROCESSOR(svr))
81 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
91 case PVR_FAM(PVR_85xx):
99 if (PVR_MEM(pvr) == 0x03)
102 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
104 get_sys_info(&sysinfo);
106 puts("Clock Configuration:");
107 for (i = 0; i < CONFIG_NUM_CPUS; i++) {
110 printf("CPU%d:%-4s MHz, ",
111 i,strmhz(buf1, sysinfo.freqProcessor[i]));
113 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
117 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
118 strmhz(buf1, sysinfo.freqDDRBus/2),
119 strmhz(buf2, sysinfo.freqDDRBus));
122 printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
123 strmhz(buf1, sysinfo.freqDDRBus/2),
124 strmhz(buf2, sysinfo.freqDDRBus));
127 printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
128 strmhz(buf1, sysinfo.freqDDRBus/2),
129 strmhz(buf2, sysinfo.freqDDRBus));
133 if (sysinfo.freqLocalBus > LCRR_CLKDIV)
134 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
136 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
137 sysinfo.freqLocalBus);
140 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
144 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
147 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
153 /* ------------------------------------------------------------------------- */
155 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
159 unsigned long val, msr;
165 /* e500 v2 core has reset control register */
166 volatile unsigned int * rstcr;
167 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
168 *rstcr = 0x2; /* HRESET_REQ */
173 * Fallthrough if the code above failed
174 * Initiate hard reset in debug control register DBCR0
175 * Make sure MSR[DE] = 1
191 * Get timebase clock frequency
193 unsigned long get_tbclk (void)
195 return (gd->bus_clk + 4UL)/8UL;
199 #if defined(CONFIG_WATCHDOG)
203 int re_enable = disable_interrupts();
204 reset_85xx_watchdog();
205 if (re_enable) enable_interrupts();
209 reset_85xx_watchdog(void)
212 * Clear TSR(WIS) bit by writing 1
215 val = mfspr(SPRN_TSR);
217 mtspr(SPRN_TSR, val);
219 #endif /* CONFIG_WATCHDOG */
222 * Configures a UPM. The function requires the respective MxMR to be set
223 * before calling this function. "size" is the number or entries, not a sizeof.
225 void upmconfig (uint upm, uint * table, uint size)
227 int i, mdr, mad, old_mad = 0;
229 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
230 volatile u32 *brp,*orp;
231 volatile u8* dummy = NULL;
237 upmmask = BR_MS_UPMA;
241 upmmask = BR_MS_UPMB;
245 upmmask = BR_MS_UPMC;
248 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
252 /* Find the address for the dummy write transaction */
253 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
254 i++, brp += 2, orp += 2) {
256 /* Look for a valid BR with selected UPM */
257 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
258 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
264 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
268 for (i = 0; i < size; i++) {
270 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
272 out_be32(&lbc->mdr, table[i]);
274 mdr = in_be32(&lbc->mdr);
276 *(volatile u8 *)dummy = 0;
279 mad = in_be32(mxmr) & MxMR_MAD_MSK;
280 } while (mad <= old_mad && !(!mad && i == (size-1)));
283 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
287 * Initializes on-chip MMC controllers.
288 * to override, implement board_mmc_init()
290 int cpu_mmc_init(bd_t *bis)
292 #ifdef CONFIG_FSL_ESDHC
293 return fsl_esdhc_mmc_init(bis);