2 # Copyright (C) 2014, Simon Glass <sjg@chromium.org>
3 # Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
5 # SPDX-License-Identifier: GPL-2.0+
11 This document describes the information about U-Boot running on x86 targets,
12 including supported boards, build instructions, todo list, etc.
16 U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17 (Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should
18 work with minimal adjustments on other x86 boards since coreboot deals with
19 most of the low-level details.
21 U-Boot also supports booting directly from x86 reset vector without coreboot,
22 aka raw support or bare support. Currently Link, QEMU x86 targets and all
23 Intel boards support running U-Boot 'bare metal'.
25 As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
26 Linux kernel as part of a FIT image. It also supports a compressed zImage.
30 Building U-Boot as a coreboot payload is just like building U-Boot for targets
31 on other architectures, like below:
33 $ make coreboot-x86_defconfig
36 Note this default configuration will build a U-Boot payload for the QEMU board.
37 To build a coreboot payload against another board, you can change the build
38 configuration during the 'make menuconfig' process.
42 (qemu-x86) Board configuration file
43 (qemu-x86) Board Device Tree Source (dts) file
44 (0x01920000) Board specific Cache-As-RAM (CAR) address
45 (0x4000) Board specific Cache-As-RAM (CAR) size
47 Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
48 to point to a new board. You can also change the Cache-As-RAM (CAR) related
49 settings here if the default values do not fit your new board.
51 Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
52 little bit tricky, as generally it requires several binary blobs which are not
53 shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
54 not turned on by default in the U-Boot source tree. Firstly, you need turn it
55 on by enabling the ROM build:
59 This tells the Makefile to build u-boot.rom as a target.
61 Link-specific instructions:
63 First, you need the following binary blobs:
65 * descriptor.bin - Intel flash descriptor
66 * me.bin - Intel Management Engine
67 * mrc.bin - Memory Reference Code, which sets up SDRAM
68 * video ROM - sets up the display
70 You can get these binary blobs by:
72 $ git clone http://review.coreboot.org/p/blobs.git
75 Find the following files:
77 * ./mainboard/google/link/descriptor.bin
78 * ./mainboard/google/link/me.bin
79 * ./northbridge/intel/sandybridge/systemagent-r6.bin
81 The 3rd one should be renamed to mrc.bin.
82 As for the video ROM, you can get it here [3].
83 Make sure all these binary blobs are put in the board directory.
85 Now you can build U-Boot and obtain u-boot.rom:
87 $ make chromebook_link_defconfig
90 Intel Crown Bay specific instructions:
92 U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
93 Firmware Support Package [5] to perform all the necessary initialization steps
94 as documented in the BIOS Writer Guide, including initialization of the CPU,
95 memory controller, chipset and certain bus interfaces.
97 Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
98 install it on your host and locate the FSP binary blob. Note this platform
99 also requires a Chipset Micro Code (CMC) state machine binary to be present in
100 the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
101 in this FSP package too.
103 * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
104 * ./Microcode/C0_22211.BIN
106 Rename the first one to fsp.bin and second one to cmc.bin and put them in the
109 Note the FSP release version 001 has a bug which could cause random endless
110 loop during the FspInit call. This bug was published by Intel although Intel
111 did not describe any details. We need manually apply the patch to the FSP
112 binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
113 binary, change the following five bytes values from orginally E8 42 FF FF FF
116 Now you can build U-Boot and obtain u-boot.rom
118 $ make crownbay_defconfig
121 Intel Minnowboard Max instructions:
123 This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
124 Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
125 the time of writing). Put it in the board directory:
126 board/intel/minnowmax/fsp.bin
128 Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
129 directory: board/intel/minnowmax/vga.bin
131 You still need two more binary blobs. The first comes from the original
132 firmware image available from:
134 http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
138 $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
140 Use ifdtool in the U-Boot tools directory to extract the images from that
143 $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
145 This will provide the descriptor file - copy this into the correct place:
147 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
149 Then do the same with the sample SPI image provided in the FSP (SPI.bin at
150 the time of writing) to obtain the last image. Note that this will also
151 produce a flash descriptor file, but it does not seem to work, probably
152 because it is not designed for the Minnowmax. That is why you need to get
153 the flash descriptor from the original firmware as above.
155 $ ./tools/ifdtool -x BayleyBay/SPI.bin
156 $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
158 Now you can build U-Boot and obtain u-boot.rom
160 $ make minnowmax_defconfig
163 Intel Galileo instructions:
165 Only one binary blob is needed for Remote Management Unit (RMU) within Intel
166 Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
167 needed by the Quark SoC itself.
169 You can get the binary blob from Quark Board Support Package from Intel website:
171 * ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
173 Rename the file and put it to the board directory by:
175 $ cp RMU.bin board/intel/galileo/rmu.bin
177 Now you can build U-Boot and obtain u-boot.rom
179 $ make galileo_defconfig
182 QEMU x86 target instructions:
184 To build u-boot.rom for QEMU x86 targets, just simply run
186 $ make qemu-x86_defconfig
191 For testing U-Boot as the coreboot payload, there are things that need be paid
192 attention to. coreboot supports loading an ELF executable and a 32-bit plain
193 binary, as well as other supported payloads. With the default configuration,
194 U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
195 generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
196 provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
197 this capability yet. The command is as follows:
199 # in the coreboot root directory
200 $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
201 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
203 Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
204 symbol address of _start (in arch/x86/cpu/start.S).
206 If you want to use ELF as the coreboot payload, change U-Boot configuration to
207 use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
209 To enable video you must enable these options in coreboot:
211 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
212 - Keep VESA framebuffer
214 At present it seems that for Minnowboard Max, coreboot does not pass through
215 the video information correctly (it always says the resolution is 0x0). This
216 works correctly for link though.
220 QEMU is a fancy emulator that can enable us to test U-Boot without access to
221 a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
222 U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows:
224 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom
226 This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
227 also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
228 also supported by U-Boot. To instantiate such a machine, call QEMU with:
230 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
232 Note by default QEMU instantiated boards only have 128 MiB system memory. But
233 it is enough to have U-Boot boot and function correctly. You can increase the
234 system memory by pass '-m' parameter to QEMU if you want more memory:
236 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
238 This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
239 supports 3 GiB maximum system memory and reserves the last 1 GiB address space
240 for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
243 QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
244 show QEMU's VGA console window. Note this will disable QEMU's serial output.
245 If you want to check both consoles, use '-serial stdio'.
249 Modern CPUs usually require a special bit stream called microcode [6] to be
250 loaded on the processor after power up in order to function properly. U-Boot
251 has already integrated these as hex dumps in the source tree.
255 x86 has been converted to use driver model for serial and GPIO.
259 x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
260 be turned on. Not every device on the board is configured via device tree, but
261 more and more devices will be added as time goes by. Check out the directory
262 arch/x86/dts/ for these device tree source files.
266 In keeping with the U-Boot philosophy of providing functions to check and
267 adjust internal settings, there are several x86-specific commands that may be
270 hob - Display information about Firmware Support Package (FSP) Hand-off
271 Block. This is only available on platforms which use FSP, mostly
273 iod - Display I/O memory
274 iow - Write I/O memory
275 mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
276 tell the CPU whether memory is cacheable and if so the cache write
277 mode to use. U-Boot sets up some reasonable values but you can
278 adjust then with this command.
282 These notes are for those who want to port U-Boot to a new x86 platform.
284 Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
285 The Dediprog em100 can be used on Linux. The em100 tool is available here:
287 http://review.coreboot.org/p/em100.git
289 On Minnowboard Max the following command line can be used:
291 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
293 A suitable clip for connecting over the SPI flash chip is here:
295 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
297 This allows you to override the SPI flash contents for development purposes.
298 Typically you can write to the em100 in around 1200ms, considerably faster
299 than programming the real flash device each time. The only important
300 limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
301 This means that images must be set to boot with that speed. This is an
302 Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
303 speed in the SPI descriptor region.
305 If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
306 easy to fit it in. You can follow the Minnowboard Max implementation, for
307 example. Hopefully you will just need to create new files similar to those
308 in arch/x86/cpu/baytrail which provide Bay Trail support.
310 If you are not using an FSP you have more freedom and more responsibility.
311 The ivybridge support works this way, although it still uses a ROM for
312 graphics and still has binary blobs containing Intel code. You should aim to
313 support all important peripherals on your platform including video and storage.
314 Use the device tree for configuration where possible.
316 For the microcode you can create a suitable device tree file using the
319 ./tools/microcode-tool -d microcode.dat create <model>
321 or if you only have header files and not the full Intel microcode.dat database:
323 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
324 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
327 These are written to arch/x86/dts/microcode/ by default.
329 Note that it is possible to just add the micrcode for your CPU if you know its
330 model. U-Boot prints this information when it starts
332 CPU: x86_64, vendor Intel, device 30673h
334 so here we can use the M0130673322 file.
336 If you platform can display POST codes on two little 7-segment displays on
337 the board, then you can use post_code() calls from C or assembler to monitor
338 boot progress. This can be good for debugging.
340 If not, you can try to get serial working as early as possible. The early
341 debug serial port may be useful here. See setup_early_uart() for an example.
346 - Chrome OS verified boot
347 - SMI and ACPI support, to provide platform info and facilities to Linux
351 [1] http://www.coreboot.org
352 [2] http://www.qemu.org
353 [3] http://www.coreboot.org/~stepan/pci8086,0166.rom
354 [4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
355 [5] http://www.intel.com/fsp
356 [6] http://en.wikipedia.org/wiki/Microcode