1 <!-- Copyright (C) 2003 Red Hat, Inc. -->
2 <!-- This material may be distributed only subject to the terms -->
3 <!-- and conditions set forth in the Open Publication License, v1.0 -->
4 <!-- or later (the latest version is presently available at -->
5 <!-- http://www.opencontent.org/openpub/). -->
6 <!-- Distribution of the work or derivative of the work in any -->
7 <!-- standard (paper) book form is prohibited unless prior -->
8 <!-- permission is obtained from the copyright holder. -->
12 >Architecture, Variant and Platform</TITLE
13 ><meta name="MSSmartTagsPreventParsing" content="TRUE">
16 CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
19 TITLE="eCos Reference Manual"
20 HREF="ecos-ref.html"><LINK
22 TITLE="The eCos Hardware Abstraction Layer (HAL)"
23 HREF="the-ecos-hardware-abstraction-layer.html"><LINK
26 HREF="hal-introduction.html"><LINK
28 TITLE="General principles"
29 HREF="hal-general-principles.html"></HEAD
40 SUMMARY="Header navigation table"
49 >eCos Reference Manual</TH
57 HREF="hal-introduction.html"
71 HREF="hal-general-principles.html"
84 NAME="HAL-ARCHITECTURE-VARIANT-AND-PLATFORM">Chapter 7. Architecture, Variant and Platform</H1
86 >We have identified three levels at which the HAL must operate.</P
96 > abstracts the basic CPU architecture and includes
97 things like interrupt delivery, context switching, CPU startup
107 encapsulates features of the CPU variant such as caches, MMU and
108 FPU features. It also deals with any on-chip peripherals such as
109 memory and interrupt controllers. For architectural variations,
110 the actual implementation of the variation is often in the
111 architectural HAL, and the variant HAL simply provides the correct
112 configuration definitions.
121 abstracts the properties of the current platform and includes
122 things like platform startup, timer devices, I/O register access
123 and interrupt controllers.
128 >The boundaries between these three HAL levels are necessarily blurred
129 since functionality shifts between levels on a target-by-target basis.
130 For example caches and MMU may be either an architecture feature or a
131 variant feature. Similarly, memory and interrupt controllers may be
132 on-chip and in the variant HAL, or off-chip and in the platform HAL.</P
134 >Generally there is a separate package for each of the architecture,
135 variant and package HALs for a target. For some of the older targets,
136 or where it would be essentially empty, the variant HAL is omitted.</P
143 SUMMARY="Footer navigation table"
154 HREF="hal-introduction.html"
172 HREF="hal-general-principles.html"
188 HREF="the-ecos-hardware-abstraction-layer.html"
196 >General principles</TD