drivers/acpi/acpi_lpss.c

   1 /*
   2  * ACPI support for Intel Lynxpoint LPSS.
   3  *
   4  * Copyright (C) 2013, Intel Corporation
   5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
   6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/acpi.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/mutex.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/platform_data/clk-lpss.h>
  21 #include <linux/platform_data/x86/pmc_atom.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/pwm.h>
  25 #include <linux/delay.h>
  26
  27 #include "internal.h"
  28
  29 ACPI_MODULE_NAME("acpi_lpss");
  30
  31 #ifdef CONFIG_X86_INTEL_LPSS
  32
  33 #include <asm/cpu_device_id.h>
  34 #include <asm/intel-family.h>
  35 #include <asm/iosf_mbi.h>
  36
  37 #define LPSS_ADDR(desc) ((unsigned long)&desc)
  38
  39 #define LPSS_CLK_SIZE   0x04
  40 #define LPSS_LTR_SIZE   0x18
  41
  42 /* Offsets relative to LPSS_PRIVATE_OFFSET */
  43 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
  44 #define LPSS_RESETS                     0x04
  45 #define LPSS_RESETS_RESET_FUNC          BIT(0)
  46 #define LPSS_RESETS_RESET_APB           BIT(1)
  47 #define LPSS_GENERAL                    0x08
  48 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
  49 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
  50 #define LPSS_SW_LTR                     0x10
  51 #define LPSS_AUTO_LTR                   0x14
  52 #define LPSS_LTR_SNOOP_REQ              BIT(15)
  53 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
  54 #define LPSS_LTR_SNOOP_LAT_1US          0x800
  55 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
  56 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
  57 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
  58 #define LPSS_LTR_MAX_VAL                0x3FF
  59 #define LPSS_TX_INT                     0x20
  60 #define LPSS_TX_INT_MASK                BIT(1)
  61
  62 #define LPSS_PRV_REG_COUNT              9
  63
  64 /* LPSS Flags */
  65 #define LPSS_CLK                        BIT(0)
  66 #define LPSS_CLK_GATE                   BIT(1)
  67 #define LPSS_CLK_DIVIDER                BIT(2)
  68 #define LPSS_LTR                        BIT(3)
  69 #define LPSS_SAVE_CTX                   BIT(4)
  70 #define LPSS_NO_D3_DELAY                BIT(5)
  71
  72 struct lpss_private_data;
  73
  74 struct lpss_device_desc {
  75         unsigned int flags;
  76         const char *clk_con_id;
  77         unsigned int prv_offset;
  78         size_t prv_size_override;
  79         struct property_entry *properties;
  80         void (*setup)(struct lpss_private_data *pdata);
  81 };
  82
  83 static const struct lpss_device_desc lpss_dma_desc = {
  84         .flags = LPSS_CLK,
  85 };
  86
  87 struct lpss_private_data {
  88         void __iomem *mmio_base;
  89         resource_size_t mmio_size;
  90         unsigned int fixed_clk_rate;
  91         struct clk *clk;
  92         const struct lpss_device_desc *dev_desc;
  93         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
  94 };
  95
  96 /* LPSS run time quirks */
  97 static unsigned int lpss_quirks;
  98
  99 /*
 100  * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
 101  *
 102  * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
 103  * it can be powered off automatically whenever the last LPSS device goes down.
 104  * In case of no power any access to the DMA controller will hang the system.
 105  * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
 106  * well as on ASuS T100TA transformer.
 107  *
 108  * This quirk overrides power state of entire LPSS island to keep DMA powered
 109  * on whenever we have at least one other device in use.
 110  */
 111 #define LPSS_QUIRK_ALWAYS_POWER_ON      BIT(0)
 112
 113 /* UART Component Parameter Register */
 114 #define LPSS_UART_CPR                   0xF4
 115 #define LPSS_UART_CPR_AFCE              BIT(4)
 116
 117 static void lpss_uart_setup(struct lpss_private_data *pdata)
 118 {
 119         unsigned int offset;
 120         u32 val;
 121
 122         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
 123         val = readl(pdata->mmio_base + offset);
 124         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
 125
 126         val = readl(pdata->mmio_base + LPSS_UART_CPR);
 127         if (!(val & LPSS_UART_CPR_AFCE)) {
 128                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
 129                 val = readl(pdata->mmio_base + offset);
 130                 val |= LPSS_GENERAL_UART_RTS_OVRD;
 131                 writel(val, pdata->mmio_base + offset);
 132         }
 133 }
 134
 135 static void lpss_deassert_reset(struct lpss_private_data *pdata)
 136 {
 137         unsigned int offset;
 138         u32 val;
 139
 140         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
 141         val = readl(pdata->mmio_base + offset);
 142         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
 143         writel(val, pdata->mmio_base + offset);
 144 }
 145
 146 #define LPSS_I2C_ENABLE                 0x6c
 147
 148 static void byt_i2c_setup(struct lpss_private_data *pdata)
 149 {
 150         lpss_deassert_reset(pdata);
 151
 152         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
 153                 pdata->fixed_clk_rate = 133000000;
 154
 155         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
 156 }
 157
 158 /* BSW PWM used for backlight control by the i915 driver */
 159 static struct pwm_lookup bsw_pwm_lookup[] = {
 160         PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0",
 161                                "pwm_backlight", 0, PWM_POLARITY_NORMAL,
 162                                "pwm-lpss-platform"),
 163 };
 164
 165 static void bsw_pwm_setup(struct lpss_private_data *pdata)
 166 {
 167         pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup));
 168 }
 169
 170 static const struct lpss_device_desc lpt_dev_desc = {
 171         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 172         .prv_offset = 0x800,
 173 };
 174
 175 static const struct lpss_device_desc lpt_i2c_dev_desc = {
 176         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
 177         .prv_offset = 0x800,
 178 };
 179
 180 static struct property_entry uart_properties[] = {
 181         PROPERTY_ENTRY_U32("reg-io-width", 4),
 182         PROPERTY_ENTRY_U32("reg-shift", 2),
 183         PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
 184         { },
 185 };
 186
 187 static const struct lpss_device_desc lpt_uart_dev_desc = {
 188         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
 189         .clk_con_id = "baudclk",
 190         .prv_offset = 0x800,
 191         .setup = lpss_uart_setup,
 192         .properties = uart_properties,
 193 };
 194
 195 static const struct lpss_device_desc lpt_sdio_dev_desc = {
 196         .flags = LPSS_LTR,
 197         .prv_offset = 0x1000,
 198         .prv_size_override = 0x1018,
 199 };
 200
 201 static const struct lpss_device_desc byt_pwm_dev_desc = {
 202         .flags = LPSS_SAVE_CTX,
 203 };
 204
 205 static const struct lpss_device_desc bsw_pwm_dev_desc = {
 206         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 207         .setup = bsw_pwm_setup,
 208 };
 209
 210 static const struct lpss_device_desc byt_uart_dev_desc = {
 211         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 212         .clk_con_id = "baudclk",
 213         .prv_offset = 0x800,
 214         .setup = lpss_uart_setup,
 215         .properties = uart_properties,
 216 };
 217
 218 static const struct lpss_device_desc bsw_uart_dev_desc = {
 219         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 220                         | LPSS_NO_D3_DELAY,
 221         .clk_con_id = "baudclk",
 222         .prv_offset = 0x800,
 223         .setup = lpss_uart_setup,
 224         .properties = uart_properties,
 225 };
 226
 227 static const struct lpss_device_desc byt_spi_dev_desc = {
 228         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
 229         .prv_offset = 0x400,
 230 };
 231
 232 static const struct lpss_device_desc byt_sdio_dev_desc = {
 233         .flags = LPSS_CLK,
 234 };
 235
 236 static const struct lpss_device_desc byt_i2c_dev_desc = {
 237         .flags = LPSS_CLK | LPSS_SAVE_CTX,
 238         .prv_offset = 0x800,
 239         .setup = byt_i2c_setup,
 240 };
 241
 242 static const struct lpss_device_desc bsw_i2c_dev_desc = {
 243         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
 244         .prv_offset = 0x800,
 245         .setup = byt_i2c_setup,
 246 };
 247
 248 static const struct lpss_device_desc bsw_spi_dev_desc = {
 249         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
 250                         | LPSS_NO_D3_DELAY,
 251         .prv_offset = 0x400,
 252         .setup = lpss_deassert_reset,
 253 };
 254
 255 #define ICPU(model)     { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 256
 257 static const struct x86_cpu_id lpss_cpu_ids[] = {
 258         ICPU(INTEL_FAM6_ATOM_SILVERMONT1),      /* Valleyview, Bay Trail */
 259         ICPU(INTEL_FAM6_ATOM_AIRMONT),  /* Braswell, Cherry Trail */
 260         {}
 261 };
 262
 263 #else
 264
 265 #define LPSS_ADDR(desc) (0UL)
 266
 267 #endif /* CONFIG_X86_INTEL_LPSS */
 268
 269 static const struct acpi_device_id acpi_lpss_device_ids[] = {
 270         /* Generic LPSS devices */
 271         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
 272
 273         /* Lynxpoint LPSS devices */
 274         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
 275         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
 276         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
 277         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
 278         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
 279         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
 280         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
 281         { "INT33C7", },
 282
 283         /* BayTrail LPSS devices */
 284         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
 285         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
 286         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
 287         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
 288         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
 289         { "INT33B2", },
 290         { "INT33FC", },
 291
 292         /* Braswell LPSS devices */
 293         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
 294         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
 295         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
 296         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
 297
 298         /* Broadwell LPSS devices */
 299         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
 300         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
 301         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
 302         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
 303         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
 304         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
 305         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
 306         { "INT3437", },
 307
 308         /* Wildcat Point LPSS devices */
 309         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
 310
 311         { }
 312 };
 313
 314 #ifdef CONFIG_X86_INTEL_LPSS
 315
 316 static int is_memory(struct acpi_resource *res, void *not_used)
 317 {
 318         struct resource r;
 319         return !acpi_dev_resource_memory(res, &r);
 320 }
 321
 322 /* LPSS main clock device. */
 323 static struct platform_device *lpss_clk_dev;
 324
 325 static inline void lpt_register_clock_device(void)
 326 {
 327         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
 328 }
 329
 330 static int register_device_clock(struct acpi_device *adev,
 331                                  struct lpss_private_data *pdata)
 332 {
 333         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
 334         const char *devname = dev_name(&adev->dev);
 335         struct clk *clk = ERR_PTR(-ENODEV);
 336         struct lpss_clk_data *clk_data;
 337         const char *parent, *clk_name;
 338         void __iomem *prv_base;
 339
 340         if (!lpss_clk_dev)
 341                 lpt_register_clock_device();
 342
 343         clk_data = platform_get_drvdata(lpss_clk_dev);
 344         if (!clk_data)
 345                 return -ENODEV;
 346         clk = clk_data->clk;
 347
 348         if (!pdata->mmio_base
 349             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
 350                 return -ENODATA;
 351
 352         parent = clk_data->name;
 353         prv_base = pdata->mmio_base + dev_desc->prv_offset;
 354
 355         if (pdata->fixed_clk_rate) {
 356                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
 357                                               pdata->fixed_clk_rate);
 358                 goto out;
 359         }
 360
 361         if (dev_desc->flags & LPSS_CLK_GATE) {
 362                 clk = clk_register_gate(NULL, devname, parent, 0,
 363                                         prv_base, 0, 0, NULL);
 364                 parent = devname;
 365         }
 366
 367         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
 368                 /* Prevent division by zero */
 369                 if (!readl(prv_base))
 370                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
 371
 372                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
 373                 if (!clk_name)
 374                         return -ENOMEM;
 375                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
 376                                                       0, prv_base,
 377                                                       1, 15, 16, 15, 0, NULL);
 378                 parent = clk_name;
 379
 380                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
 381                 if (!clk_name) {
 382                         kfree(parent);
 383                         return -ENOMEM;
 384                 }
 385                 clk = clk_register_gate(NULL, clk_name, parent,
 386                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
 387                                         prv_base, 31, 0, NULL);
 388                 kfree(parent);
 389                 kfree(clk_name);
 390         }
 391 out:
 392         if (IS_ERR(clk))
 393                 return PTR_ERR(clk);
 394
 395         pdata->clk = clk;
 396         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
 397         return 0;
 398 }
 399
 400 static int acpi_lpss_create_device(struct acpi_device *adev,
 401                                    const struct acpi_device_id *id)
 402 {
 403         const struct lpss_device_desc *dev_desc;
 404         struct lpss_private_data *pdata;
 405         struct resource_entry *rentry;
 406         struct list_head resource_list;
 407         struct platform_device *pdev;
 408         int ret;
 409
 410         dev_desc = (const struct lpss_device_desc *)id->driver_data;
 411         if (!dev_desc) {
 412                 pdev = acpi_create_platform_device(adev, NULL);
 413                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
 414         }
 415         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 416         if (!pdata)
 417                 return -ENOMEM;
 418
 419         INIT_LIST_HEAD(&resource_list);
 420         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
 421         if (ret < 0)
 422                 goto err_out;
 423
 424         list_for_each_entry(rentry, &resource_list, node)
 425                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
 426                         if (dev_desc->prv_size_override)
 427                                 pdata->mmio_size = dev_desc->prv_size_override;
 428                         else
 429                                 pdata->mmio_size = resource_size(rentry->res);
 430                         pdata->mmio_base = ioremap(rentry->res->start,
 431                                                    pdata->mmio_size);
 432                         break;
 433                 }
 434
 435         acpi_dev_free_resource_list(&resource_list);
 436
 437         if (!pdata->mmio_base) {
 438                 ret = -ENOMEM;
 439                 goto err_out;
 440         }
 441
 442         pdata->dev_desc = dev_desc;
 443
 444         if (dev_desc->setup)
 445                 dev_desc->setup(pdata);
 446
 447         if (dev_desc->flags & LPSS_CLK) {
 448                 ret = register_device_clock(adev, pdata);
 449                 if (ret) {
 450                         /* Skip the device, but continue the namespace scan. */
 451                         ret = 0;
 452                         goto err_out;
 453                 }
 454         }
 455
 456         /*
 457          * This works around a known issue in ACPI tables where LPSS devices
 458          * have _PS0 and _PS3 without _PSC (and no power resources), so
 459          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
 460          */
 461         ret = acpi_device_fix_up_power(adev);
 462         if (ret) {
 463                 /* Skip the device, but continue the namespace scan. */
 464                 ret = 0;
 465                 goto err_out;
 466         }
 467
 468         adev->driver_data = pdata;
 469         pdev = acpi_create_platform_device(adev, dev_desc->properties);
 470         if (!IS_ERR_OR_NULL(pdev)) {
 471                 return 1;
 472         }
 473
 474         ret = PTR_ERR(pdev);
 475         adev->driver_data = NULL;
 476
 477  err_out:
 478         kfree(pdata);
 479         return ret;
 480 }
 481
 482 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
 483 {
 484         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 485 }
 486
 487 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
 488                              unsigned int reg)
 489 {
 490         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
 491 }
 492
 493 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
 494 {
 495         struct acpi_device *adev;
 496         struct lpss_private_data *pdata;
 497         unsigned long flags;
 498         int ret;
 499
 500         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
 501         if (WARN_ON(ret))
 502                 return ret;
 503
 504         spin_lock_irqsave(&dev->power.lock, flags);
 505         if (pm_runtime_suspended(dev)) {
 506                 ret = -EAGAIN;
 507                 goto out;
 508         }
 509         pdata = acpi_driver_data(adev);
 510         if (WARN_ON(!pdata || !pdata->mmio_base)) {
 511                 ret = -ENODEV;
 512                 goto out;
 513         }
 514         *val = __lpss_reg_read(pdata, reg);
 515
 516  out:
 517         spin_unlock_irqrestore(&dev->power.lock, flags);
 518         return ret;
 519 }
 520
 521 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
 522                              char *buf)
 523 {
 524         u32 ltr_value = 0;
 525         unsigned int reg;
 526         int ret;
 527
 528         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
 529         ret = lpss_reg_read(dev, reg, &ltr_value);
 530         if (ret)
 531                 return ret;
 532
 533         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
 534 }
 535
 536 static ssize_t lpss_ltr_mode_show(struct device *dev,
 537                                   struct device_attribute *attr, char *buf)
 538 {
 539         u32 ltr_mode = 0;
 540         char *outstr;
 541         int ret;
 542
 543         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
 544         if (ret)
 545                 return ret;
 546
 547         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
 548         return sprintf(buf, "%s\n", outstr);
 549 }
 550
 551 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
 552 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
 553 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
 554
 555 static struct attribute *lpss_attrs[] = {
 556         &dev_attr_auto_ltr.attr,
 557         &dev_attr_sw_ltr.attr,
 558         &dev_attr_ltr_mode.attr,
 559         NULL,
 560 };
 561
 562 static struct attribute_group lpss_attr_group = {
 563         .attrs = lpss_attrs,
 564         .name = "lpss_ltr",
 565 };
 566
 567 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
 568 {
 569         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 570         u32 ltr_mode, ltr_val;
 571
 572         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
 573         if (val < 0) {
 574                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
 575                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
 576                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 577                 }
 578                 return;
 579         }
 580         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
 581         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
 582                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
 583                 val = LPSS_LTR_MAX_VAL;
 584         } else if (val > LPSS_LTR_MAX_VAL) {
 585                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
 586                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
 587         } else {
 588                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
 589         }
 590         ltr_val |= val;
 591         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
 592         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
 593                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
 594                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
 595         }
 596 }
 597
 598 #ifdef CONFIG_PM
 599 /**
 600  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
 601  * @dev: LPSS device
 602  * @pdata: pointer to the private data of the LPSS device
 603  *
 604  * Most LPSS devices have private registers which may loose their context when
 605  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
 606  * prv_reg_ctx array.
 607  */
 608 static void acpi_lpss_save_ctx(struct device *dev,
 609                                struct lpss_private_data *pdata)
 610 {
 611         unsigned int i;
 612
 613         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 614                 unsigned long offset = i * sizeof(u32);
 615
 616                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
 617                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
 618                         pdata->prv_reg_ctx[i], offset);
 619         }
 620 }
 621
 622 /**
 623  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
 624  * @dev: LPSS device
 625  * @pdata: pointer to the private data of the LPSS device
 626  *
 627  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
 628  */
 629 static void acpi_lpss_restore_ctx(struct device *dev,
 630                                   struct lpss_private_data *pdata)
 631 {
 632         unsigned int i;
 633
 634         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
 635                 unsigned long offset = i * sizeof(u32);
 636
 637                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
 638                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
 639                         pdata->prv_reg_ctx[i], offset);
 640         }
 641 }
 642
 643 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
 644 {
 645         /*
 646          * The following delay is needed or the subsequent write operations may
 647          * fail. The LPSS devices are actually PCI devices and the PCI spec
 648          * expects 10ms delay before the device can be accessed after D3 to D0
 649          * transition. However some platforms like BSW does not need this delay.
 650          */
 651         unsigned int delay = 10;        /* default 10ms delay */
 652
 653         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
 654                 delay = 0;
 655
 656         msleep(delay);
 657 }
 658
 659 static int acpi_lpss_activate(struct device *dev)
 660 {
 661         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 662         int ret;
 663
 664         ret = acpi_dev_runtime_resume(dev);
 665         if (ret)
 666                 return ret;
 667
 668         acpi_lpss_d3_to_d0_delay(pdata);
 669
 670         /*
 671          * This is called only on ->probe() stage where a device is either in
 672          * known state defined by BIOS or most likely powered off. Due to this
 673          * we have to deassert reset line to be sure that ->probe() will
 674          * recognize the device.
 675          */
 676         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 677                 lpss_deassert_reset(pdata);
 678
 679         return 0;
 680 }
 681
 682 static void acpi_lpss_dismiss(struct device *dev)
 683 {
 684         acpi_dev_runtime_suspend(dev);
 685 }
 686
 687 #ifdef CONFIG_PM_SLEEP
 688 static int acpi_lpss_suspend_late(struct device *dev)
 689 {
 690         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 691         int ret;
 692
 693         ret = pm_generic_suspend_late(dev);
 694         if (ret)
 695                 return ret;
 696
 697         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 698                 acpi_lpss_save_ctx(dev, pdata);
 699
 700         return acpi_dev_suspend_late(dev);
 701 }
 702
 703 static int acpi_lpss_resume_early(struct device *dev)
 704 {
 705         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 706         int ret;
 707
 708         ret = acpi_dev_resume_early(dev);
 709         if (ret)
 710                 return ret;
 711
 712         acpi_lpss_d3_to_d0_delay(pdata);
 713
 714         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 715                 acpi_lpss_restore_ctx(dev, pdata);
 716
 717         return pm_generic_resume_early(dev);
 718 }
 719 #endif /* CONFIG_PM_SLEEP */
 720
 721 /* IOSF SB for LPSS island */
 722 #define LPSS_IOSF_UNIT_LPIOEP           0xA0
 723 #define LPSS_IOSF_UNIT_LPIO1            0xAB
 724 #define LPSS_IOSF_UNIT_LPIO2            0xAC
 725
 726 #define LPSS_IOSF_PMCSR                 0x84
 727 #define LPSS_PMCSR_D0                   0
 728 #define LPSS_PMCSR_D3hot                3
 729 #define LPSS_PMCSR_Dx_MASK              GENMASK(1, 0)
 730
 731 #define LPSS_IOSF_GPIODEF0              0x154
 732 #define LPSS_GPIODEF0_DMA1_D3           BIT(2)
 733 #define LPSS_GPIODEF0_DMA2_D3           BIT(3)
 734 #define LPSS_GPIODEF0_DMA_D3_MASK       GENMASK(3, 2)
 735 #define LPSS_GPIODEF0_DMA_LLP           BIT(13)
 736
 737 static DEFINE_MUTEX(lpss_iosf_mutex);
 738
 739 static void lpss_iosf_enter_d3_state(void)
 740 {
 741         u32 value1 = 0;
 742         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 743         u32 value2 = LPSS_PMCSR_D3hot;
 744         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 745         /*
 746          * PMC provides an information about actual status of the LPSS devices.
 747          * Here we read the values related to LPSS power island, i.e. LPSS
 748          * devices, excluding both LPSS DMA controllers, along with SCC domain.
 749          */
 750         u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe;
 751         int ret;
 752
 753         ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
 754         if (ret)
 755                 return;
 756
 757         mutex_lock(&lpss_iosf_mutex);
 758
 759         ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
 760         if (ret)
 761                 goto exit;
 762
 763         /*
 764          * Get the status of entire LPSS power island per device basis.
 765          * Shutdown both LPSS DMA controllers if and only if all other devices
 766          * are already in D3hot.
 767          */
 768         pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask;
 769         if (pmc_status)
 770                 goto exit;
 771
 772         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 773                         LPSS_IOSF_PMCSR, value2, mask2);
 774
 775         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 776                         LPSS_IOSF_PMCSR, value2, mask2);
 777
 778         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 779                         LPSS_IOSF_GPIODEF0, value1, mask1);
 780 exit:
 781         mutex_unlock(&lpss_iosf_mutex);
 782 }
 783
 784 static void lpss_iosf_exit_d3_state(void)
 785 {
 786         u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 |
 787                      LPSS_GPIODEF0_DMA_LLP;
 788         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP;
 789         u32 value2 = LPSS_PMCSR_D0;
 790         u32 mask2 = LPSS_PMCSR_Dx_MASK;
 791
 792         mutex_lock(&lpss_iosf_mutex);
 793
 794         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
 795                         LPSS_IOSF_GPIODEF0, value1, mask1);
 796
 797         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
 798                         LPSS_IOSF_PMCSR, value2, mask2);
 799
 800         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
 801                         LPSS_IOSF_PMCSR, value2, mask2);
 802
 803         mutex_unlock(&lpss_iosf_mutex);
 804 }
 805
 806 static int acpi_lpss_runtime_suspend(struct device *dev)
 807 {
 808         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 809         int ret;
 810
 811         ret = pm_generic_runtime_suspend(dev);
 812         if (ret)
 813                 return ret;
 814
 815         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 816                 acpi_lpss_save_ctx(dev, pdata);
 817
 818         ret = acpi_dev_runtime_suspend(dev);
 819
 820         /*
 821          * This call must be last in the sequence, otherwise PMC will return
 822          * wrong status for devices being about to be powered off. See
 823          * lpss_iosf_enter_d3_state() for further information.
 824          */
 825         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
 826                 lpss_iosf_enter_d3_state();
 827
 828         return ret;
 829 }
 830
 831 static int acpi_lpss_runtime_resume(struct device *dev)
 832 {
 833         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 834         int ret;
 835
 836         /*
 837          * This call is kept first to be in symmetry with
 838          * acpi_lpss_runtime_suspend() one.
 839          */
 840         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
 841                 lpss_iosf_exit_d3_state();
 842
 843         ret = acpi_dev_runtime_resume(dev);
 844         if (ret)
 845                 return ret;
 846
 847         acpi_lpss_d3_to_d0_delay(pdata);
 848
 849         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
 850                 acpi_lpss_restore_ctx(dev, pdata);
 851
 852         return pm_generic_runtime_resume(dev);
 853 }
 854 #endif /* CONFIG_PM */
 855
 856 static struct dev_pm_domain acpi_lpss_pm_domain = {
 857 #ifdef CONFIG_PM
 858         .activate = acpi_lpss_activate,
 859         .dismiss = acpi_lpss_dismiss,
 860 #endif
 861         .ops = {
 862 #ifdef CONFIG_PM
 863 #ifdef CONFIG_PM_SLEEP
 864                 .prepare = acpi_subsys_prepare,
 865                 .complete = pm_complete_with_resume_check,
 866                 .suspend = acpi_subsys_suspend,
 867                 .suspend_late = acpi_lpss_suspend_late,
 868                 .resume_early = acpi_lpss_resume_early,
 869                 .freeze = acpi_subsys_freeze,
 870                 .poweroff = acpi_subsys_suspend,
 871                 .poweroff_late = acpi_lpss_suspend_late,
 872                 .restore_early = acpi_lpss_resume_early,
 873 #endif
 874                 .runtime_suspend = acpi_lpss_runtime_suspend,
 875                 .runtime_resume = acpi_lpss_runtime_resume,
 876 #endif
 877         },
 878 };
 879
 880 static int acpi_lpss_platform_notify(struct notifier_block *nb,
 881                                      unsigned long action, void *data)
 882 {
 883         struct platform_device *pdev = to_platform_device(data);
 884         struct lpss_private_data *pdata;
 885         struct acpi_device *adev;
 886         const struct acpi_device_id *id;
 887
 888         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
 889         if (!id || !id->driver_data)
 890                 return 0;
 891
 892         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
 893                 return 0;
 894
 895         pdata = acpi_driver_data(adev);
 896         if (!pdata)
 897                 return 0;
 898
 899         if (pdata->mmio_base &&
 900             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
 901                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
 902                 return 0;
 903         }
 904
 905         switch (action) {
 906         case BUS_NOTIFY_BIND_DRIVER:
 907                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
 908                 break;
 909         case BUS_NOTIFY_DRIVER_NOT_BOUND:
 910         case BUS_NOTIFY_UNBOUND_DRIVER:
 911                 dev_pm_domain_set(&pdev->dev, NULL);
 912                 break;
 913         case BUS_NOTIFY_ADD_DEVICE:
 914                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
 915                 if (pdata->dev_desc->flags & LPSS_LTR)
 916                         return sysfs_create_group(&pdev->dev.kobj,
 917                                                   &lpss_attr_group);
 918                 break;
 919         case BUS_NOTIFY_DEL_DEVICE:
 920                 if (pdata->dev_desc->flags & LPSS_LTR)
 921                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
 922                 dev_pm_domain_set(&pdev->dev, NULL);
 923                 break;
 924         default:
 925                 break;
 926         }
 927
 928         return 0;
 929 }
 930
 931 static struct notifier_block acpi_lpss_nb = {
 932         .notifier_call = acpi_lpss_platform_notify,
 933 };
 934
 935 static void acpi_lpss_bind(struct device *dev)
 936 {
 937         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
 938
 939         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
 940                 return;
 941
 942         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
 943                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
 944         else
 945                 dev_err(dev, "MMIO size insufficient to access LTR\n");
 946 }
 947
 948 static void acpi_lpss_unbind(struct device *dev)
 949 {
 950         dev->power.set_latency_tolerance = NULL;
 951 }
 952
 953 static struct acpi_scan_handler lpss_handler = {
 954         .ids = acpi_lpss_device_ids,
 955         .attach = acpi_lpss_create_device,
 956         .bind = acpi_lpss_bind,
 957         .unbind = acpi_lpss_unbind,
 958 };
 959
 960 void __init acpi_lpss_init(void)
 961 {
 962         const struct x86_cpu_id *id;
 963         int ret;
 964
 965         ret = lpt_clk_init();
 966         if (ret)
 967                 return;
 968
 969         id = x86_match_cpu(lpss_cpu_ids);
 970         if (id)
 971                 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
 972
 973         bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
 974         acpi_scan_add_handler(&lpss_handler);
 975 }
 976
 977 #else
 978
 979 static struct acpi_scan_handler lpss_handler = {
 980         .ids = acpi_lpss_device_ids,
 981 };
 982
 983 void __init acpi_lpss_init(void)
 984 {
 985         acpi_scan_add_handler(&lpss_handler);
 986 }
 987
 988 #endif /* CONFIG_X86_INTEL_LPSS */