2 * ACPI support for Intel Lynxpoint LPSS.
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/acpi.h>
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/clk-provider.h>
17 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/platform_data/clk-lpss.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/delay.h>
26 ACPI_MODULE_NAME("acpi_lpss");
28 #ifdef CONFIG_X86_INTEL_LPSS
30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
32 #define LPSS_CLK_SIZE 0x04
33 #define LPSS_LTR_SIZE 0x18
35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
36 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
37 #define LPSS_RESETS 0x04
38 #define LPSS_RESETS_RESET_FUNC BIT(0)
39 #define LPSS_RESETS_RESET_APB BIT(1)
40 #define LPSS_GENERAL 0x08
41 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
42 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
43 #define LPSS_SW_LTR 0x10
44 #define LPSS_AUTO_LTR 0x14
45 #define LPSS_LTR_SNOOP_REQ BIT(15)
46 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
47 #define LPSS_LTR_SNOOP_LAT_1US 0x800
48 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
49 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
50 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
51 #define LPSS_LTR_MAX_VAL 0x3FF
52 #define LPSS_TX_INT 0x20
53 #define LPSS_TX_INT_MASK BIT(1)
55 #define LPSS_PRV_REG_COUNT 9
58 #define LPSS_CLK BIT(0)
59 #define LPSS_CLK_GATE BIT(1)
60 #define LPSS_CLK_DIVIDER BIT(2)
61 #define LPSS_LTR BIT(3)
62 #define LPSS_SAVE_CTX BIT(4)
64 struct lpss_private_data;
66 struct lpss_device_desc {
68 unsigned int prv_offset;
69 size_t prv_size_override;
70 void (*setup)(struct lpss_private_data *pdata);
73 static struct lpss_device_desc lpss_dma_desc = {
77 struct lpss_private_data {
78 void __iomem *mmio_base;
79 resource_size_t mmio_size;
80 unsigned int fixed_clk_rate;
82 const struct lpss_device_desc *dev_desc;
83 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
86 /* UART Component Parameter Register */
87 #define LPSS_UART_CPR 0xF4
88 #define LPSS_UART_CPR_AFCE BIT(4)
90 static void lpss_uart_setup(struct lpss_private_data *pdata)
95 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
96 val = readl(pdata->mmio_base + offset);
97 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
99 val = readl(pdata->mmio_base + LPSS_UART_CPR);
100 if (!(val & LPSS_UART_CPR_AFCE)) {
101 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
102 val = readl(pdata->mmio_base + offset);
103 val |= LPSS_GENERAL_UART_RTS_OVRD;
104 writel(val, pdata->mmio_base + offset);
108 static void byt_i2c_setup(struct lpss_private_data *pdata)
113 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
114 val = readl(pdata->mmio_base + offset);
115 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
116 writel(val, pdata->mmio_base + offset);
118 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
119 pdata->fixed_clk_rate = 133000000;
122 static struct lpss_device_desc lpt_dev_desc = {
123 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
127 static struct lpss_device_desc lpt_i2c_dev_desc = {
128 .flags = LPSS_CLK | LPSS_LTR,
132 static struct lpss_device_desc lpt_uart_dev_desc = {
133 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
135 .setup = lpss_uart_setup,
138 static struct lpss_device_desc lpt_sdio_dev_desc = {
140 .prv_offset = 0x1000,
141 .prv_size_override = 0x1018,
144 static struct lpss_device_desc byt_pwm_dev_desc = {
145 .flags = LPSS_SAVE_CTX,
148 static struct lpss_device_desc byt_uart_dev_desc = {
149 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
151 .setup = lpss_uart_setup,
154 static struct lpss_device_desc byt_spi_dev_desc = {
155 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
159 static struct lpss_device_desc byt_sdio_dev_desc = {
163 static struct lpss_device_desc byt_i2c_dev_desc = {
164 .flags = LPSS_CLK | LPSS_SAVE_CTX,
166 .setup = byt_i2c_setup,
171 #define LPSS_ADDR(desc) (0UL)
173 #endif /* CONFIG_X86_INTEL_LPSS */
175 static const struct acpi_device_id acpi_lpss_device_ids[] = {
176 /* Generic LPSS devices */
177 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
179 /* Lynxpoint LPSS devices */
180 { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
181 { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
182 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
183 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
184 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
185 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
186 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
189 /* BayTrail LPSS devices */
190 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
191 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
192 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
193 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
194 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
198 /* Braswell LPSS devices */
199 { "80862288", LPSS_ADDR(byt_pwm_dev_desc) },
200 { "8086228A", LPSS_ADDR(byt_uart_dev_desc) },
201 { "8086228E", LPSS_ADDR(byt_spi_dev_desc) },
202 { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) },
204 { "INT3430", LPSS_ADDR(lpt_dev_desc) },
205 { "INT3431", LPSS_ADDR(lpt_dev_desc) },
206 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
207 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
208 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
209 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
210 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
213 /* Wildcat Point LPSS devices */
214 { "INT3438", LPSS_ADDR(lpt_dev_desc) },
219 #ifdef CONFIG_X86_INTEL_LPSS
221 static int is_memory(struct acpi_resource *res, void *not_used)
224 return !acpi_dev_resource_memory(res, &r);
227 /* LPSS main clock device. */
228 static struct platform_device *lpss_clk_dev;
230 static inline void lpt_register_clock_device(void)
232 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
235 static int register_device_clock(struct acpi_device *adev,
236 struct lpss_private_data *pdata)
238 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
239 const char *devname = dev_name(&adev->dev);
240 struct clk *clk = ERR_PTR(-ENODEV);
241 struct lpss_clk_data *clk_data;
242 const char *parent, *clk_name;
243 void __iomem *prv_base;
246 lpt_register_clock_device();
248 clk_data = platform_get_drvdata(lpss_clk_dev);
253 if (!pdata->mmio_base
254 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
257 parent = clk_data->name;
258 prv_base = pdata->mmio_base + dev_desc->prv_offset;
260 if (pdata->fixed_clk_rate) {
261 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
262 pdata->fixed_clk_rate);
266 if (dev_desc->flags & LPSS_CLK_GATE) {
267 clk = clk_register_gate(NULL, devname, parent, 0,
268 prv_base, 0, 0, NULL);
272 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
273 /* Prevent division by zero */
274 if (!readl(prv_base))
275 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
277 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
280 clk = clk_register_fractional_divider(NULL, clk_name, parent,
282 1, 15, 16, 15, 0, NULL);
285 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
290 clk = clk_register_gate(NULL, clk_name, parent,
291 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
292 prv_base, 31, 0, NULL);
301 clk_register_clkdev(clk, NULL, devname);
305 static int acpi_lpss_create_device(struct acpi_device *adev,
306 const struct acpi_device_id *id)
308 struct lpss_device_desc *dev_desc;
309 struct lpss_private_data *pdata;
310 struct resource_entry *rentry;
311 struct list_head resource_list;
312 struct platform_device *pdev;
315 dev_desc = (struct lpss_device_desc *)id->driver_data;
317 pdev = acpi_create_platform_device(adev);
318 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
320 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
324 INIT_LIST_HEAD(&resource_list);
325 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
329 list_for_each_entry(rentry, &resource_list, node)
330 if (resource_type(rentry->res) == IORESOURCE_MEM) {
331 if (dev_desc->prv_size_override)
332 pdata->mmio_size = dev_desc->prv_size_override;
334 pdata->mmio_size = resource_size(rentry->res);
335 pdata->mmio_base = ioremap(rentry->res->start,
337 if (!pdata->mmio_base)
342 acpi_dev_free_resource_list(&resource_list);
344 pdata->dev_desc = dev_desc;
347 dev_desc->setup(pdata);
349 if (dev_desc->flags & LPSS_CLK) {
350 ret = register_device_clock(adev, pdata);
352 /* Skip the device, but continue the namespace scan. */
359 * This works around a known issue in ACPI tables where LPSS devices
360 * have _PS0 and _PS3 without _PSC (and no power resources), so
361 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
363 ret = acpi_device_fix_up_power(adev);
365 /* Skip the device, but continue the namespace scan. */
370 adev->driver_data = pdata;
371 pdev = acpi_create_platform_device(adev);
372 if (!IS_ERR_OR_NULL(pdev)) {
377 adev->driver_data = NULL;
384 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
386 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
389 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
392 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
395 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
397 struct acpi_device *adev;
398 struct lpss_private_data *pdata;
402 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
406 spin_lock_irqsave(&dev->power.lock, flags);
407 if (pm_runtime_suspended(dev)) {
411 pdata = acpi_driver_data(adev);
412 if (WARN_ON(!pdata || !pdata->mmio_base)) {
416 *val = __lpss_reg_read(pdata, reg);
419 spin_unlock_irqrestore(&dev->power.lock, flags);
423 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
430 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
431 ret = lpss_reg_read(dev, reg, <r_value);
435 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
438 static ssize_t lpss_ltr_mode_show(struct device *dev,
439 struct device_attribute *attr, char *buf)
445 ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode);
449 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
450 return sprintf(buf, "%s\n", outstr);
453 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
454 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
455 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
457 static struct attribute *lpss_attrs[] = {
458 &dev_attr_auto_ltr.attr,
459 &dev_attr_sw_ltr.attr,
460 &dev_attr_ltr_mode.attr,
464 static struct attribute_group lpss_attr_group = {
469 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
471 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
472 u32 ltr_mode, ltr_val;
474 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
476 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
477 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
478 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
482 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
483 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
484 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
485 val = LPSS_LTR_MAX_VAL;
486 } else if (val > LPSS_LTR_MAX_VAL) {
487 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
488 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
490 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
493 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
494 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
495 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
496 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
502 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
504 * @pdata: pointer to the private data of the LPSS device
506 * Most LPSS devices have private registers which may loose their context when
507 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
510 static void acpi_lpss_save_ctx(struct device *dev,
511 struct lpss_private_data *pdata)
515 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
516 unsigned long offset = i * sizeof(u32);
518 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
519 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
520 pdata->prv_reg_ctx[i], offset);
525 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
527 * @pdata: pointer to the private data of the LPSS device
529 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
531 static void acpi_lpss_restore_ctx(struct device *dev,
532 struct lpss_private_data *pdata)
537 * The following delay is needed or the subsequent write operations may
538 * fail. The LPSS devices are actually PCI devices and the PCI spec
539 * expects 10ms delay before the device can be accessed after D3 to D0
544 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
545 unsigned long offset = i * sizeof(u32);
547 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
548 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
549 pdata->prv_reg_ctx[i], offset);
553 #ifdef CONFIG_PM_SLEEP
554 static int acpi_lpss_suspend_late(struct device *dev)
556 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
559 ret = pm_generic_suspend_late(dev);
563 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
564 acpi_lpss_save_ctx(dev, pdata);
566 return acpi_dev_suspend_late(dev);
569 static int acpi_lpss_resume_early(struct device *dev)
571 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
574 ret = acpi_dev_resume_early(dev);
578 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
579 acpi_lpss_restore_ctx(dev, pdata);
581 return pm_generic_resume_early(dev);
583 #endif /* CONFIG_PM_SLEEP */
585 static int acpi_lpss_runtime_suspend(struct device *dev)
587 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
590 ret = pm_generic_runtime_suspend(dev);
594 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
595 acpi_lpss_save_ctx(dev, pdata);
597 return acpi_dev_runtime_suspend(dev);
600 static int acpi_lpss_runtime_resume(struct device *dev)
602 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
605 ret = acpi_dev_runtime_resume(dev);
609 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
610 acpi_lpss_restore_ctx(dev, pdata);
612 return pm_generic_runtime_resume(dev);
614 #endif /* CONFIG_PM */
616 static struct dev_pm_domain acpi_lpss_pm_domain = {
619 #ifdef CONFIG_PM_SLEEP
620 .prepare = acpi_subsys_prepare,
621 .complete = acpi_subsys_complete,
622 .suspend = acpi_subsys_suspend,
623 .suspend_late = acpi_lpss_suspend_late,
624 .resume_early = acpi_lpss_resume_early,
625 .freeze = acpi_subsys_freeze,
626 .poweroff = acpi_subsys_suspend,
627 .poweroff_late = acpi_lpss_suspend_late,
628 .restore_early = acpi_lpss_resume_early,
630 .runtime_suspend = acpi_lpss_runtime_suspend,
631 .runtime_resume = acpi_lpss_runtime_resume,
636 static int acpi_lpss_platform_notify(struct notifier_block *nb,
637 unsigned long action, void *data)
639 struct platform_device *pdev = to_platform_device(data);
640 struct lpss_private_data *pdata;
641 struct acpi_device *adev;
642 const struct acpi_device_id *id;
644 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
645 if (!id || !id->driver_data)
648 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
651 pdata = acpi_driver_data(adev);
655 if (pdata->mmio_base &&
656 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
657 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
662 case BUS_NOTIFY_ADD_DEVICE:
663 pdev->dev.pm_domain = &acpi_lpss_pm_domain;
664 if (pdata->dev_desc->flags & LPSS_LTR)
665 return sysfs_create_group(&pdev->dev.kobj,
668 case BUS_NOTIFY_DEL_DEVICE:
669 if (pdata->dev_desc->flags & LPSS_LTR)
670 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
671 pdev->dev.pm_domain = NULL;
680 static struct notifier_block acpi_lpss_nb = {
681 .notifier_call = acpi_lpss_platform_notify,
684 static void acpi_lpss_bind(struct device *dev)
686 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
688 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
691 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
692 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
694 dev_err(dev, "MMIO size insufficient to access LTR\n");
697 static void acpi_lpss_unbind(struct device *dev)
699 dev->power.set_latency_tolerance = NULL;
702 static struct acpi_scan_handler lpss_handler = {
703 .ids = acpi_lpss_device_ids,
704 .attach = acpi_lpss_create_device,
705 .bind = acpi_lpss_bind,
706 .unbind = acpi_lpss_unbind,
709 void __init acpi_lpss_init(void)
711 if (!lpt_clk_init()) {
712 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
713 acpi_scan_add_handler(&lpss_handler);
719 static struct acpi_scan_handler lpss_handler = {
720 .ids = acpi_lpss_device_ids,
723 void __init acpi_lpss_init(void)
725 acpi_scan_add_handler(&lpss_handler);
728 #endif /* CONFIG_X86_INTEL_LPSS */