2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
59 /* board IDs by feature in alphabetical order */
65 /* board IDs for specific chipsets in alphabetical order */
71 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 static struct scsi_host_template ahci_sht = {
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
107 static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
113 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
115 static const struct ata_port_info ahci_port_info[] = {
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
124 [board_ahci_ign_iferr] =
126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
132 [board_ahci_nosntf] =
134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
140 [board_ahci_yes_fbs] =
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_sb600_ops,
193 [board_ahci_sb700] = /* for SB700 and SB800 */
195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_sb600_ops,
201 [board_ahci_vt8251] =
203 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_vt8251_ops,
211 static const struct pci_device_id ahci_pci_tbl[] = {
213 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
214 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
215 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
216 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
217 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
218 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
219 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
223 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
225 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
227 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
239 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
240 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
241 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
242 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
243 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
244 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
250 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
251 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
252 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
260 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
262 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
263 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
265 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
266 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
267 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
270 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
271 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
276 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
280 /* AMD is using RAID class only for ahci controllers */
281 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
282 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
285 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
286 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
289 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
376 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
377 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
380 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
381 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
382 { PCI_DEVICE(0x1b4b, 0x9123),
383 .class = PCI_CLASS_STORAGE_SATA_AHCI,
384 .class_mask = 0xffffff,
385 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
386 { PCI_DEVICE(0x1b4b, 0x9125),
387 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
390 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
392 /* Generic, PCI class code for AHCI */
393 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
394 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
396 { } /* terminate list */
400 static struct pci_driver ahci_pci_driver = {
402 .id_table = ahci_pci_tbl,
403 .probe = ahci_init_one,
404 .remove = ata_pci_remove_one,
406 .suspend = ahci_pci_device_suspend,
407 .resume = ahci_pci_device_resume,
411 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
412 static int marvell_enable;
414 static int marvell_enable = 1;
416 module_param(marvell_enable, int, 0644);
417 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
420 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
421 struct ahci_host_priv *hpriv)
423 unsigned int force_port_map = 0;
424 unsigned int mask_port_map = 0;
426 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
427 dev_info(&pdev->dev, "JMB361 has only one port\n");
432 * Temporary Marvell 6145 hack: PATA port presence
433 * is asserted through the standard AHCI port
434 * presence register, as bit 4 (counting from 0)
436 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
437 if (pdev->device == 0x6121)
442 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
445 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
449 static int ahci_pci_reset_controller(struct ata_host *host)
451 struct pci_dev *pdev = to_pci_dev(host->dev);
453 ahci_reset_controller(host);
455 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
456 struct ahci_host_priv *hpriv = host->private_data;
460 pci_read_config_word(pdev, 0x92, &tmp16);
461 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
462 tmp16 |= hpriv->port_map;
463 pci_write_config_word(pdev, 0x92, tmp16);
470 static void ahci_pci_init_controller(struct ata_host *host)
472 struct ahci_host_priv *hpriv = host->private_data;
473 struct pci_dev *pdev = to_pci_dev(host->dev);
474 void __iomem *port_mmio;
478 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
479 if (pdev->device == 0x6121)
483 port_mmio = __ahci_port_base(host, mv);
485 writel(0, port_mmio + PORT_IRQ_MASK);
488 tmp = readl(port_mmio + PORT_IRQ_STAT);
489 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
491 writel(tmp, port_mmio + PORT_IRQ_STAT);
494 ahci_init_controller(host);
497 static int ahci_sb600_check_ready(struct ata_link *link)
499 void __iomem *port_mmio = ahci_port_base(link->ap);
500 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
501 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
504 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
505 * which can save timeout delay.
507 if (irq_status & PORT_IRQ_BAD_PMP)
510 return ata_check_ready(status);
513 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
514 unsigned long deadline)
516 struct ata_port *ap = link->ap;
517 void __iomem *port_mmio = ahci_port_base(ap);
518 int pmp = sata_srst_pmp(link);
524 rc = ahci_do_softreset(link, class, pmp, deadline,
525 ahci_sb600_check_ready);
528 * Soft reset fails on some ATI chips with IPMS set when PMP
529 * is enabled but SATA HDD/ODD is connected to SATA port,
530 * do soft reset again to port 0.
533 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
534 if (irq_sts & PORT_IRQ_BAD_PMP) {
535 ata_link_printk(link, KERN_WARNING,
536 "applying SB600 PMP SRST workaround "
538 rc = ahci_do_softreset(link, class, 0, deadline,
546 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
547 unsigned long deadline)
549 struct ata_port *ap = link->ap;
555 ahci_stop_engine(ap);
557 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
558 deadline, &online, NULL);
560 ahci_start_engine(ap);
562 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
564 /* vt8251 doesn't clear BSY on signature FIS reception,
565 * request follow-up softreset.
567 return online ? -EAGAIN : rc;
570 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
571 unsigned long deadline)
573 struct ata_port *ap = link->ap;
574 struct ahci_port_priv *pp = ap->private_data;
575 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
576 struct ata_taskfile tf;
580 ahci_stop_engine(ap);
582 /* clear D2H reception area to properly wait for D2H FIS */
583 ata_tf_init(link->device, &tf);
585 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
587 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
588 deadline, &online, NULL);
590 ahci_start_engine(ap);
592 /* The pseudo configuration device on SIMG4726 attached to
593 * ASUS P5W-DH Deluxe doesn't send signature FIS after
594 * hardreset if no device is attached to the first downstream
595 * port && the pseudo device locks up on SRST w/ PMP==0. To
596 * work around this, wait for !BSY only briefly. If BSY isn't
597 * cleared, perform CLO and proceed to IDENTIFY (achieved by
598 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
600 * Wait for two seconds. Devices attached to downstream port
601 * which can't process the following IDENTIFY after this will
602 * have to be reset again. For most cases, this should
603 * suffice while making probing snappish enough.
606 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
609 ahci_kick_engine(ap);
615 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
617 struct ata_host *host = dev_get_drvdata(&pdev->dev);
618 struct ahci_host_priv *hpriv = host->private_data;
619 void __iomem *mmio = hpriv->mmio;
622 if (mesg.event & PM_EVENT_SUSPEND &&
623 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
624 dev_printk(KERN_ERR, &pdev->dev,
625 "BIOS update required for suspend/resume\n");
629 if (mesg.event & PM_EVENT_SLEEP) {
630 /* AHCI spec rev1.1 section 8.3.3:
631 * Software must disable interrupts prior to requesting a
632 * transition of the HBA to D3 state.
634 ctl = readl(mmio + HOST_CTL);
636 writel(ctl, mmio + HOST_CTL);
637 readl(mmio + HOST_CTL); /* flush */
640 return ata_pci_device_suspend(pdev, mesg);
643 static int ahci_pci_device_resume(struct pci_dev *pdev)
645 struct ata_host *host = dev_get_drvdata(&pdev->dev);
648 rc = ata_pci_device_do_resume(pdev);
652 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
653 rc = ahci_pci_reset_controller(host);
657 ahci_pci_init_controller(host);
660 ata_host_resume(host);
666 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
671 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
672 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
674 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
676 dev_printk(KERN_ERR, &pdev->dev,
677 "64-bit DMA enable failed\n");
682 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
684 dev_printk(KERN_ERR, &pdev->dev,
685 "32-bit DMA enable failed\n");
688 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
690 dev_printk(KERN_ERR, &pdev->dev,
691 "32-bit consistent DMA enable failed\n");
698 static void ahci_pci_print_info(struct ata_host *host)
700 struct pci_dev *pdev = to_pci_dev(host->dev);
704 pci_read_config_word(pdev, 0x0a, &cc);
705 if (cc == PCI_CLASS_STORAGE_IDE)
707 else if (cc == PCI_CLASS_STORAGE_SATA)
709 else if (cc == PCI_CLASS_STORAGE_RAID)
714 ahci_print_info(host, scc_s);
717 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
718 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
719 * support PMP and the 4726 either directly exports the device
720 * attached to the first downstream port or acts as a hardware storage
721 * controller and emulate a single ATA device (can be RAID 0/1 or some
722 * other configuration).
724 * When there's no device attached to the first downstream port of the
725 * 4726, "Config Disk" appears, which is a pseudo ATA device to
726 * configure the 4726. However, ATA emulation of the device is very
727 * lame. It doesn't send signature D2H Reg FIS after the initial
728 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
730 * The following function works around the problem by always using
731 * hardreset on the port and not depending on receiving signature FIS
732 * afterward. If signature FIS isn't received soon, ATA class is
733 * assumed without follow-up softreset.
735 static void ahci_p5wdh_workaround(struct ata_host *host)
737 static struct dmi_system_id sysids[] = {
739 .ident = "P5W DH Deluxe",
741 DMI_MATCH(DMI_SYS_VENDOR,
742 "ASUSTEK COMPUTER INC"),
743 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
748 struct pci_dev *pdev = to_pci_dev(host->dev);
750 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
751 dmi_check_system(sysids)) {
752 struct ata_port *ap = host->ports[1];
754 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
755 "Deluxe on-board SIMG4726 workaround\n");
757 ap->ops = &ahci_p5wdh_ops;
758 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
762 /* only some SB600 ahci controllers can do 64bit DMA */
763 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
765 static const struct dmi_system_id sysids[] = {
767 * The oldest version known to be broken is 0901 and
768 * working is 1501 which was released on 2007-10-26.
769 * Enable 64bit DMA on 1501 and anything newer.
771 * Please read bko#9412 for more info.
774 .ident = "ASUS M2A-VM",
776 DMI_MATCH(DMI_BOARD_VENDOR,
777 "ASUSTeK Computer INC."),
778 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
780 .driver_data = "20071026", /* yyyymmdd */
783 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
786 * BIOS versions earlier than 1.5 had the Manufacturer DMI
787 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
788 * This spelling mistake was fixed in BIOS version 1.5, so
789 * 1.5 and later have the Manufacturer as
790 * "MICRO-STAR INTERNATIONAL CO.,LTD".
791 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
793 * BIOS versions earlier than 1.9 had a Board Product Name
794 * DMI field of "MS-7376". This was changed to be
795 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
796 * match on DMI_BOARD_NAME of "MS-7376".
799 .ident = "MSI K9A2 Platinum",
801 DMI_MATCH(DMI_BOARD_VENDOR,
803 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
808 const struct dmi_system_id *match;
809 int year, month, date;
812 match = dmi_first_match(sysids);
813 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
817 if (!match->driver_data)
820 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
821 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
823 if (strcmp(buf, match->driver_data) >= 0)
826 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
827 "forcing 32bit DMA, update BIOS\n", match->ident);
832 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
837 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
839 static const struct dmi_system_id broken_systems[] = {
841 .ident = "HP Compaq nx6310",
843 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
844 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
846 /* PCI slot number of the controller */
847 .driver_data = (void *)0x1FUL,
850 .ident = "HP Compaq 6720s",
852 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
853 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
855 /* PCI slot number of the controller */
856 .driver_data = (void *)0x1FUL,
859 { } /* terminate list */
861 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
864 unsigned long slot = (unsigned long)dmi->driver_data;
865 /* apply the quirk only to on-board controllers */
866 return slot == PCI_SLOT(pdev->devfn);
872 static bool ahci_broken_suspend(struct pci_dev *pdev)
874 static const struct dmi_system_id sysids[] = {
876 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
877 * to the harddisk doesn't become online after
878 * resuming from STR. Warn and fail suspend.
880 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
882 * Use dates instead of versions to match as HP is
883 * apparently recycling both product and version
886 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
891 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
892 DMI_MATCH(DMI_PRODUCT_NAME,
893 "HP Pavilion dv4 Notebook PC"),
895 .driver_data = "20090105", /* F.30 */
900 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
901 DMI_MATCH(DMI_PRODUCT_NAME,
902 "HP Pavilion dv5 Notebook PC"),
904 .driver_data = "20090506", /* F.16 */
909 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
910 DMI_MATCH(DMI_PRODUCT_NAME,
911 "HP Pavilion dv6 Notebook PC"),
913 .driver_data = "20090423", /* F.21 */
918 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
919 DMI_MATCH(DMI_PRODUCT_NAME,
920 "HP HDX18 Notebook PC"),
922 .driver_data = "20090430", /* F.23 */
925 * Acer eMachines G725 has the same problem. BIOS
926 * V1.03 is known to be broken. V3.04 is known to
927 * work. Inbetween, there are V1.06, V2.06 and V3.03
928 * that we don't have much idea about. For now,
929 * blacklist anything older than V3.04.
931 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
936 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
937 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
939 .driver_data = "20091216", /* V3.04 */
941 { } /* terminate list */
943 const struct dmi_system_id *dmi = dmi_first_match(sysids);
944 int year, month, date;
947 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
950 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
951 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
953 return strcmp(buf, dmi->driver_data) < 0;
956 static bool ahci_broken_online(struct pci_dev *pdev)
958 #define ENCODE_BUSDEVFN(bus, slot, func) \
959 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
960 static const struct dmi_system_id sysids[] = {
962 * There are several gigabyte boards which use
963 * SIMG5723s configured as hardware RAID. Certain
964 * 5723 firmware revisions shipped there keep the link
965 * online but fail to answer properly to SRST or
966 * IDENTIFY when no device is attached downstream
967 * causing libata to retry quite a few times leading
968 * to excessive detection delay.
970 * As these firmwares respond to the second reset try
971 * with invalid device signature, considering unknown
972 * sig as offline works around the problem acceptably.
977 DMI_MATCH(DMI_BOARD_VENDOR,
978 "Gigabyte Technology Co., Ltd."),
979 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
981 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
986 DMI_MATCH(DMI_BOARD_VENDOR,
987 "Gigabyte Technology Co., Ltd."),
988 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
990 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
992 { } /* terminate list */
994 #undef ENCODE_BUSDEVFN
995 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1001 val = (unsigned long)dmi->driver_data;
1003 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1006 #ifdef CONFIG_ATA_ACPI
1007 static void ahci_gtf_filter_workaround(struct ata_host *host)
1009 static const struct dmi_system_id sysids[] = {
1011 * Aspire 3810T issues a bunch of SATA enable commands
1012 * via _GTF including an invalid one and one which is
1013 * rejected by the device. Among the successful ones
1014 * is FPDMA non-zero offset enable which when enabled
1015 * only on the drive side leads to NCQ command
1016 * failures. Filter it out.
1019 .ident = "Aspire 3810T",
1021 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1022 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1024 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1028 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1029 unsigned int filter;
1035 filter = (unsigned long)dmi->driver_data;
1036 dev_printk(KERN_INFO, host->dev,
1037 "applying extra ACPI _GTF filter 0x%x for %s\n",
1038 filter, dmi->ident);
1040 for (i = 0; i < host->n_ports; i++) {
1041 struct ata_port *ap = host->ports[i];
1042 struct ata_link *link;
1043 struct ata_device *dev;
1045 ata_for_each_link(link, ap, EDGE)
1046 ata_for_each_dev(dev, link, ALL)
1047 dev->gtf_filter |= filter;
1051 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1055 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1057 static int printed_version;
1058 unsigned int board_id = ent->driver_data;
1059 struct ata_port_info pi = ahci_port_info[board_id];
1060 const struct ata_port_info *ppi[] = { &pi, NULL };
1061 struct device *dev = &pdev->dev;
1062 struct ahci_host_priv *hpriv;
1063 struct ata_host *host;
1068 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1070 if (!printed_version++)
1071 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1073 /* The AHCI driver can only drive the SATA ports, the PATA driver
1074 can drive them all so if both drivers are selected make sure
1075 AHCI stays out of the way */
1076 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1080 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1081 * ahci, use ata_generic instead.
1083 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1084 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1085 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1086 pdev->subsystem_device == 0xcb89)
1089 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1090 * At the moment, we can only use the AHCI mode. Let the users know
1091 * that for SAS drives they're out of luck.
1093 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1094 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1095 "can only drive SATA devices with this driver\n");
1097 /* acquire resources */
1098 rc = pcim_enable_device(pdev);
1102 /* AHCI controllers often implement SFF compatible interface.
1103 * Grab all PCI BARs just in case.
1105 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1107 pcim_pin_device(pdev);
1111 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1112 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1115 /* ICH6s share the same PCI ID for both piix and ahci
1116 * modes. Enabling ahci mode while MAP indicates
1117 * combined mode is a bad idea. Yield to ata_piix.
1119 pci_read_config_byte(pdev, ICH_MAP, &map);
1121 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1122 "combined mode, can't enable AHCI mode\n");
1127 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1130 hpriv->flags |= (unsigned long)pi.private_data;
1132 /* MCP65 revision A1 and A2 can't do MSI */
1133 if (board_id == board_ahci_mcp65 &&
1134 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1135 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1137 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1138 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1139 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1141 /* only some SB600s can do 64bit DMA */
1142 if (ahci_sb600_enable_64bit(pdev))
1143 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1145 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1148 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1150 /* save initial config */
1151 ahci_pci_save_initial_config(pdev, hpriv);
1154 if (hpriv->cap & HOST_CAP_NCQ) {
1155 pi.flags |= ATA_FLAG_NCQ;
1157 * Auto-activate optimization is supposed to be
1158 * supported on all AHCI controllers indicating NCQ
1159 * capability, but it seems to be broken on some
1160 * chipsets including NVIDIAs.
1162 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1163 pi.flags |= ATA_FLAG_FPDMA_AA;
1166 if (hpriv->cap & HOST_CAP_PMP)
1167 pi.flags |= ATA_FLAG_PMP;
1169 ahci_set_em_messages(hpriv, &pi);
1171 if (ahci_broken_system_poweroff(pdev)) {
1172 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1173 dev_info(&pdev->dev,
1174 "quirky BIOS, skipping spindown on poweroff\n");
1177 if (ahci_broken_suspend(pdev)) {
1178 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1179 dev_printk(KERN_WARNING, &pdev->dev,
1180 "BIOS update required for suspend/resume\n");
1183 if (ahci_broken_online(pdev)) {
1184 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1185 dev_info(&pdev->dev,
1186 "online status unreliable, applying workaround\n");
1189 /* CAP.NP sometimes indicate the index of the last enabled
1190 * port, at other times, that of the last possible port, so
1191 * determining the maximum port number requires looking at
1192 * both CAP.NP and port_map.
1194 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1196 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1199 host->private_data = hpriv;
1201 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1202 host->flags |= ATA_HOST_PARALLEL_SCAN;
1204 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1206 if (pi.flags & ATA_FLAG_EM)
1207 ahci_reset_em(host);
1209 for (i = 0; i < host->n_ports; i++) {
1210 struct ata_port *ap = host->ports[i];
1212 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1213 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1214 0x100 + ap->port_no * 0x80, "port");
1216 /* set enclosure management message type */
1217 if (ap->flags & ATA_FLAG_EM)
1218 ap->em_message_type = hpriv->em_msg_type;
1221 /* disabled/not-implemented port */
1222 if (!(hpriv->port_map & (1 << i)))
1223 ap->ops = &ata_dummy_port_ops;
1226 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1227 ahci_p5wdh_workaround(host);
1229 /* apply gtf filter quirk */
1230 ahci_gtf_filter_workaround(host);
1232 /* initialize adapter */
1233 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1237 rc = ahci_pci_reset_controller(host);
1241 ahci_pci_init_controller(host);
1242 ahci_pci_print_info(host);
1244 pci_set_master(pdev);
1245 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1249 static int __init ahci_init(void)
1251 return pci_register_driver(&ahci_pci_driver);
1254 static void __exit ahci_exit(void)
1256 pci_unregister_driver(&ahci_pci_driver);
1260 MODULE_AUTHOR("Jeff Garzik");
1261 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1262 MODULE_LICENSE("GPL");
1263 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1264 MODULE_VERSION(DRV_VERSION);
1266 module_init(ahci_init);
1267 module_exit(ahci_exit);