2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "3.0"
54 AHCI_PCI_BAR_STA2X11 = 0,
55 AHCI_PCI_BAR_ENMOTUS = 2,
56 AHCI_PCI_BAR_STANDARD = 5,
60 /* board IDs by feature in alphabetical order */
68 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
88 static bool is_mcp89_apple(struct pci_dev *pdev);
89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
92 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
93 static int ahci_pci_device_resume(struct pci_dev *pdev);
96 static struct scsi_host_template ahci_sht = {
100 static struct ata_port_operations ahci_vt8251_ops = {
101 .inherits = &ahci_ops,
102 .hardreset = ahci_vt8251_hardreset,
105 static struct ata_port_operations ahci_p5wdh_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_p5wdh_hardreset,
110 static const struct ata_port_info ahci_port_info[] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
118 [board_ahci_ign_iferr] = {
119 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
120 .flags = AHCI_FLAG_COMMON,
121 .pio_mask = ATA_PIO4,
122 .udma_mask = ATA_UDMA6,
123 .port_ops = &ahci_ops,
125 [board_ahci_nomsi] = {
126 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
132 [board_ahci_noncq] = {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
139 [board_ahci_nosntf] = {
140 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
146 [board_ahci_yes_fbs] = {
147 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
154 [board_ahci_mcp65] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
157 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
162 [board_ahci_mcp77] = {
163 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
164 .flags = AHCI_FLAG_COMMON,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
169 [board_ahci_mcp89] = {
170 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
177 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
178 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
179 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
184 [board_ahci_sb600] = {
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_pmp_retry_srst_ops,
193 [board_ahci_sb700] = { /* for SB700 and SB800 */
194 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_pmp_retry_srst_ops,
200 [board_ahci_vt8251] = {
201 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_vt8251_ops,
209 static const struct pci_device_id ahci_pci_tbl[] = {
211 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
212 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
213 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
214 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
215 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
216 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
217 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
221 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
222 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
226 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
237 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
240 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
241 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
242 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
243 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
245 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
247 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
248 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
250 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
251 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
258 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
259 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
260 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
262 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
266 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
270 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
271 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
274 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
275 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
277 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
278 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
279 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
282 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
283 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
285 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
294 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
295 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
301 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
303 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
304 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
306 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
307 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
308 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
310 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
311 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
312 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
313 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
314 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
318 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
319 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
320 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
321 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
322 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
323 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
324 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
325 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
328 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
329 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
330 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
331 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
333 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
334 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
335 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
336 /* JMicron 362B and 362C have an AHCI function with IDE class code */
337 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
338 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
341 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
342 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
343 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
344 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
345 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
346 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
347 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
350 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
351 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
352 /* AMD is using RAID class only for ahci controllers */
353 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
354 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
357 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
358 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
361 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
362 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
363 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
364 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
365 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
366 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
367 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
368 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
369 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
374 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
375 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
376 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
377 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
378 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
379 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
380 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
381 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
390 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
391 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
392 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
393 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
394 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
395 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
396 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
397 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
402 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
403 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
404 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
405 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
406 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
407 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
408 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
414 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
415 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
416 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
417 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
418 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
419 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
420 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
421 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
426 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
427 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
428 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
429 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
430 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
431 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
432 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
433 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
438 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
439 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
440 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
441 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
442 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
443 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
444 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
447 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
448 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
449 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
451 /* ST Microelectronics */
452 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
455 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
456 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
457 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
458 .class = PCI_CLASS_STORAGE_SATA_AHCI,
459 .class_mask = 0xffffff,
460 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
461 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
462 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
463 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
464 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
465 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
466 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
467 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
468 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
469 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
470 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
471 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
472 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
473 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
474 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
475 .driver_data = board_ahci_yes_fbs },
476 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
477 .driver_data = board_ahci_yes_fbs },
478 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
479 .driver_data = board_ahci_yes_fbs },
480 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
481 .driver_data = board_ahci_yes_fbs },
484 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
485 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
488 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
489 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
490 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
491 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
494 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
495 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
497 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
498 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
501 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
503 /* Generic, PCI class code for AHCI */
504 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
505 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
507 { } /* terminate list */
511 static struct pci_driver ahci_pci_driver = {
513 .id_table = ahci_pci_tbl,
514 .probe = ahci_init_one,
515 .remove = ata_pci_remove_one,
517 .suspend = ahci_pci_device_suspend,
518 .resume = ahci_pci_device_resume,
522 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
523 static int marvell_enable;
525 static int marvell_enable = 1;
527 module_param(marvell_enable, int, 0644);
528 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
531 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
532 struct ahci_host_priv *hpriv)
534 unsigned int force_port_map = 0;
535 unsigned int mask_port_map = 0;
537 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
538 dev_info(&pdev->dev, "JMB361 has only one port\n");
543 * Temporary Marvell 6145 hack: PATA port presence
544 * is asserted through the standard AHCI port
545 * presence register, as bit 4 (counting from 0)
547 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
548 if (pdev->device == 0x6121)
553 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
556 ahci_save_initial_config(&pdev->dev, hpriv);
559 static int ahci_pci_reset_controller(struct ata_host *host)
561 struct pci_dev *pdev = to_pci_dev(host->dev);
563 ahci_reset_controller(host);
565 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
566 struct ahci_host_priv *hpriv = host->private_data;
570 pci_read_config_word(pdev, 0x92, &tmp16);
571 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
572 tmp16 |= hpriv->port_map;
573 pci_write_config_word(pdev, 0x92, tmp16);
580 static void ahci_pci_init_controller(struct ata_host *host)
582 struct ahci_host_priv *hpriv = host->private_data;
583 struct pci_dev *pdev = to_pci_dev(host->dev);
584 void __iomem *port_mmio;
588 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
589 if (pdev->device == 0x6121)
593 port_mmio = __ahci_port_base(host, mv);
595 writel(0, port_mmio + PORT_IRQ_MASK);
598 tmp = readl(port_mmio + PORT_IRQ_STAT);
599 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
601 writel(tmp, port_mmio + PORT_IRQ_STAT);
604 ahci_init_controller(host);
607 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
608 unsigned long deadline)
610 struct ata_port *ap = link->ap;
611 struct ahci_host_priv *hpriv = ap->host->private_data;
617 ahci_stop_engine(ap);
619 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
620 deadline, &online, NULL);
622 hpriv->start_engine(ap);
624 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
626 /* vt8251 doesn't clear BSY on signature FIS reception,
627 * request follow-up softreset.
629 return online ? -EAGAIN : rc;
632 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
633 unsigned long deadline)
635 struct ata_port *ap = link->ap;
636 struct ahci_port_priv *pp = ap->private_data;
637 struct ahci_host_priv *hpriv = ap->host->private_data;
638 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
639 struct ata_taskfile tf;
643 ahci_stop_engine(ap);
645 /* clear D2H reception area to properly wait for D2H FIS */
646 ata_tf_init(link->device, &tf);
647 tf.command = ATA_BUSY;
648 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
650 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
651 deadline, &online, NULL);
653 hpriv->start_engine(ap);
655 /* The pseudo configuration device on SIMG4726 attached to
656 * ASUS P5W-DH Deluxe doesn't send signature FIS after
657 * hardreset if no device is attached to the first downstream
658 * port && the pseudo device locks up on SRST w/ PMP==0. To
659 * work around this, wait for !BSY only briefly. If BSY isn't
660 * cleared, perform CLO and proceed to IDENTIFY (achieved by
661 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
663 * Wait for two seconds. Devices attached to downstream port
664 * which can't process the following IDENTIFY after this will
665 * have to be reset again. For most cases, this should
666 * suffice while making probing snappish enough.
669 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
672 ahci_kick_engine(ap);
678 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
680 struct ata_host *host = pci_get_drvdata(pdev);
681 struct ahci_host_priv *hpriv = host->private_data;
682 void __iomem *mmio = hpriv->mmio;
685 if (mesg.event & PM_EVENT_SUSPEND &&
686 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
688 "BIOS update required for suspend/resume\n");
692 if (mesg.event & PM_EVENT_SLEEP) {
693 /* AHCI spec rev1.1 section 8.3.3:
694 * Software must disable interrupts prior to requesting a
695 * transition of the HBA to D3 state.
697 ctl = readl(mmio + HOST_CTL);
699 writel(ctl, mmio + HOST_CTL);
700 readl(mmio + HOST_CTL); /* flush */
703 return ata_pci_device_suspend(pdev, mesg);
706 static int ahci_pci_device_resume(struct pci_dev *pdev)
708 struct ata_host *host = pci_get_drvdata(pdev);
711 rc = ata_pci_device_do_resume(pdev);
715 /* Apple BIOS helpfully mangles the registers on resume */
716 if (is_mcp89_apple(pdev))
717 ahci_mcp89_apple_enable(pdev);
719 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
720 rc = ahci_pci_reset_controller(host);
724 ahci_pci_init_controller(host);
727 ata_host_resume(host);
733 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
738 * If the device fixup already set the dma_mask to some non-standard
739 * value, don't extend it here. This happens on STA2X11, for example.
741 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
745 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
746 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
748 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
751 "64-bit DMA enable failed\n");
756 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
758 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
761 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
764 "32-bit consistent DMA enable failed\n");
771 static void ahci_pci_print_info(struct ata_host *host)
773 struct pci_dev *pdev = to_pci_dev(host->dev);
777 pci_read_config_word(pdev, 0x0a, &cc);
778 if (cc == PCI_CLASS_STORAGE_IDE)
780 else if (cc == PCI_CLASS_STORAGE_SATA)
782 else if (cc == PCI_CLASS_STORAGE_RAID)
787 ahci_print_info(host, scc_s);
790 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
791 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
792 * support PMP and the 4726 either directly exports the device
793 * attached to the first downstream port or acts as a hardware storage
794 * controller and emulate a single ATA device (can be RAID 0/1 or some
795 * other configuration).
797 * When there's no device attached to the first downstream port of the
798 * 4726, "Config Disk" appears, which is a pseudo ATA device to
799 * configure the 4726. However, ATA emulation of the device is very
800 * lame. It doesn't send signature D2H Reg FIS after the initial
801 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
803 * The following function works around the problem by always using
804 * hardreset on the port and not depending on receiving signature FIS
805 * afterward. If signature FIS isn't received soon, ATA class is
806 * assumed without follow-up softreset.
808 static void ahci_p5wdh_workaround(struct ata_host *host)
810 static struct dmi_system_id sysids[] = {
812 .ident = "P5W DH Deluxe",
814 DMI_MATCH(DMI_SYS_VENDOR,
815 "ASUSTEK COMPUTER INC"),
816 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
821 struct pci_dev *pdev = to_pci_dev(host->dev);
823 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
824 dmi_check_system(sysids)) {
825 struct ata_port *ap = host->ports[1];
828 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
830 ap->ops = &ahci_p5wdh_ops;
831 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
836 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
837 * booting in BIOS compatibility mode. We restore the registers but not ID.
839 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
843 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
845 pci_read_config_dword(pdev, 0xf8, &val);
847 /* the following changes the device ID, but appears not to affect function */
848 /* val = (val & ~0xf0000000) | 0x80000000; */
849 pci_write_config_dword(pdev, 0xf8, val);
851 pci_read_config_dword(pdev, 0x54c, &val);
853 pci_write_config_dword(pdev, 0x54c, val);
855 pci_read_config_dword(pdev, 0x4a4, &val);
858 pci_write_config_dword(pdev, 0x4a4, val);
860 pci_read_config_dword(pdev, 0x54c, &val);
862 pci_write_config_dword(pdev, 0x54c, val);
864 pci_read_config_dword(pdev, 0xf8, &val);
866 pci_write_config_dword(pdev, 0xf8, val);
869 static bool is_mcp89_apple(struct pci_dev *pdev)
871 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
872 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
873 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
874 pdev->subsystem_device == 0xcb89;
877 /* only some SB600 ahci controllers can do 64bit DMA */
878 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
880 static const struct dmi_system_id sysids[] = {
882 * The oldest version known to be broken is 0901 and
883 * working is 1501 which was released on 2007-10-26.
884 * Enable 64bit DMA on 1501 and anything newer.
886 * Please read bko#9412 for more info.
889 .ident = "ASUS M2A-VM",
891 DMI_MATCH(DMI_BOARD_VENDOR,
892 "ASUSTeK Computer INC."),
893 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
895 .driver_data = "20071026", /* yyyymmdd */
898 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
901 * BIOS versions earlier than 1.5 had the Manufacturer DMI
902 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
903 * This spelling mistake was fixed in BIOS version 1.5, so
904 * 1.5 and later have the Manufacturer as
905 * "MICRO-STAR INTERNATIONAL CO.,LTD".
906 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
908 * BIOS versions earlier than 1.9 had a Board Product Name
909 * DMI field of "MS-7376". This was changed to be
910 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
911 * match on DMI_BOARD_NAME of "MS-7376".
914 .ident = "MSI K9A2 Platinum",
916 DMI_MATCH(DMI_BOARD_VENDOR,
918 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
922 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
925 * This board also had the typo mentioned above in the
926 * Manufacturer DMI field (fixed in BIOS version 1.5), so
927 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
930 .ident = "MSI K9AGM2",
932 DMI_MATCH(DMI_BOARD_VENDOR,
934 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
938 * All BIOS versions for the Asus M3A support 64bit DMA.
939 * (all release versions from 0301 to 1206 were tested)
944 DMI_MATCH(DMI_BOARD_VENDOR,
945 "ASUSTeK Computer INC."),
946 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
951 const struct dmi_system_id *match;
952 int year, month, date;
955 match = dmi_first_match(sysids);
956 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
960 if (!match->driver_data)
963 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
964 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
966 if (strcmp(buf, match->driver_data) >= 0)
970 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
976 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
980 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
982 static const struct dmi_system_id broken_systems[] = {
984 .ident = "HP Compaq nx6310",
986 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
989 /* PCI slot number of the controller */
990 .driver_data = (void *)0x1FUL,
993 .ident = "HP Compaq 6720s",
995 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
996 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
998 /* PCI slot number of the controller */
999 .driver_data = (void *)0x1FUL,
1002 { } /* terminate list */
1004 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1007 unsigned long slot = (unsigned long)dmi->driver_data;
1008 /* apply the quirk only to on-board controllers */
1009 return slot == PCI_SLOT(pdev->devfn);
1015 static bool ahci_broken_suspend(struct pci_dev *pdev)
1017 static const struct dmi_system_id sysids[] = {
1019 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1020 * to the harddisk doesn't become online after
1021 * resuming from STR. Warn and fail suspend.
1023 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1025 * Use dates instead of versions to match as HP is
1026 * apparently recycling both product and version
1029 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1034 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1035 DMI_MATCH(DMI_PRODUCT_NAME,
1036 "HP Pavilion dv4 Notebook PC"),
1038 .driver_data = "20090105", /* F.30 */
1043 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1044 DMI_MATCH(DMI_PRODUCT_NAME,
1045 "HP Pavilion dv5 Notebook PC"),
1047 .driver_data = "20090506", /* F.16 */
1052 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1053 DMI_MATCH(DMI_PRODUCT_NAME,
1054 "HP Pavilion dv6 Notebook PC"),
1056 .driver_data = "20090423", /* F.21 */
1061 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1062 DMI_MATCH(DMI_PRODUCT_NAME,
1063 "HP HDX18 Notebook PC"),
1065 .driver_data = "20090430", /* F.23 */
1068 * Acer eMachines G725 has the same problem. BIOS
1069 * V1.03 is known to be broken. V3.04 is known to
1070 * work. Between, there are V1.06, V2.06 and V3.03
1071 * that we don't have much idea about. For now,
1072 * blacklist anything older than V3.04.
1074 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1079 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1080 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1082 .driver_data = "20091216", /* V3.04 */
1084 { } /* terminate list */
1086 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1087 int year, month, date;
1090 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1093 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1094 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1096 return strcmp(buf, dmi->driver_data) < 0;
1099 static bool ahci_broken_online(struct pci_dev *pdev)
1101 #define ENCODE_BUSDEVFN(bus, slot, func) \
1102 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1103 static const struct dmi_system_id sysids[] = {
1105 * There are several gigabyte boards which use
1106 * SIMG5723s configured as hardware RAID. Certain
1107 * 5723 firmware revisions shipped there keep the link
1108 * online but fail to answer properly to SRST or
1109 * IDENTIFY when no device is attached downstream
1110 * causing libata to retry quite a few times leading
1111 * to excessive detection delay.
1113 * As these firmwares respond to the second reset try
1114 * with invalid device signature, considering unknown
1115 * sig as offline works around the problem acceptably.
1118 .ident = "EP45-DQ6",
1120 DMI_MATCH(DMI_BOARD_VENDOR,
1121 "Gigabyte Technology Co., Ltd."),
1122 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1124 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1127 .ident = "EP45-DS5",
1129 DMI_MATCH(DMI_BOARD_VENDOR,
1130 "Gigabyte Technology Co., Ltd."),
1131 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1133 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1135 { } /* terminate list */
1137 #undef ENCODE_BUSDEVFN
1138 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1144 val = (unsigned long)dmi->driver_data;
1146 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1149 #ifdef CONFIG_ATA_ACPI
1150 static void ahci_gtf_filter_workaround(struct ata_host *host)
1152 static const struct dmi_system_id sysids[] = {
1154 * Aspire 3810T issues a bunch of SATA enable commands
1155 * via _GTF including an invalid one and one which is
1156 * rejected by the device. Among the successful ones
1157 * is FPDMA non-zero offset enable which when enabled
1158 * only on the drive side leads to NCQ command
1159 * failures. Filter it out.
1162 .ident = "Aspire 3810T",
1164 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1165 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1167 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1171 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1172 unsigned int filter;
1178 filter = (unsigned long)dmi->driver_data;
1179 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1180 filter, dmi->ident);
1182 for (i = 0; i < host->n_ports; i++) {
1183 struct ata_port *ap = host->ports[i];
1184 struct ata_link *link;
1185 struct ata_device *dev;
1187 ata_for_each_link(link, ap, EDGE)
1188 ata_for_each_dev(dev, link, ALL)
1189 dev->gtf_filter |= filter;
1193 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1197 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1198 struct ahci_host_priv *hpriv)
1202 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1205 rc = pci_msi_vec_count(pdev);
1210 * If number of MSIs is less than number of ports then Sharing Last
1211 * Message mode could be enforced. In this case assume that advantage
1212 * of multipe MSIs is negated and use single MSI mode instead.
1218 rc = pci_enable_msi_block(pdev, nvec);
1224 /* fallback to single MSI mode if the controller enforced MRSM mode */
1225 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1226 pci_disable_msi(pdev);
1227 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1231 /* fallback to single MSI mode if the controller enforced MRSM mode */
1232 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1233 pci_disable_msi(pdev);
1234 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1241 rc = pci_enable_msi(pdev);
1252 * ahci_host_activate - start AHCI host, request IRQs and register it
1253 * @host: target ATA host
1254 * @irq: base IRQ number to request
1255 * @n_msis: number of MSIs allocated for this host
1256 * @irq_handler: irq_handler used when requesting IRQs
1257 * @irq_flags: irq_flags used when requesting IRQs
1259 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1260 * when multiple MSIs were allocated. That is one MSI per port, starting
1264 * Inherited from calling layer (may sleep).
1267 * 0 on success, -errno otherwise.
1269 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1273 /* Sharing Last Message among several ports is not supported */
1274 if (n_msis < host->n_ports)
1277 rc = ata_host_start(host);
1281 for (i = 0; i < host->n_ports; i++) {
1282 struct ahci_port_priv *pp = host->ports[i]->private_data;
1284 /* Do not receive interrupts sent by dummy ports */
1286 disable_irq(irq + i);
1290 rc = devm_request_threaded_irq(host->dev, irq + i,
1292 ahci_thread_fn, IRQF_SHARED,
1293 pp->irq_desc, host->ports[i]);
1298 for (i = 0; i < host->n_ports; i++)
1299 ata_port_desc(host->ports[i], "irq %d", irq + i);
1301 rc = ata_host_register(host, &ahci_sht);
1303 goto out_free_all_irqs;
1310 for (i--; i >= 0; i--)
1311 devm_free_irq(host->dev, irq + i, host->ports[i]);
1316 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1318 unsigned int board_id = ent->driver_data;
1319 struct ata_port_info pi = ahci_port_info[board_id];
1320 const struct ata_port_info *ppi[] = { &pi, NULL };
1321 struct device *dev = &pdev->dev;
1322 struct ahci_host_priv *hpriv;
1323 struct ata_host *host;
1324 int n_ports, n_msis, i, rc;
1325 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1329 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1331 ata_print_version_once(&pdev->dev, DRV_VERSION);
1333 /* The AHCI driver can only drive the SATA ports, the PATA driver
1334 can drive them all so if both drivers are selected make sure
1335 AHCI stays out of the way */
1336 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1339 /* Apple BIOS on MCP89 prevents us using AHCI */
1340 if (is_mcp89_apple(pdev))
1341 ahci_mcp89_apple_enable(pdev);
1343 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1344 * At the moment, we can only use the AHCI mode. Let the users know
1345 * that for SAS drives they're out of luck.
1347 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1348 dev_info(&pdev->dev,
1349 "PDC42819 can only drive SATA devices with this driver\n");
1351 /* Both Connext and Enmotus devices use non-standard BARs */
1352 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1353 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1354 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1355 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1357 /* acquire resources */
1358 rc = pcim_enable_device(pdev);
1362 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1363 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1366 /* ICH6s share the same PCI ID for both piix and ahci
1367 * modes. Enabling ahci mode while MAP indicates
1368 * combined mode is a bad idea. Yield to ata_piix.
1370 pci_read_config_byte(pdev, ICH_MAP, &map);
1372 dev_info(&pdev->dev,
1373 "controller is in combined mode, can't enable AHCI mode\n");
1378 /* AHCI controllers often implement SFF compatible interface.
1379 * Grab all PCI BARs just in case.
1381 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1383 pcim_pin_device(pdev);
1387 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1390 hpriv->flags |= (unsigned long)pi.private_data;
1392 /* MCP65 revision A1 and A2 can't do MSI */
1393 if (board_id == board_ahci_mcp65 &&
1394 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1395 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1397 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1398 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1399 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1401 /* only some SB600s can do 64bit DMA */
1402 if (ahci_sb600_enable_64bit(pdev))
1403 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1405 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1407 /* save initial config */
1408 ahci_pci_save_initial_config(pdev, hpriv);
1411 if (hpriv->cap & HOST_CAP_NCQ) {
1412 pi.flags |= ATA_FLAG_NCQ;
1414 * Auto-activate optimization is supposed to be
1415 * supported on all AHCI controllers indicating NCQ
1416 * capability, but it seems to be broken on some
1417 * chipsets including NVIDIAs.
1419 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1420 pi.flags |= ATA_FLAG_FPDMA_AA;
1423 * All AHCI controllers should be forward-compatible
1424 * with the new auxiliary field. This code should be
1425 * conditionalized if any buggy AHCI controllers are
1428 pi.flags |= ATA_FLAG_FPDMA_AUX;
1431 if (hpriv->cap & HOST_CAP_PMP)
1432 pi.flags |= ATA_FLAG_PMP;
1434 ahci_set_em_messages(hpriv, &pi);
1436 if (ahci_broken_system_poweroff(pdev)) {
1437 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1438 dev_info(&pdev->dev,
1439 "quirky BIOS, skipping spindown on poweroff\n");
1442 if (ahci_broken_suspend(pdev)) {
1443 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1444 dev_warn(&pdev->dev,
1445 "BIOS update required for suspend/resume\n");
1448 if (ahci_broken_online(pdev)) {
1449 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1450 dev_info(&pdev->dev,
1451 "online status unreliable, applying workaround\n");
1454 /* CAP.NP sometimes indicate the index of the last enabled
1455 * port, at other times, that of the last possible port, so
1456 * determining the maximum port number requires looking at
1457 * both CAP.NP and port_map.
1459 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1461 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1463 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1465 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1468 host->private_data = hpriv;
1470 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1471 host->flags |= ATA_HOST_PARALLEL_SCAN;
1473 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1475 if (pi.flags & ATA_FLAG_EM)
1476 ahci_reset_em(host);
1478 for (i = 0; i < host->n_ports; i++) {
1479 struct ata_port *ap = host->ports[i];
1481 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1482 ata_port_pbar_desc(ap, ahci_pci_bar,
1483 0x100 + ap->port_no * 0x80, "port");
1485 /* set enclosure management message type */
1486 if (ap->flags & ATA_FLAG_EM)
1487 ap->em_message_type = hpriv->em_msg_type;
1490 /* disabled/not-implemented port */
1491 if (!(hpriv->port_map & (1 << i)))
1492 ap->ops = &ata_dummy_port_ops;
1495 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1496 ahci_p5wdh_workaround(host);
1498 /* apply gtf filter quirk */
1499 ahci_gtf_filter_workaround(host);
1501 /* initialize adapter */
1502 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1506 rc = ahci_pci_reset_controller(host);
1510 ahci_pci_init_controller(host);
1511 ahci_pci_print_info(host);
1513 pci_set_master(pdev);
1515 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1516 return ahci_host_activate(host, pdev->irq, n_msis);
1518 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1522 module_pci_driver(ahci_pci_driver);
1524 MODULE_AUTHOR("Jeff Garzik");
1525 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1526 MODULE_LICENSE("GPL");
1527 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1528 MODULE_VERSION(DRV_VERSION);