2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_CAVIUM = 0,
57 AHCI_PCI_BAR_ENMOTUS = 2,
58 AHCI_PCI_BAR_STANDARD = 5,
62 /* board IDs by feature in alphabetical order */
70 /* board IDs for specific chipsets in alphabetical order */
77 board_ahci_sb700, /* for SB700 and SB800 */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
84 board_ahci_mcp79 = board_ahci_mcp77,
87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
97 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
98 static int ahci_pci_device_resume(struct pci_dev *pdev);
101 static struct scsi_host_template ahci_sht = {
105 static struct ata_port_operations ahci_vt8251_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_vt8251_hardreset,
110 static struct ata_port_operations ahci_p5wdh_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_p5wdh_hardreset,
115 static struct ata_port_operations ahci_avn_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_avn_hardreset,
120 static const struct ata_port_info ahci_port_info[] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_ign_iferr] = {
129 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
135 [board_ahci_nomsi] = {
136 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
142 [board_ahci_noncq] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
149 [board_ahci_nosntf] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
156 [board_ahci_yes_fbs] = {
157 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_avn_ops,
170 [board_ahci_mcp65] = {
171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
173 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
178 [board_ahci_mcp77] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
185 [board_ahci_mcp89] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
194 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
195 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
200 [board_ahci_sb600] = {
201 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
202 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
203 AHCI_HFLAG_32BIT_ONLY),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_pmp_retry_srst_ops,
209 [board_ahci_sb700] = { /* for SB700 and SB800 */
210 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
216 [board_ahci_vt8251] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_vt8251_ops,
225 static const struct pci_device_id ahci_pci_tbl[] = {
227 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
228 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
229 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
230 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
231 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
232 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
233 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
235 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
236 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
237 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
239 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
240 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
241 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
242 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
246 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
247 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
251 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
255 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
256 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
258 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
259 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
260 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
261 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
262 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
264 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
265 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
266 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
268 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
269 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
270 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
271 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
272 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
273 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
288 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
289 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
290 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
291 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
292 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
293 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
294 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
295 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
296 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
297 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
298 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
299 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
300 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
301 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
302 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
303 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
304 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
305 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
308 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
309 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
310 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
311 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
312 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
313 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
314 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
315 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
317 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
318 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
319 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
320 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
321 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
322 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
323 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
324 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
325 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
326 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
327 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
328 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
329 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
338 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
339 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
340 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
341 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
342 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
343 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
344 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
348 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
349 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
352 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
353 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
354 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
355 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
356 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
357 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
358 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
359 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
360 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
361 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
362 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
363 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
364 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
365 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
366 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
367 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
368 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
369 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
370 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
371 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
372 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
373 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
374 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
375 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
376 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
377 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
380 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
381 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
382 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
383 /* JMicron 362B and 362C have an AHCI function with IDE class code */
384 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
385 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
386 /* May need to update quirk_jmicron_async_suspend() for additions */
389 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
390 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
391 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
392 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
393 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
394 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
395 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
398 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
399 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
400 /* AMD is using RAID class only for ahci controllers */
401 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
402 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
405 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
406 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
409 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
410 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
411 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
412 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
415 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
430 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
431 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
432 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
433 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
434 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
435 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
436 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
437 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
438 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
446 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
447 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
448 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
449 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
450 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
451 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
458 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
459 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
460 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
461 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
462 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
463 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
470 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
471 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
472 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
473 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
474 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
475 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
476 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
477 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
478 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
482 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
483 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
484 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
485 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
486 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
487 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
488 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
489 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
490 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
496 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
497 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
499 /* ST Microelectronics */
500 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
503 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
504 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
505 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
506 .class = PCI_CLASS_STORAGE_SATA_AHCI,
507 .class_mask = 0xffffff,
508 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
509 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
510 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
511 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
512 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
513 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
514 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
515 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
516 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
517 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
518 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
519 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
521 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
522 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
523 .driver_data = board_ahci_yes_fbs },
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
525 .driver_data = board_ahci_yes_fbs },
526 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
527 .driver_data = board_ahci_yes_fbs },
528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
529 .driver_data = board_ahci_yes_fbs },
530 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
531 .driver_data = board_ahci_yes_fbs },
534 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
535 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
538 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
539 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
540 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
541 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
544 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
545 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
547 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
548 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
551 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
553 /* Generic, PCI class code for AHCI */
554 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
555 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
557 { } /* terminate list */
561 static struct pci_driver ahci_pci_driver = {
563 .id_table = ahci_pci_tbl,
564 .probe = ahci_init_one,
565 .remove = ata_pci_remove_one,
567 .suspend = ahci_pci_device_suspend,
568 .resume = ahci_pci_device_resume,
572 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
573 static int marvell_enable;
575 static int marvell_enable = 1;
577 module_param(marvell_enable, int, 0644);
578 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
581 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
582 struct ahci_host_priv *hpriv)
584 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
585 dev_info(&pdev->dev, "JMB361 has only one port\n");
586 hpriv->force_port_map = 1;
590 * Temporary Marvell 6145 hack: PATA port presence
591 * is asserted through the standard AHCI port
592 * presence register, as bit 4 (counting from 0)
594 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
595 if (pdev->device == 0x6121)
596 hpriv->mask_port_map = 0x3;
598 hpriv->mask_port_map = 0xf;
600 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
603 ahci_save_initial_config(&pdev->dev, hpriv);
606 static int ahci_pci_reset_controller(struct ata_host *host)
608 struct pci_dev *pdev = to_pci_dev(host->dev);
610 ahci_reset_controller(host);
612 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
613 struct ahci_host_priv *hpriv = host->private_data;
617 pci_read_config_word(pdev, 0x92, &tmp16);
618 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
619 tmp16 |= hpriv->port_map;
620 pci_write_config_word(pdev, 0x92, tmp16);
627 static void ahci_pci_init_controller(struct ata_host *host)
629 struct ahci_host_priv *hpriv = host->private_data;
630 struct pci_dev *pdev = to_pci_dev(host->dev);
631 void __iomem *port_mmio;
635 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
636 if (pdev->device == 0x6121)
640 port_mmio = __ahci_port_base(host, mv);
642 writel(0, port_mmio + PORT_IRQ_MASK);
645 tmp = readl(port_mmio + PORT_IRQ_STAT);
646 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
648 writel(tmp, port_mmio + PORT_IRQ_STAT);
651 ahci_init_controller(host);
654 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
655 unsigned long deadline)
657 struct ata_port *ap = link->ap;
658 struct ahci_host_priv *hpriv = ap->host->private_data;
664 ahci_stop_engine(ap);
666 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
667 deadline, &online, NULL);
669 hpriv->start_engine(ap);
671 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
673 /* vt8251 doesn't clear BSY on signature FIS reception,
674 * request follow-up softreset.
676 return online ? -EAGAIN : rc;
679 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
680 unsigned long deadline)
682 struct ata_port *ap = link->ap;
683 struct ahci_port_priv *pp = ap->private_data;
684 struct ahci_host_priv *hpriv = ap->host->private_data;
685 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
686 struct ata_taskfile tf;
690 ahci_stop_engine(ap);
692 /* clear D2H reception area to properly wait for D2H FIS */
693 ata_tf_init(link->device, &tf);
694 tf.command = ATA_BUSY;
695 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
697 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
698 deadline, &online, NULL);
700 hpriv->start_engine(ap);
702 /* The pseudo configuration device on SIMG4726 attached to
703 * ASUS P5W-DH Deluxe doesn't send signature FIS after
704 * hardreset if no device is attached to the first downstream
705 * port && the pseudo device locks up on SRST w/ PMP==0. To
706 * work around this, wait for !BSY only briefly. If BSY isn't
707 * cleared, perform CLO and proceed to IDENTIFY (achieved by
708 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
710 * Wait for two seconds. Devices attached to downstream port
711 * which can't process the following IDENTIFY after this will
712 * have to be reset again. For most cases, this should
713 * suffice while making probing snappish enough.
716 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
719 ahci_kick_engine(ap);
725 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
727 * It has been observed with some SSDs that the timing of events in the
728 * link synchronization phase can leave the port in a state that can not
729 * be recovered by a SATA-hard-reset alone. The failing signature is
730 * SStatus.DET stuck at 1 ("Device presence detected but Phy
731 * communication not established"). It was found that unloading and
732 * reloading the driver when this problem occurs allows the drive
733 * connection to be recovered (DET advanced to 0x3). The critical
734 * component of reloading the driver is that the port state machines are
735 * reset by bouncing "port enable" in the AHCI PCS configuration
736 * register. So, reproduce that effect by bouncing a port whenever we
737 * see DET==1 after a reset.
739 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
740 unsigned long deadline)
742 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
743 struct ata_port *ap = link->ap;
744 struct ahci_port_priv *pp = ap->private_data;
745 struct ahci_host_priv *hpriv = ap->host->private_data;
746 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
747 unsigned long tmo = deadline - jiffies;
748 struct ata_taskfile tf;
754 ahci_stop_engine(ap);
756 for (i = 0; i < 2; i++) {
759 int port = ap->port_no;
760 struct ata_host *host = ap->host;
761 struct pci_dev *pdev = to_pci_dev(host->dev);
763 /* clear D2H reception area to properly wait for D2H FIS */
764 ata_tf_init(link->device, &tf);
765 tf.command = ATA_BUSY;
766 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
768 rc = sata_link_hardreset(link, timing, deadline, &online,
771 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
772 (sstatus & 0xf) != 1)
775 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
778 pci_read_config_word(pdev, 0x92, &val);
780 pci_write_config_word(pdev, 0x92, val);
781 ata_msleep(ap, 1000);
783 pci_write_config_word(pdev, 0x92, val);
787 hpriv->start_engine(ap);
790 *class = ahci_dev_classify(ap);
792 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
798 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
800 struct ata_host *host = pci_get_drvdata(pdev);
801 struct ahci_host_priv *hpriv = host->private_data;
802 void __iomem *mmio = hpriv->mmio;
805 if (mesg.event & PM_EVENT_SUSPEND &&
806 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
808 "BIOS update required for suspend/resume\n");
812 if (mesg.event & PM_EVENT_SLEEP) {
813 /* AHCI spec rev1.1 section 8.3.3:
814 * Software must disable interrupts prior to requesting a
815 * transition of the HBA to D3 state.
817 ctl = readl(mmio + HOST_CTL);
819 writel(ctl, mmio + HOST_CTL);
820 readl(mmio + HOST_CTL); /* flush */
823 return ata_pci_device_suspend(pdev, mesg);
826 static int ahci_pci_device_resume(struct pci_dev *pdev)
828 struct ata_host *host = pci_get_drvdata(pdev);
831 rc = ata_pci_device_do_resume(pdev);
835 /* Apple BIOS helpfully mangles the registers on resume */
836 if (is_mcp89_apple(pdev))
837 ahci_mcp89_apple_enable(pdev);
839 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
840 rc = ahci_pci_reset_controller(host);
844 ahci_pci_init_controller(host);
847 ata_host_resume(host);
853 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
858 * If the device fixup already set the dma_mask to some non-standard
859 * value, don't extend it here. This happens on STA2X11, for example.
861 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
865 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
866 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
868 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
871 "64-bit DMA enable failed\n");
876 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
878 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
881 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
884 "32-bit consistent DMA enable failed\n");
891 static void ahci_pci_print_info(struct ata_host *host)
893 struct pci_dev *pdev = to_pci_dev(host->dev);
897 pci_read_config_word(pdev, 0x0a, &cc);
898 if (cc == PCI_CLASS_STORAGE_IDE)
900 else if (cc == PCI_CLASS_STORAGE_SATA)
902 else if (cc == PCI_CLASS_STORAGE_RAID)
907 ahci_print_info(host, scc_s);
910 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
911 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
912 * support PMP and the 4726 either directly exports the device
913 * attached to the first downstream port or acts as a hardware storage
914 * controller and emulate a single ATA device (can be RAID 0/1 or some
915 * other configuration).
917 * When there's no device attached to the first downstream port of the
918 * 4726, "Config Disk" appears, which is a pseudo ATA device to
919 * configure the 4726. However, ATA emulation of the device is very
920 * lame. It doesn't send signature D2H Reg FIS after the initial
921 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
923 * The following function works around the problem by always using
924 * hardreset on the port and not depending on receiving signature FIS
925 * afterward. If signature FIS isn't received soon, ATA class is
926 * assumed without follow-up softreset.
928 static void ahci_p5wdh_workaround(struct ata_host *host)
930 static const struct dmi_system_id sysids[] = {
932 .ident = "P5W DH Deluxe",
934 DMI_MATCH(DMI_SYS_VENDOR,
935 "ASUSTEK COMPUTER INC"),
936 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
941 struct pci_dev *pdev = to_pci_dev(host->dev);
943 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
944 dmi_check_system(sysids)) {
945 struct ata_port *ap = host->ports[1];
948 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
950 ap->ops = &ahci_p5wdh_ops;
951 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
956 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
957 * booting in BIOS compatibility mode. We restore the registers but not ID.
959 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
963 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
965 pci_read_config_dword(pdev, 0xf8, &val);
967 /* the following changes the device ID, but appears not to affect function */
968 /* val = (val & ~0xf0000000) | 0x80000000; */
969 pci_write_config_dword(pdev, 0xf8, val);
971 pci_read_config_dword(pdev, 0x54c, &val);
973 pci_write_config_dword(pdev, 0x54c, val);
975 pci_read_config_dword(pdev, 0x4a4, &val);
978 pci_write_config_dword(pdev, 0x4a4, val);
980 pci_read_config_dword(pdev, 0x54c, &val);
982 pci_write_config_dword(pdev, 0x54c, val);
984 pci_read_config_dword(pdev, 0xf8, &val);
986 pci_write_config_dword(pdev, 0xf8, val);
989 static bool is_mcp89_apple(struct pci_dev *pdev)
991 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
992 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
993 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
994 pdev->subsystem_device == 0xcb89;
997 /* only some SB600 ahci controllers can do 64bit DMA */
998 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1000 static const struct dmi_system_id sysids[] = {
1002 * The oldest version known to be broken is 0901 and
1003 * working is 1501 which was released on 2007-10-26.
1004 * Enable 64bit DMA on 1501 and anything newer.
1006 * Please read bko#9412 for more info.
1009 .ident = "ASUS M2A-VM",
1011 DMI_MATCH(DMI_BOARD_VENDOR,
1012 "ASUSTeK Computer INC."),
1013 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1015 .driver_data = "20071026", /* yyyymmdd */
1018 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1019 * support 64bit DMA.
1021 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1022 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1023 * This spelling mistake was fixed in BIOS version 1.5, so
1024 * 1.5 and later have the Manufacturer as
1025 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1026 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1028 * BIOS versions earlier than 1.9 had a Board Product Name
1029 * DMI field of "MS-7376". This was changed to be
1030 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1031 * match on DMI_BOARD_NAME of "MS-7376".
1034 .ident = "MSI K9A2 Platinum",
1036 DMI_MATCH(DMI_BOARD_VENDOR,
1037 "MICRO-STAR INTER"),
1038 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1042 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1045 * This board also had the typo mentioned above in the
1046 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1047 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1050 .ident = "MSI K9AGM2",
1052 DMI_MATCH(DMI_BOARD_VENDOR,
1053 "MICRO-STAR INTER"),
1054 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1058 * All BIOS versions for the Asus M3A support 64bit DMA.
1059 * (all release versions from 0301 to 1206 were tested)
1062 .ident = "ASUS M3A",
1064 DMI_MATCH(DMI_BOARD_VENDOR,
1065 "ASUSTeK Computer INC."),
1066 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1071 const struct dmi_system_id *match;
1072 int year, month, date;
1075 match = dmi_first_match(sysids);
1076 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1080 if (!match->driver_data)
1083 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1084 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1086 if (strcmp(buf, match->driver_data) >= 0)
1089 dev_warn(&pdev->dev,
1090 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1096 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1100 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1102 static const struct dmi_system_id broken_systems[] = {
1104 .ident = "HP Compaq nx6310",
1106 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1107 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1109 /* PCI slot number of the controller */
1110 .driver_data = (void *)0x1FUL,
1113 .ident = "HP Compaq 6720s",
1115 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1116 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1118 /* PCI slot number of the controller */
1119 .driver_data = (void *)0x1FUL,
1122 { } /* terminate list */
1124 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1127 unsigned long slot = (unsigned long)dmi->driver_data;
1128 /* apply the quirk only to on-board controllers */
1129 return slot == PCI_SLOT(pdev->devfn);
1135 static bool ahci_broken_suspend(struct pci_dev *pdev)
1137 static const struct dmi_system_id sysids[] = {
1139 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1140 * to the harddisk doesn't become online after
1141 * resuming from STR. Warn and fail suspend.
1143 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1145 * Use dates instead of versions to match as HP is
1146 * apparently recycling both product and version
1149 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1154 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1155 DMI_MATCH(DMI_PRODUCT_NAME,
1156 "HP Pavilion dv4 Notebook PC"),
1158 .driver_data = "20090105", /* F.30 */
1163 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1164 DMI_MATCH(DMI_PRODUCT_NAME,
1165 "HP Pavilion dv5 Notebook PC"),
1167 .driver_data = "20090506", /* F.16 */
1172 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1173 DMI_MATCH(DMI_PRODUCT_NAME,
1174 "HP Pavilion dv6 Notebook PC"),
1176 .driver_data = "20090423", /* F.21 */
1181 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1182 DMI_MATCH(DMI_PRODUCT_NAME,
1183 "HP HDX18 Notebook PC"),
1185 .driver_data = "20090430", /* F.23 */
1188 * Acer eMachines G725 has the same problem. BIOS
1189 * V1.03 is known to be broken. V3.04 is known to
1190 * work. Between, there are V1.06, V2.06 and V3.03
1191 * that we don't have much idea about. For now,
1192 * blacklist anything older than V3.04.
1194 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1199 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1200 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1202 .driver_data = "20091216", /* V3.04 */
1204 { } /* terminate list */
1206 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1207 int year, month, date;
1210 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1213 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1214 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1216 return strcmp(buf, dmi->driver_data) < 0;
1219 static bool ahci_broken_online(struct pci_dev *pdev)
1221 #define ENCODE_BUSDEVFN(bus, slot, func) \
1222 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1223 static const struct dmi_system_id sysids[] = {
1225 * There are several gigabyte boards which use
1226 * SIMG5723s configured as hardware RAID. Certain
1227 * 5723 firmware revisions shipped there keep the link
1228 * online but fail to answer properly to SRST or
1229 * IDENTIFY when no device is attached downstream
1230 * causing libata to retry quite a few times leading
1231 * to excessive detection delay.
1233 * As these firmwares respond to the second reset try
1234 * with invalid device signature, considering unknown
1235 * sig as offline works around the problem acceptably.
1238 .ident = "EP45-DQ6",
1240 DMI_MATCH(DMI_BOARD_VENDOR,
1241 "Gigabyte Technology Co., Ltd."),
1242 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1244 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1247 .ident = "EP45-DS5",
1249 DMI_MATCH(DMI_BOARD_VENDOR,
1250 "Gigabyte Technology Co., Ltd."),
1251 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1253 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1255 { } /* terminate list */
1257 #undef ENCODE_BUSDEVFN
1258 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1264 val = (unsigned long)dmi->driver_data;
1266 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1269 static bool ahci_broken_devslp(struct pci_dev *pdev)
1271 /* device with broken DEVSLP but still showing SDS capability */
1272 static const struct pci_device_id ids[] = {
1273 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1277 return pci_match_id(ids, pdev);
1280 #ifdef CONFIG_ATA_ACPI
1281 static void ahci_gtf_filter_workaround(struct ata_host *host)
1283 static const struct dmi_system_id sysids[] = {
1285 * Aspire 3810T issues a bunch of SATA enable commands
1286 * via _GTF including an invalid one and one which is
1287 * rejected by the device. Among the successful ones
1288 * is FPDMA non-zero offset enable which when enabled
1289 * only on the drive side leads to NCQ command
1290 * failures. Filter it out.
1293 .ident = "Aspire 3810T",
1295 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1296 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1298 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1302 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1303 unsigned int filter;
1309 filter = (unsigned long)dmi->driver_data;
1310 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1311 filter, dmi->ident);
1313 for (i = 0; i < host->n_ports; i++) {
1314 struct ata_port *ap = host->ports[i];
1315 struct ata_link *link;
1316 struct ata_device *dev;
1318 ata_for_each_link(link, ap, EDGE)
1319 ata_for_each_dev(dev, link, ALL)
1320 dev->gtf_filter |= filter;
1324 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1329 * ahci_init_msix() - optionally enable per-port MSI-X otherwise defer
1332 static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports,
1333 struct ahci_host_priv *hpriv, unsigned long flags)
1337 /* Do not init MSI-X if MSI is disabled for the device */
1338 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1341 nvec = pci_msix_vec_count(pdev);
1346 * Proper MSI-X implementations will have a vector per-port.
1347 * Barring that, we prefer single-MSI over single-MSIX. If this
1348 * check fails (not enough MSI-X vectors for all ports) we will
1349 * be called again with the flag clear iff ahci_init_msi()
1352 if (flags & AHCI_HFLAG_MULTI_MSIX) {
1360 * Emit dev_err() since this was the non-legacy irq
1361 * method of last resort.
1367 for (i = 0; i < nvec; i++)
1368 hpriv->msix[i].entry = i;
1369 rc = pci_enable_msix_exact(pdev, hpriv->msix, nvec);
1374 hpriv->flags |= AHCI_HFLAG_MULTI_MSIX;
1375 hpriv->irq = hpriv->msix[0].vector; /* for single msi-x */
1380 "failed to enable MSI-X with error %d, # of vectors: %d\n",
1386 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1387 struct ahci_host_priv *hpriv)
1391 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1394 nvec = pci_msi_vec_count(pdev);
1399 * If number of MSIs is less than number of ports then Sharing Last
1400 * Message mode could be enforced. In this case assume that advantage
1401 * of multipe MSIs is negated and use single MSI mode instead.
1406 rc = pci_enable_msi_exact(pdev, nvec);
1412 /* fallback to single MSI mode if the controller enforced MRSM mode */
1413 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1414 pci_disable_msi(pdev);
1415 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1420 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1427 rc = pci_enable_msi(pdev);
1431 hpriv->irq = pdev->irq;
1436 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1437 struct ahci_host_priv *hpriv)
1442 * Try to enable per-port MSI-X. If the host is not capable
1443 * fall back to single MSI before finally attempting single
1446 nvec = ahci_init_msix(pdev, n_ports, hpriv, AHCI_HFLAG_MULTI_MSIX);
1450 nvec = ahci_init_msi(pdev, n_ports, hpriv);
1454 /* try single-msix */
1455 nvec = ahci_init_msix(pdev, n_ports, hpriv, 0);
1459 /* legacy intx interrupts */
1461 hpriv->irq = pdev->irq;
1466 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1468 unsigned int board_id = ent->driver_data;
1469 struct ata_port_info pi = ahci_port_info[board_id];
1470 const struct ata_port_info *ppi[] = { &pi, NULL };
1471 struct device *dev = &pdev->dev;
1472 struct ahci_host_priv *hpriv;
1473 struct ata_host *host;
1475 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1479 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1481 ata_print_version_once(&pdev->dev, DRV_VERSION);
1483 /* The AHCI driver can only drive the SATA ports, the PATA driver
1484 can drive them all so if both drivers are selected make sure
1485 AHCI stays out of the way */
1486 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1489 /* Apple BIOS on MCP89 prevents us using AHCI */
1490 if (is_mcp89_apple(pdev))
1491 ahci_mcp89_apple_enable(pdev);
1493 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1494 * At the moment, we can only use the AHCI mode. Let the users know
1495 * that for SAS drives they're out of luck.
1497 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1498 dev_info(&pdev->dev,
1499 "PDC42819 can only drive SATA devices with this driver\n");
1501 /* Some devices use non-standard BARs */
1502 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1503 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1504 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1505 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1506 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1507 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1509 /* acquire resources */
1510 rc = pcim_enable_device(pdev);
1514 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1515 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1518 /* ICH6s share the same PCI ID for both piix and ahci
1519 * modes. Enabling ahci mode while MAP indicates
1520 * combined mode is a bad idea. Yield to ata_piix.
1522 pci_read_config_byte(pdev, ICH_MAP, &map);
1524 dev_info(&pdev->dev,
1525 "controller is in combined mode, can't enable AHCI mode\n");
1530 /* AHCI controllers often implement SFF compatible interface.
1531 * Grab all PCI BARs just in case.
1533 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1535 pcim_pin_device(pdev);
1539 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1542 hpriv->flags |= (unsigned long)pi.private_data;
1544 /* MCP65 revision A1 and A2 can't do MSI */
1545 if (board_id == board_ahci_mcp65 &&
1546 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1547 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1549 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1550 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1551 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1553 /* only some SB600s can do 64bit DMA */
1554 if (ahci_sb600_enable_64bit(pdev))
1555 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1557 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1559 /* must set flag prior to save config in order to take effect */
1560 if (ahci_broken_devslp(pdev))
1561 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1563 /* save initial config */
1564 ahci_pci_save_initial_config(pdev, hpriv);
1567 if (hpriv->cap & HOST_CAP_NCQ) {
1568 pi.flags |= ATA_FLAG_NCQ;
1570 * Auto-activate optimization is supposed to be
1571 * supported on all AHCI controllers indicating NCQ
1572 * capability, but it seems to be broken on some
1573 * chipsets including NVIDIAs.
1575 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1576 pi.flags |= ATA_FLAG_FPDMA_AA;
1579 * All AHCI controllers should be forward-compatible
1580 * with the new auxiliary field. This code should be
1581 * conditionalized if any buggy AHCI controllers are
1584 pi.flags |= ATA_FLAG_FPDMA_AUX;
1587 if (hpriv->cap & HOST_CAP_PMP)
1588 pi.flags |= ATA_FLAG_PMP;
1590 ahci_set_em_messages(hpriv, &pi);
1592 if (ahci_broken_system_poweroff(pdev)) {
1593 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1594 dev_info(&pdev->dev,
1595 "quirky BIOS, skipping spindown on poweroff\n");
1598 if (ahci_broken_suspend(pdev)) {
1599 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1600 dev_warn(&pdev->dev,
1601 "BIOS update required for suspend/resume\n");
1604 if (ahci_broken_online(pdev)) {
1605 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1606 dev_info(&pdev->dev,
1607 "online status unreliable, applying workaround\n");
1610 /* CAP.NP sometimes indicate the index of the last enabled
1611 * port, at other times, that of the last possible port, so
1612 * determining the maximum port number requires looking at
1613 * both CAP.NP and port_map.
1615 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1617 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1620 host->private_data = hpriv;
1621 hpriv->msix = devm_kzalloc(&pdev->dev,
1622 sizeof(struct msix_entry) * n_ports, GFP_KERNEL);
1625 ahci_init_interrupts(pdev, n_ports, hpriv);
1627 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1628 host->flags |= ATA_HOST_PARALLEL_SCAN;
1630 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1632 if (pi.flags & ATA_FLAG_EM)
1633 ahci_reset_em(host);
1635 for (i = 0; i < host->n_ports; i++) {
1636 struct ata_port *ap = host->ports[i];
1638 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1639 ata_port_pbar_desc(ap, ahci_pci_bar,
1640 0x100 + ap->port_no * 0x80, "port");
1642 /* set enclosure management message type */
1643 if (ap->flags & ATA_FLAG_EM)
1644 ap->em_message_type = hpriv->em_msg_type;
1647 /* disabled/not-implemented port */
1648 if (!(hpriv->port_map & (1 << i)))
1649 ap->ops = &ata_dummy_port_ops;
1652 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1653 ahci_p5wdh_workaround(host);
1655 /* apply gtf filter quirk */
1656 ahci_gtf_filter_workaround(host);
1658 /* initialize adapter */
1659 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1663 rc = ahci_pci_reset_controller(host);
1667 ahci_pci_init_controller(host);
1668 ahci_pci_print_info(host);
1670 pci_set_master(pdev);
1672 return ahci_host_activate(host, &ahci_sht);
1675 module_pci_driver(ahci_pci_driver);
1677 MODULE_AUTHOR("Jeff Garzik");
1678 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1679 MODULE_LICENSE("GPL");
1680 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1681 MODULE_VERSION(DRV_VERSION);