2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "2.0"
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
82 board_ahci_vt8251 = 2,
83 board_ahci_ign_iferr = 3,
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
158 PORT_CMD_CLO = (1 << 3), /* Command list override */
159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
169 AHCI_FLAG_NO_NCQ = (1 << 24),
170 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
171 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
174 struct ahci_cmd_hdr {
189 struct ahci_host_priv {
190 u32 cap; /* cache of HOST_CAP register */
191 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
194 struct ahci_port_priv {
195 struct ahci_cmd_hdr *cmd_slot;
196 dma_addr_t cmd_slot_dma;
198 dma_addr_t cmd_tbl_dma;
200 dma_addr_t rx_fis_dma;
201 /* for NCQ spurious interrupt analysis */
202 int ncq_saw_spurious_sdb_cnt;
203 unsigned int ncq_saw_d2h:1;
204 unsigned int ncq_saw_dmas:1;
207 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
208 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
209 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
210 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
211 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
212 static void ahci_irq_clear(struct ata_port *ap);
213 static int ahci_port_start(struct ata_port *ap);
214 static void ahci_port_stop(struct ata_port *ap);
215 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
216 static void ahci_qc_prep(struct ata_queued_cmd *qc);
217 static u8 ahci_check_status(struct ata_port *ap);
218 static void ahci_freeze(struct ata_port *ap);
219 static void ahci_thaw(struct ata_port *ap);
220 static void ahci_error_handler(struct ata_port *ap);
221 static void ahci_vt8251_error_handler(struct ata_port *ap);
222 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
223 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
224 static int ahci_port_resume(struct ata_port *ap);
225 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
226 static int ahci_pci_device_resume(struct pci_dev *pdev);
228 static struct scsi_host_template ahci_sht = {
229 .module = THIS_MODULE,
231 .ioctl = ata_scsi_ioctl,
232 .queuecommand = ata_scsi_queuecmd,
233 .change_queue_depth = ata_scsi_change_queue_depth,
234 .can_queue = AHCI_MAX_CMDS - 1,
235 .this_id = ATA_SHT_THIS_ID,
236 .sg_tablesize = AHCI_MAX_SG,
237 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
238 .emulated = ATA_SHT_EMULATED,
239 .use_clustering = AHCI_USE_CLUSTERING,
240 .proc_name = DRV_NAME,
241 .dma_boundary = AHCI_DMA_BOUNDARY,
242 .slave_configure = ata_scsi_slave_config,
243 .slave_destroy = ata_scsi_slave_destroy,
244 .bios_param = ata_std_bios_param,
245 .suspend = ata_scsi_device_suspend,
246 .resume = ata_scsi_device_resume,
249 static const struct ata_port_operations ahci_ops = {
250 .port_disable = ata_port_disable,
252 .check_status = ahci_check_status,
253 .check_altstatus = ahci_check_status,
254 .dev_select = ata_noop_dev_select,
256 .tf_read = ahci_tf_read,
258 .qc_prep = ahci_qc_prep,
259 .qc_issue = ahci_qc_issue,
261 .irq_handler = ahci_interrupt,
262 .irq_clear = ahci_irq_clear,
263 .irq_on = ata_dummy_irq_on,
264 .irq_ack = ata_dummy_irq_ack,
266 .scr_read = ahci_scr_read,
267 .scr_write = ahci_scr_write,
269 .freeze = ahci_freeze,
272 .error_handler = ahci_error_handler,
273 .post_internal_cmd = ahci_post_internal_cmd,
275 .port_suspend = ahci_port_suspend,
276 .port_resume = ahci_port_resume,
278 .port_start = ahci_port_start,
279 .port_stop = ahci_port_stop,
282 static const struct ata_port_operations ahci_vt8251_ops = {
283 .port_disable = ata_port_disable,
285 .check_status = ahci_check_status,
286 .check_altstatus = ahci_check_status,
287 .dev_select = ata_noop_dev_select,
289 .tf_read = ahci_tf_read,
291 .qc_prep = ahci_qc_prep,
292 .qc_issue = ahci_qc_issue,
294 .irq_handler = ahci_interrupt,
295 .irq_clear = ahci_irq_clear,
296 .irq_on = ata_dummy_irq_on,
297 .irq_ack = ata_dummy_irq_ack,
299 .scr_read = ahci_scr_read,
300 .scr_write = ahci_scr_write,
302 .freeze = ahci_freeze,
305 .error_handler = ahci_vt8251_error_handler,
306 .post_internal_cmd = ahci_post_internal_cmd,
308 .port_suspend = ahci_port_suspend,
309 .port_resume = ahci_port_resume,
311 .port_start = ahci_port_start,
312 .port_stop = ahci_port_stop,
315 static const struct ata_port_info ahci_port_info[] = {
319 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
320 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
321 ATA_FLAG_SKIP_D2H_BSY,
322 .pio_mask = 0x1f, /* pio0-4 */
323 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
324 .port_ops = &ahci_ops,
329 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
330 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
331 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
332 .pio_mask = 0x1f, /* pio0-4 */
333 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
334 .port_ops = &ahci_ops,
336 /* board_ahci_vt8251 */
339 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
340 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
341 ATA_FLAG_SKIP_D2H_BSY |
342 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
343 .pio_mask = 0x1f, /* pio0-4 */
344 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
345 .port_ops = &ahci_vt8251_ops,
347 /* board_ahci_ign_iferr */
350 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
351 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
352 ATA_FLAG_SKIP_D2H_BSY |
353 AHCI_FLAG_IGN_IRQ_IF_ERR,
354 .pio_mask = 0x1f, /* pio0-4 */
355 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
356 .port_ops = &ahci_ops,
360 static const struct pci_device_id ahci_pci_tbl[] = {
362 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
363 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
364 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
365 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
366 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
367 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
368 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
369 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
370 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
371 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
372 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
373 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
374 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
375 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
376 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
377 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
378 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
379 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
380 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
381 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
382 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
383 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
384 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
385 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
386 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
387 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
390 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
391 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
392 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
393 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
394 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
397 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
398 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
401 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
404 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
405 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
406 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
407 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
408 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
409 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
410 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
411 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
412 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
413 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
414 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
415 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
416 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
417 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
426 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
427 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
428 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
430 /* Generic, PCI class code for AHCI */
431 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
432 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
434 { } /* terminate list */
438 static struct pci_driver ahci_pci_driver = {
440 .id_table = ahci_pci_tbl,
441 .probe = ahci_init_one,
442 .remove = ata_pci_remove_one,
443 .suspend = ahci_pci_device_suspend,
444 .resume = ahci_pci_device_resume,
448 static inline int ahci_nr_ports(u32 cap)
450 return (cap & 0x1f) + 1;
453 static inline void __iomem *ahci_port_base(void __iomem *base,
456 return base + 0x100 + (port * 0x80);
459 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
464 case SCR_STATUS: sc_reg = 0; break;
465 case SCR_CONTROL: sc_reg = 1; break;
466 case SCR_ERROR: sc_reg = 2; break;
467 case SCR_ACTIVE: sc_reg = 3; break;
472 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
476 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
482 case SCR_STATUS: sc_reg = 0; break;
483 case SCR_CONTROL: sc_reg = 1; break;
484 case SCR_ERROR: sc_reg = 2; break;
485 case SCR_ACTIVE: sc_reg = 3; break;
490 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
493 static void ahci_start_engine(void __iomem *port_mmio)
498 tmp = readl(port_mmio + PORT_CMD);
499 tmp |= PORT_CMD_START;
500 writel(tmp, port_mmio + PORT_CMD);
501 readl(port_mmio + PORT_CMD); /* flush */
504 static int ahci_stop_engine(void __iomem *port_mmio)
508 tmp = readl(port_mmio + PORT_CMD);
510 /* check if the HBA is idle */
511 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
514 /* setting HBA to idle */
515 tmp &= ~PORT_CMD_START;
516 writel(tmp, port_mmio + PORT_CMD);
518 /* wait for engine to stop. This could be as long as 500 msec */
519 tmp = ata_wait_register(port_mmio + PORT_CMD,
520 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
521 if (tmp & PORT_CMD_LIST_ON)
527 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
528 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
532 /* set FIS registers */
533 if (cap & HOST_CAP_64)
534 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
535 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
537 if (cap & HOST_CAP_64)
538 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
539 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
541 /* enable FIS reception */
542 tmp = readl(port_mmio + PORT_CMD);
543 tmp |= PORT_CMD_FIS_RX;
544 writel(tmp, port_mmio + PORT_CMD);
547 readl(port_mmio + PORT_CMD);
550 static int ahci_stop_fis_rx(void __iomem *port_mmio)
554 /* disable FIS reception */
555 tmp = readl(port_mmio + PORT_CMD);
556 tmp &= ~PORT_CMD_FIS_RX;
557 writel(tmp, port_mmio + PORT_CMD);
559 /* wait for completion, spec says 500ms, give it 1000 */
560 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
561 PORT_CMD_FIS_ON, 10, 1000);
562 if (tmp & PORT_CMD_FIS_ON)
568 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
572 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
575 if (cap & HOST_CAP_SSS) {
576 cmd |= PORT_CMD_SPIN_UP;
577 writel(cmd, port_mmio + PORT_CMD);
581 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
584 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
588 if (!(cap & HOST_CAP_SSS))
591 /* put device into listen mode, first set PxSCTL.DET to 0 */
592 scontrol = readl(port_mmio + PORT_SCR_CTL);
594 writel(scontrol, port_mmio + PORT_SCR_CTL);
596 /* then set PxCMD.SUD to 0 */
597 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
598 cmd &= ~PORT_CMD_SPIN_UP;
599 writel(cmd, port_mmio + PORT_CMD);
602 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
603 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
605 /* enable FIS reception */
606 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
609 ahci_start_engine(port_mmio);
612 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
617 rc = ahci_stop_engine(port_mmio);
619 *emsg = "failed to stop engine";
623 /* disable FIS reception */
624 rc = ahci_stop_fis_rx(port_mmio);
626 *emsg = "failed stop FIS RX";
633 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
635 u32 cap_save, impl_save, tmp;
637 cap_save = readl(mmio + HOST_CAP);
638 impl_save = readl(mmio + HOST_PORTS_IMPL);
640 /* global controller reset */
641 tmp = readl(mmio + HOST_CTL);
642 if ((tmp & HOST_RESET) == 0) {
643 writel(tmp | HOST_RESET, mmio + HOST_CTL);
644 readl(mmio + HOST_CTL); /* flush */
647 /* reset must complete within 1 second, or
648 * the hardware should be considered fried.
652 tmp = readl(mmio + HOST_CTL);
653 if (tmp & HOST_RESET) {
654 dev_printk(KERN_ERR, &pdev->dev,
655 "controller reset failed (0x%x)\n", tmp);
659 /* turn on AHCI mode */
660 writel(HOST_AHCI_EN, mmio + HOST_CTL);
661 (void) readl(mmio + HOST_CTL); /* flush */
663 /* These write-once registers are normally cleared on reset.
664 * Restore BIOS values... which we HOPE were present before
668 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
669 dev_printk(KERN_WARNING, &pdev->dev,
670 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
672 writel(cap_save, mmio + HOST_CAP);
673 writel(impl_save, mmio + HOST_PORTS_IMPL);
674 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
676 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
680 pci_read_config_word(pdev, 0x92, &tmp16);
682 pci_write_config_word(pdev, 0x92, tmp16);
688 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
689 int n_ports, unsigned int port_flags,
690 struct ahci_host_priv *hpriv)
695 for (i = 0; i < n_ports; i++) {
696 void __iomem *port_mmio = ahci_port_base(mmio, i);
697 const char *emsg = NULL;
699 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
700 !(hpriv->port_map & (1 << i)))
703 /* make sure port is not active */
704 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
706 dev_printk(KERN_WARNING, &pdev->dev,
707 "%s (%d)\n", emsg, rc);
710 tmp = readl(port_mmio + PORT_SCR_ERR);
711 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
712 writel(tmp, port_mmio + PORT_SCR_ERR);
715 tmp = readl(port_mmio + PORT_IRQ_STAT);
716 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
718 writel(tmp, port_mmio + PORT_IRQ_STAT);
720 writel(1 << i, mmio + HOST_IRQ_STAT);
723 tmp = readl(mmio + HOST_CTL);
724 VPRINTK("HOST_CTL 0x%x\n", tmp);
725 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
726 tmp = readl(mmio + HOST_CTL);
727 VPRINTK("HOST_CTL 0x%x\n", tmp);
730 static unsigned int ahci_dev_classify(struct ata_port *ap)
732 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
733 struct ata_taskfile tf;
736 tmp = readl(port_mmio + PORT_SIG);
737 tf.lbah = (tmp >> 24) & 0xff;
738 tf.lbam = (tmp >> 16) & 0xff;
739 tf.lbal = (tmp >> 8) & 0xff;
740 tf.nsect = (tmp) & 0xff;
742 return ata_dev_classify(&tf);
745 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
748 dma_addr_t cmd_tbl_dma;
750 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
752 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
753 pp->cmd_slot[tag].status = 0;
754 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
755 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
758 static int ahci_clo(struct ata_port *ap)
760 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
761 struct ahci_host_priv *hpriv = ap->host->private_data;
764 if (!(hpriv->cap & HOST_CAP_CLO))
767 tmp = readl(port_mmio + PORT_CMD);
769 writel(tmp, port_mmio + PORT_CMD);
771 tmp = ata_wait_register(port_mmio + PORT_CMD,
772 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
773 if (tmp & PORT_CMD_CLO)
779 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
781 struct ahci_port_priv *pp = ap->private_data;
782 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
783 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
784 const u32 cmd_fis_len = 5; /* five dwords */
785 const char *reason = NULL;
786 struct ata_taskfile tf;
793 if (ata_port_offline(ap)) {
794 DPRINTK("PHY reports no device\n");
795 *class = ATA_DEV_NONE;
799 /* prepare for SRST (AHCI-1.1 10.4.1) */
800 rc = ahci_stop_engine(port_mmio);
802 reason = "failed to stop engine";
806 /* check BUSY/DRQ, perform Command List Override if necessary */
807 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
810 if (rc == -EOPNOTSUPP) {
811 reason = "port busy but CLO unavailable";
814 reason = "port busy but CLO failed";
820 ahci_start_engine(port_mmio);
822 ata_tf_init(ap->device, &tf);
825 /* issue the first D2H Register FIS */
826 ahci_fill_cmd_slot(pp, 0,
827 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
830 ata_tf_to_fis(&tf, fis, 0);
831 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
833 writel(1, port_mmio + PORT_CMD_ISSUE);
835 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
838 reason = "1st FIS failed";
842 /* spec says at least 5us, but be generous and sleep for 1ms */
845 /* issue the second D2H Register FIS */
846 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
849 ata_tf_to_fis(&tf, fis, 0);
850 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
852 writel(1, port_mmio + PORT_CMD_ISSUE);
853 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
855 /* spec mandates ">= 2ms" before checking status.
856 * We wait 150ms, because that was the magic delay used for
857 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
858 * between when the ATA command register is written, and then
859 * status is checked. Because waiting for "a while" before
860 * checking status is fine, post SRST, we perform this magic
861 * delay here as well.
865 *class = ATA_DEV_NONE;
866 if (ata_port_online(ap)) {
867 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
869 reason = "device not ready";
872 *class = ahci_dev_classify(ap);
875 DPRINTK("EXIT, class=%u\n", *class);
879 ahci_start_engine(port_mmio);
881 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
885 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
887 struct ahci_port_priv *pp = ap->private_data;
888 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
889 struct ata_taskfile tf;
890 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
891 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
896 ahci_stop_engine(port_mmio);
898 /* clear D2H reception area to properly wait for D2H FIS */
899 ata_tf_init(ap->device, &tf);
901 ata_tf_to_fis(&tf, d2h_fis, 0);
903 rc = sata_std_hardreset(ap, class);
905 ahci_start_engine(port_mmio);
907 if (rc == 0 && ata_port_online(ap))
908 *class = ahci_dev_classify(ap);
909 if (*class == ATA_DEV_UNKNOWN)
910 *class = ATA_DEV_NONE;
912 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
916 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
918 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
919 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
924 ahci_stop_engine(port_mmio);
926 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
928 /* vt8251 needs SError cleared for the port to operate */
929 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
931 ahci_start_engine(port_mmio);
933 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
935 /* vt8251 doesn't clear BSY on signature FIS reception,
936 * request follow-up softreset.
938 return rc ?: -EAGAIN;
941 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
943 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
946 ata_std_postreset(ap, class);
948 /* Make sure port's ATAPI bit is set appropriately */
949 new_tmp = tmp = readl(port_mmio + PORT_CMD);
950 if (*class == ATA_DEV_ATAPI)
951 new_tmp |= PORT_CMD_ATAPI;
953 new_tmp &= ~PORT_CMD_ATAPI;
954 if (new_tmp != tmp) {
955 writel(new_tmp, port_mmio + PORT_CMD);
956 readl(port_mmio + PORT_CMD); /* flush */
960 static u8 ahci_check_status(struct ata_port *ap)
962 void __iomem *mmio = ap->ioaddr.cmd_addr;
964 return readl(mmio + PORT_TFDATA) & 0xFF;
967 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
969 struct ahci_port_priv *pp = ap->private_data;
970 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
972 ata_tf_from_fis(d2h_fis, tf);
975 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
977 struct scatterlist *sg;
978 struct ahci_sg *ahci_sg;
979 unsigned int n_sg = 0;
984 * Next, the S/G list.
986 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
987 ata_for_each_sg(sg, qc) {
988 dma_addr_t addr = sg_dma_address(sg);
989 u32 sg_len = sg_dma_len(sg);
991 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
992 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
993 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1002 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1004 struct ata_port *ap = qc->ap;
1005 struct ahci_port_priv *pp = ap->private_data;
1006 int is_atapi = is_atapi_taskfile(&qc->tf);
1009 const u32 cmd_fis_len = 5; /* five dwords */
1010 unsigned int n_elem;
1013 * Fill in command table information. First, the header,
1014 * a SATA Register - Host to Device command FIS.
1016 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1018 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1020 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1021 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1025 if (qc->flags & ATA_QCFLAG_DMAMAP)
1026 n_elem = ahci_fill_sg(qc, cmd_tbl);
1029 * Fill in command slot information.
1031 opts = cmd_fis_len | n_elem << 16;
1032 if (qc->tf.flags & ATA_TFLAG_WRITE)
1033 opts |= AHCI_CMD_WRITE;
1035 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1037 ahci_fill_cmd_slot(pp, qc->tag, opts);
1040 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1042 struct ahci_port_priv *pp = ap->private_data;
1043 struct ata_eh_info *ehi = &ap->eh_info;
1044 unsigned int err_mask = 0, action = 0;
1045 struct ata_queued_cmd *qc;
1048 ata_ehi_clear_desc(ehi);
1050 /* AHCI needs SError cleared; otherwise, it might lock up */
1051 serror = ahci_scr_read(ap, SCR_ERROR);
1052 ahci_scr_write(ap, SCR_ERROR, serror);
1054 /* analyze @irq_stat */
1055 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1057 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1058 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1059 irq_stat &= ~PORT_IRQ_IF_ERR;
1061 if (irq_stat & PORT_IRQ_TF_ERR)
1062 err_mask |= AC_ERR_DEV;
1064 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1065 err_mask |= AC_ERR_HOST_BUS;
1066 action |= ATA_EH_SOFTRESET;
1069 if (irq_stat & PORT_IRQ_IF_ERR) {
1070 err_mask |= AC_ERR_ATA_BUS;
1071 action |= ATA_EH_SOFTRESET;
1072 ata_ehi_push_desc(ehi, ", interface fatal error");
1075 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1076 ata_ehi_hotplugged(ehi);
1077 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1078 "connection status changed" : "PHY RDY changed");
1081 if (irq_stat & PORT_IRQ_UNK_FIS) {
1082 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1084 err_mask |= AC_ERR_HSM;
1085 action |= ATA_EH_SOFTRESET;
1086 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1087 unk[0], unk[1], unk[2], unk[3]);
1090 /* okay, let's hand over to EH */
1091 ehi->serror |= serror;
1092 ehi->action |= action;
1094 qc = ata_qc_from_tag(ap, ap->active_tag);
1096 qc->err_mask |= err_mask;
1098 ehi->err_mask |= err_mask;
1100 if (irq_stat & PORT_IRQ_FREEZE)
1101 ata_port_freeze(ap);
1106 static void ahci_host_intr(struct ata_port *ap)
1108 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1109 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1110 struct ata_eh_info *ehi = &ap->eh_info;
1111 struct ahci_port_priv *pp = ap->private_data;
1112 u32 status, qc_active;
1113 int rc, known_irq = 0;
1115 status = readl(port_mmio + PORT_IRQ_STAT);
1116 writel(status, port_mmio + PORT_IRQ_STAT);
1118 if (unlikely(status & PORT_IRQ_ERROR)) {
1119 ahci_error_intr(ap, status);
1124 qc_active = readl(port_mmio + PORT_SCR_ACT);
1126 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1128 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1132 ehi->err_mask |= AC_ERR_HSM;
1133 ehi->action |= ATA_EH_SOFTRESET;
1134 ata_port_freeze(ap);
1138 /* hmmm... a spurious interupt */
1140 /* if !NCQ, ignore. No modern ATA device has broken HSM
1141 * implementation for non-NCQ commands.
1146 if (status & PORT_IRQ_D2H_REG_FIS) {
1147 if (!pp->ncq_saw_d2h)
1148 ata_port_printk(ap, KERN_INFO,
1149 "D2H reg with I during NCQ, "
1150 "this message won't be printed again\n");
1151 pp->ncq_saw_d2h = 1;
1155 if (status & PORT_IRQ_DMAS_FIS) {
1156 if (!pp->ncq_saw_dmas)
1157 ata_port_printk(ap, KERN_INFO,
1158 "DMAS FIS during NCQ, "
1159 "this message won't be printed again\n");
1160 pp->ncq_saw_dmas = 1;
1164 if (status & PORT_IRQ_SDB_FIS &&
1165 pp->ncq_saw_spurious_sdb_cnt < 10) {
1166 /* SDB FIS containing spurious completions might be
1167 * dangerous, we need to know more about them. Print
1170 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1172 ata_port_printk(ap, KERN_INFO, "Spurious SDB FIS during NCQ "
1173 "issue=0x%x SAct=0x%x FIS=%08x:%08x%s\n",
1174 readl(port_mmio + PORT_CMD_ISSUE),
1175 readl(port_mmio + PORT_SCR_ACT),
1176 le32_to_cpu(f[0]), le32_to_cpu(f[1]),
1177 pp->ncq_saw_spurious_sdb_cnt < 10 ?
1178 "" : ", shutting up");
1180 pp->ncq_saw_spurious_sdb_cnt++;
1185 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1186 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1187 status, ap->active_tag, ap->sactive);
1190 static void ahci_irq_clear(struct ata_port *ap)
1195 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1197 struct ata_host *host = dev_instance;
1198 struct ahci_host_priv *hpriv;
1199 unsigned int i, handled = 0;
1201 u32 irq_stat, irq_ack = 0;
1205 hpriv = host->private_data;
1206 mmio = host->iomap[AHCI_PCI_BAR];
1208 /* sigh. 0xffffffff is a valid return from h/w */
1209 irq_stat = readl(mmio + HOST_IRQ_STAT);
1210 irq_stat &= hpriv->port_map;
1214 spin_lock(&host->lock);
1216 for (i = 0; i < host->n_ports; i++) {
1217 struct ata_port *ap;
1219 if (!(irq_stat & (1 << i)))
1222 ap = host->ports[i];
1225 VPRINTK("port %u\n", i);
1227 VPRINTK("port %u (no irq)\n", i);
1228 if (ata_ratelimit())
1229 dev_printk(KERN_WARNING, host->dev,
1230 "interrupt on disabled port %u\n", i);
1233 irq_ack |= (1 << i);
1237 writel(irq_ack, mmio + HOST_IRQ_STAT);
1241 spin_unlock(&host->lock);
1245 return IRQ_RETVAL(handled);
1248 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1250 struct ata_port *ap = qc->ap;
1251 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1253 if (qc->tf.protocol == ATA_PROT_NCQ)
1254 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1255 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1256 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1261 static void ahci_freeze(struct ata_port *ap)
1263 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1264 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1267 writel(0, port_mmio + PORT_IRQ_MASK);
1270 static void ahci_thaw(struct ata_port *ap)
1272 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1273 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1277 tmp = readl(port_mmio + PORT_IRQ_STAT);
1278 writel(tmp, port_mmio + PORT_IRQ_STAT);
1279 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1281 /* turn IRQ back on */
1282 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1285 static void ahci_error_handler(struct ata_port *ap)
1287 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1288 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1290 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1291 /* restart engine */
1292 ahci_stop_engine(port_mmio);
1293 ahci_start_engine(port_mmio);
1296 /* perform recovery */
1297 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1301 static void ahci_vt8251_error_handler(struct ata_port *ap)
1303 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1304 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1306 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1307 /* restart engine */
1308 ahci_stop_engine(port_mmio);
1309 ahci_start_engine(port_mmio);
1312 /* perform recovery */
1313 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1317 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1319 struct ata_port *ap = qc->ap;
1320 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1321 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1323 if (qc->flags & ATA_QCFLAG_FAILED)
1324 qc->err_mask |= AC_ERR_OTHER;
1327 /* make DMA engine forget about the failed command */
1328 ahci_stop_engine(port_mmio);
1329 ahci_start_engine(port_mmio);
1333 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1335 struct ahci_host_priv *hpriv = ap->host->private_data;
1336 struct ahci_port_priv *pp = ap->private_data;
1337 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1338 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1339 const char *emsg = NULL;
1342 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1344 ahci_power_down(port_mmio, hpriv->cap);
1346 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1347 ahci_init_port(port_mmio, hpriv->cap,
1348 pp->cmd_slot_dma, pp->rx_fis_dma);
1354 static int ahci_port_resume(struct ata_port *ap)
1356 struct ahci_port_priv *pp = ap->private_data;
1357 struct ahci_host_priv *hpriv = ap->host->private_data;
1358 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1359 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1361 ahci_power_up(port_mmio, hpriv->cap);
1362 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1367 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1369 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1370 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1373 if (mesg.event == PM_EVENT_SUSPEND) {
1374 /* AHCI spec rev1.1 section 8.3.3:
1375 * Software must disable interrupts prior to requesting a
1376 * transition of the HBA to D3 state.
1378 ctl = readl(mmio + HOST_CTL);
1379 ctl &= ~HOST_IRQ_EN;
1380 writel(ctl, mmio + HOST_CTL);
1381 readl(mmio + HOST_CTL); /* flush */
1384 return ata_pci_device_suspend(pdev, mesg);
1387 static int ahci_pci_device_resume(struct pci_dev *pdev)
1389 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1390 struct ahci_host_priv *hpriv = host->private_data;
1391 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1394 rc = ata_pci_device_do_resume(pdev);
1398 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1399 rc = ahci_reset_controller(mmio, pdev);
1403 ahci_init_controller(mmio, pdev, host->n_ports,
1404 host->ports[0]->flags, hpriv);
1407 ata_host_resume(host);
1412 static int ahci_port_start(struct ata_port *ap)
1414 struct device *dev = ap->host->dev;
1415 struct ahci_host_priv *hpriv = ap->host->private_data;
1416 struct ahci_port_priv *pp;
1417 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1418 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1423 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1427 rc = ata_pad_alloc(ap, dev);
1431 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1435 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1438 * First item in chunk of DMA memory: 32-slot command table,
1439 * 32 bytes each in size
1442 pp->cmd_slot_dma = mem_dma;
1444 mem += AHCI_CMD_SLOT_SZ;
1445 mem_dma += AHCI_CMD_SLOT_SZ;
1448 * Second item: Received-FIS area
1451 pp->rx_fis_dma = mem_dma;
1453 mem += AHCI_RX_FIS_SZ;
1454 mem_dma += AHCI_RX_FIS_SZ;
1457 * Third item: data area for storing a single command
1458 * and its scatter-gather table
1461 pp->cmd_tbl_dma = mem_dma;
1463 ap->private_data = pp;
1466 ahci_power_up(port_mmio, hpriv->cap);
1468 /* initialize port */
1469 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1474 static void ahci_port_stop(struct ata_port *ap)
1476 struct ahci_host_priv *hpriv = ap->host->private_data;
1477 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1478 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1479 const char *emsg = NULL;
1482 /* de-initialize port */
1483 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1485 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1488 static void ahci_setup_port(struct ata_ioports *port, void __iomem *base,
1489 unsigned int port_idx)
1491 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1492 base = ahci_port_base(base, port_idx);
1493 VPRINTK("base now==0x%lx\n", base);
1495 port->cmd_addr = base;
1496 port->scr_addr = base + PORT_SCR;
1501 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1503 struct ahci_host_priv *hpriv = probe_ent->private_data;
1504 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1505 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1506 unsigned int i, cap_n_ports, using_dac;
1509 rc = ahci_reset_controller(mmio, pdev);
1513 hpriv->cap = readl(mmio + HOST_CAP);
1514 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1515 cap_n_ports = ahci_nr_ports(hpriv->cap);
1517 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1518 hpriv->cap, hpriv->port_map, cap_n_ports);
1520 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
1521 unsigned int n_ports = cap_n_ports;
1522 u32 port_map = hpriv->port_map;
1525 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
1526 if (port_map & (1 << i)) {
1528 port_map &= ~(1 << i);
1531 probe_ent->dummy_port_mask |= 1 << i;
1534 if (n_ports || port_map)
1535 dev_printk(KERN_WARNING, &pdev->dev,
1536 "nr_ports (%u) and implemented port map "
1537 "(0x%x) don't match\n",
1538 cap_n_ports, hpriv->port_map);
1540 probe_ent->n_ports = max_port + 1;
1542 probe_ent->n_ports = cap_n_ports;
1544 using_dac = hpriv->cap & HOST_CAP_64;
1546 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1547 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1549 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1551 dev_printk(KERN_ERR, &pdev->dev,
1552 "64-bit DMA enable failed\n");
1557 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1559 dev_printk(KERN_ERR, &pdev->dev,
1560 "32-bit DMA enable failed\n");
1563 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1565 dev_printk(KERN_ERR, &pdev->dev,
1566 "32-bit consistent DMA enable failed\n");
1571 for (i = 0; i < probe_ent->n_ports; i++)
1572 ahci_setup_port(&probe_ent->port[i], mmio, i);
1574 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1575 probe_ent->port_flags, hpriv);
1577 pci_set_master(pdev);
1582 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1584 struct ahci_host_priv *hpriv = probe_ent->private_data;
1585 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1586 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1587 u32 vers, cap, impl, speed;
1588 const char *speed_s;
1592 vers = readl(mmio + HOST_VERSION);
1594 impl = hpriv->port_map;
1596 speed = (cap >> 20) & 0xf;
1599 else if (speed == 2)
1604 pci_read_config_word(pdev, 0x0a, &cc);
1605 if (cc == PCI_CLASS_STORAGE_IDE)
1607 else if (cc == PCI_CLASS_STORAGE_SATA)
1609 else if (cc == PCI_CLASS_STORAGE_RAID)
1614 dev_printk(KERN_INFO, &pdev->dev,
1615 "AHCI %02x%02x.%02x%02x "
1616 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1619 (vers >> 24) & 0xff,
1620 (vers >> 16) & 0xff,
1624 ((cap >> 8) & 0x1f) + 1,
1630 dev_printk(KERN_INFO, &pdev->dev,
1636 cap & (1 << 31) ? "64bit " : "",
1637 cap & (1 << 30) ? "ncq " : "",
1638 cap & (1 << 28) ? "ilck " : "",
1639 cap & (1 << 27) ? "stag " : "",
1640 cap & (1 << 26) ? "pm " : "",
1641 cap & (1 << 25) ? "led " : "",
1643 cap & (1 << 24) ? "clo " : "",
1644 cap & (1 << 19) ? "nz " : "",
1645 cap & (1 << 18) ? "only " : "",
1646 cap & (1 << 17) ? "pmp " : "",
1647 cap & (1 << 15) ? "pio " : "",
1648 cap & (1 << 14) ? "slum " : "",
1649 cap & (1 << 13) ? "part " : ""
1653 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1655 static int printed_version;
1656 unsigned int board_idx = (unsigned int) ent->driver_data;
1657 struct device *dev = &pdev->dev;
1658 struct ata_probe_ent *probe_ent;
1659 struct ahci_host_priv *hpriv;
1664 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1666 if (!printed_version++)
1667 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1669 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1670 /* Function 1 is the PATA controller except on the 368, where
1671 we are not AHCI anyway */
1672 if (PCI_FUNC(pdev->devfn))
1676 rc = pcim_enable_device(pdev);
1680 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1682 pcim_pin_device(pdev);
1686 if (pci_enable_msi(pdev))
1689 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
1690 if (probe_ent == NULL)
1693 probe_ent->dev = pci_dev_to_dev(pdev);
1694 INIT_LIST_HEAD(&probe_ent->node);
1696 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1700 probe_ent->sht = ahci_port_info[board_idx].sht;
1701 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1702 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1703 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1704 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1706 probe_ent->irq = pdev->irq;
1707 probe_ent->irq_flags = IRQF_SHARED;
1708 probe_ent->iomap = pcim_iomap_table(pdev);
1709 probe_ent->private_data = hpriv;
1711 /* initialize adapter */
1712 rc = ahci_host_init(probe_ent);
1716 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1717 (hpriv->cap & HOST_CAP_NCQ))
1718 probe_ent->port_flags |= ATA_FLAG_NCQ;
1720 ahci_print_info(probe_ent);
1722 if (!ata_device_add(probe_ent))
1725 devm_kfree(dev, probe_ent);
1729 static int __init ahci_init(void)
1731 return pci_register_driver(&ahci_pci_driver);
1734 static void __exit ahci_exit(void)
1736 pci_unregister_driver(&ahci_pci_driver);
1740 MODULE_AUTHOR("Jeff Garzik");
1741 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1742 MODULE_LICENSE("GPL");
1743 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1744 MODULE_VERSION(DRV_VERSION);
1746 module_init(ahci_init);
1747 module_exit(ahci_exit);