2 * ahci.c - AHCI SATA support
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
67 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87 static bool is_mcp89_apple(struct pci_dev *pdev);
88 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
91 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92 static int ahci_pci_device_resume(struct pci_dev *pdev);
95 static struct scsi_host_template ahci_sht = {
99 static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
101 .hardreset = ahci_vt8251_hardreset,
104 static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
106 .hardreset = ahci_p5wdh_hardreset,
109 static const struct ata_port_info ahci_port_info[] = {
112 .flags = AHCI_FLAG_COMMON,
113 .pio_mask = ATA_PIO4,
114 .udma_mask = ATA_UDMA6,
115 .port_ops = &ahci_ops,
117 [board_ahci_ign_iferr] = {
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
124 [board_ahci_nosntf] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
131 [board_ahci_yes_fbs] = {
132 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
139 [board_ahci_mcp65] = {
140 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
142 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
147 [board_ahci_mcp77] = {
148 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
154 [board_ahci_mcp89] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
162 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
163 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
164 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
165 .pio_mask = ATA_PIO4,
166 .udma_mask = ATA_UDMA6,
167 .port_ops = &ahci_ops,
169 [board_ahci_sb600] = {
170 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
171 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
172 AHCI_HFLAG_32BIT_ONLY),
173 .flags = AHCI_FLAG_COMMON,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_pmp_retry_srst_ops,
178 [board_ahci_sb700] = { /* for SB700 and SB800 */
179 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_pmp_retry_srst_ops,
185 [board_ahci_vt8251] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_vt8251_ops,
194 static const struct pci_device_id ahci_pci_tbl[] = {
196 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
197 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
198 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
199 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
200 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
201 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
202 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
204 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
205 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
206 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
208 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
209 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
210 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
211 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
215 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
216 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
220 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
221 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
223 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
224 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
225 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
226 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
227 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
228 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
229 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
230 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
231 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
232 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
233 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
234 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
235 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
237 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
238 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
240 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
241 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
242 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
243 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
244 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
245 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
246 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
248 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
249 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
251 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
252 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
253 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
254 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
260 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
261 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
262 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
263 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
264 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
268 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
269 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
270 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
271 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
272 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
277 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
278 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
280 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
286 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
287 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
288 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
289 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
291 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
292 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
293 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
295 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
296 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
297 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
298 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
299 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
300 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
302 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
303 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
304 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
305 /* JMicron 362B and 362C have an AHCI function with IDE class code */
306 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
307 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
310 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
311 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
312 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
313 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
314 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
315 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
316 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
320 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
321 /* AMD is using RAID class only for ahci controllers */
322 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
323 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
326 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
327 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
330 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
331 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
332 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
333 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
371 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
372 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
383 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
395 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
396 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
406 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
407 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
408 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
417 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
418 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
420 /* ST Microelectronics */
421 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
424 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
425 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
426 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
427 .class = PCI_CLASS_STORAGE_SATA_AHCI,
428 .class_mask = 0xffffff,
429 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
430 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
431 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
432 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
433 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
434 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
435 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
437 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
438 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
439 .driver_data = board_ahci_yes_fbs },
440 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
441 .driver_data = board_ahci_yes_fbs },
444 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
447 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
448 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
449 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
450 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
453 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
455 /* Generic, PCI class code for AHCI */
456 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
457 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
459 { } /* terminate list */
463 static struct pci_driver ahci_pci_driver = {
465 .id_table = ahci_pci_tbl,
466 .probe = ahci_init_one,
467 .remove = ata_pci_remove_one,
469 .suspend = ahci_pci_device_suspend,
470 .resume = ahci_pci_device_resume,
474 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
475 static int marvell_enable;
477 static int marvell_enable = 1;
479 module_param(marvell_enable, int, 0644);
480 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
483 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
484 struct ahci_host_priv *hpriv)
486 unsigned int force_port_map = 0;
487 unsigned int mask_port_map = 0;
489 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
490 dev_info(&pdev->dev, "JMB361 has only one port\n");
495 * Temporary Marvell 6145 hack: PATA port presence
496 * is asserted through the standard AHCI port
497 * presence register, as bit 4 (counting from 0)
499 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
500 if (pdev->device == 0x6121)
505 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
508 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
512 static int ahci_pci_reset_controller(struct ata_host *host)
514 struct pci_dev *pdev = to_pci_dev(host->dev);
516 ahci_reset_controller(host);
518 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
519 struct ahci_host_priv *hpriv = host->private_data;
523 pci_read_config_word(pdev, 0x92, &tmp16);
524 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
525 tmp16 |= hpriv->port_map;
526 pci_write_config_word(pdev, 0x92, tmp16);
533 static void ahci_pci_init_controller(struct ata_host *host)
535 struct ahci_host_priv *hpriv = host->private_data;
536 struct pci_dev *pdev = to_pci_dev(host->dev);
537 void __iomem *port_mmio;
541 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
542 if (pdev->device == 0x6121)
546 port_mmio = __ahci_port_base(host, mv);
548 writel(0, port_mmio + PORT_IRQ_MASK);
551 tmp = readl(port_mmio + PORT_IRQ_STAT);
552 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
554 writel(tmp, port_mmio + PORT_IRQ_STAT);
557 ahci_init_controller(host);
560 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
561 unsigned long deadline)
563 struct ata_port *ap = link->ap;
569 ahci_stop_engine(ap);
571 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
572 deadline, &online, NULL);
574 ahci_start_engine(ap);
576 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
578 /* vt8251 doesn't clear BSY on signature FIS reception,
579 * request follow-up softreset.
581 return online ? -EAGAIN : rc;
584 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
585 unsigned long deadline)
587 struct ata_port *ap = link->ap;
588 struct ahci_port_priv *pp = ap->private_data;
589 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
590 struct ata_taskfile tf;
594 ahci_stop_engine(ap);
596 /* clear D2H reception area to properly wait for D2H FIS */
597 ata_tf_init(link->device, &tf);
598 tf.command = ATA_BUSY;
599 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
601 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
602 deadline, &online, NULL);
604 ahci_start_engine(ap);
606 /* The pseudo configuration device on SIMG4726 attached to
607 * ASUS P5W-DH Deluxe doesn't send signature FIS after
608 * hardreset if no device is attached to the first downstream
609 * port && the pseudo device locks up on SRST w/ PMP==0. To
610 * work around this, wait for !BSY only briefly. If BSY isn't
611 * cleared, perform CLO and proceed to IDENTIFY (achieved by
612 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
614 * Wait for two seconds. Devices attached to downstream port
615 * which can't process the following IDENTIFY after this will
616 * have to be reset again. For most cases, this should
617 * suffice while making probing snappish enough.
620 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
623 ahci_kick_engine(ap);
629 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
631 struct ata_host *host = pci_get_drvdata(pdev);
632 struct ahci_host_priv *hpriv = host->private_data;
633 void __iomem *mmio = hpriv->mmio;
636 if (mesg.event & PM_EVENT_SUSPEND &&
637 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
639 "BIOS update required for suspend/resume\n");
643 if (mesg.event & PM_EVENT_SLEEP) {
644 /* AHCI spec rev1.1 section 8.3.3:
645 * Software must disable interrupts prior to requesting a
646 * transition of the HBA to D3 state.
648 ctl = readl(mmio + HOST_CTL);
650 writel(ctl, mmio + HOST_CTL);
651 readl(mmio + HOST_CTL); /* flush */
654 return ata_pci_device_suspend(pdev, mesg);
657 static int ahci_pci_device_resume(struct pci_dev *pdev)
659 struct ata_host *host = pci_get_drvdata(pdev);
662 rc = ata_pci_device_do_resume(pdev);
666 /* Apple BIOS helpfully mangles the registers on resume */
667 if (is_mcp89_apple(pdev))
668 ahci_mcp89_apple_enable(pdev);
670 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
671 rc = ahci_pci_reset_controller(host);
675 ahci_pci_init_controller(host);
678 ata_host_resume(host);
684 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
689 * If the device fixup already set the dma_mask to some non-standard
690 * value, don't extend it here. This happens on STA2X11, for example.
692 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
696 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
697 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
699 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
702 "64-bit DMA enable failed\n");
707 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
709 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
712 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
715 "32-bit consistent DMA enable failed\n");
722 static void ahci_pci_print_info(struct ata_host *host)
724 struct pci_dev *pdev = to_pci_dev(host->dev);
728 pci_read_config_word(pdev, 0x0a, &cc);
729 if (cc == PCI_CLASS_STORAGE_IDE)
731 else if (cc == PCI_CLASS_STORAGE_SATA)
733 else if (cc == PCI_CLASS_STORAGE_RAID)
738 ahci_print_info(host, scc_s);
741 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
742 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
743 * support PMP and the 4726 either directly exports the device
744 * attached to the first downstream port or acts as a hardware storage
745 * controller and emulate a single ATA device (can be RAID 0/1 or some
746 * other configuration).
748 * When there's no device attached to the first downstream port of the
749 * 4726, "Config Disk" appears, which is a pseudo ATA device to
750 * configure the 4726. However, ATA emulation of the device is very
751 * lame. It doesn't send signature D2H Reg FIS after the initial
752 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
754 * The following function works around the problem by always using
755 * hardreset on the port and not depending on receiving signature FIS
756 * afterward. If signature FIS isn't received soon, ATA class is
757 * assumed without follow-up softreset.
759 static void ahci_p5wdh_workaround(struct ata_host *host)
761 static struct dmi_system_id sysids[] = {
763 .ident = "P5W DH Deluxe",
765 DMI_MATCH(DMI_SYS_VENDOR,
766 "ASUSTEK COMPUTER INC"),
767 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
772 struct pci_dev *pdev = to_pci_dev(host->dev);
774 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
775 dmi_check_system(sysids)) {
776 struct ata_port *ap = host->ports[1];
779 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
781 ap->ops = &ahci_p5wdh_ops;
782 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
787 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
788 * booting in BIOS compatibility mode. We restore the registers but not ID.
790 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
794 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
796 pci_read_config_dword(pdev, 0xf8, &val);
798 /* the following changes the device ID, but appears not to affect function */
799 /* val = (val & ~0xf0000000) | 0x80000000; */
800 pci_write_config_dword(pdev, 0xf8, val);
802 pci_read_config_dword(pdev, 0x54c, &val);
804 pci_write_config_dword(pdev, 0x54c, val);
806 pci_read_config_dword(pdev, 0x4a4, &val);
809 pci_write_config_dword(pdev, 0x4a4, val);
811 pci_read_config_dword(pdev, 0x54c, &val);
813 pci_write_config_dword(pdev, 0x54c, val);
815 pci_read_config_dword(pdev, 0xf8, &val);
817 pci_write_config_dword(pdev, 0xf8, val);
820 static bool is_mcp89_apple(struct pci_dev *pdev)
822 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
823 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
824 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
825 pdev->subsystem_device == 0xcb89;
828 /* only some SB600 ahci controllers can do 64bit DMA */
829 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
831 static const struct dmi_system_id sysids[] = {
833 * The oldest version known to be broken is 0901 and
834 * working is 1501 which was released on 2007-10-26.
835 * Enable 64bit DMA on 1501 and anything newer.
837 * Please read bko#9412 for more info.
840 .ident = "ASUS M2A-VM",
842 DMI_MATCH(DMI_BOARD_VENDOR,
843 "ASUSTeK Computer INC."),
844 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
846 .driver_data = "20071026", /* yyyymmdd */
849 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
852 * BIOS versions earlier than 1.5 had the Manufacturer DMI
853 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
854 * This spelling mistake was fixed in BIOS version 1.5, so
855 * 1.5 and later have the Manufacturer as
856 * "MICRO-STAR INTERNATIONAL CO.,LTD".
857 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
859 * BIOS versions earlier than 1.9 had a Board Product Name
860 * DMI field of "MS-7376". This was changed to be
861 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
862 * match on DMI_BOARD_NAME of "MS-7376".
865 .ident = "MSI K9A2 Platinum",
867 DMI_MATCH(DMI_BOARD_VENDOR,
869 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
873 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
876 * This board also had the typo mentioned above in the
877 * Manufacturer DMI field (fixed in BIOS version 1.5), so
878 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
881 .ident = "MSI K9AGM2",
883 DMI_MATCH(DMI_BOARD_VENDOR,
885 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
889 * All BIOS versions for the Asus M3A support 64bit DMA.
890 * (all release versions from 0301 to 1206 were tested)
895 DMI_MATCH(DMI_BOARD_VENDOR,
896 "ASUSTeK Computer INC."),
897 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
902 const struct dmi_system_id *match;
903 int year, month, date;
906 match = dmi_first_match(sysids);
907 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
911 if (!match->driver_data)
914 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
915 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
917 if (strcmp(buf, match->driver_data) >= 0)
921 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
927 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
931 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
933 static const struct dmi_system_id broken_systems[] = {
935 .ident = "HP Compaq nx6310",
937 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
938 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
940 /* PCI slot number of the controller */
941 .driver_data = (void *)0x1FUL,
944 .ident = "HP Compaq 6720s",
946 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
947 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
949 /* PCI slot number of the controller */
950 .driver_data = (void *)0x1FUL,
953 { } /* terminate list */
955 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
958 unsigned long slot = (unsigned long)dmi->driver_data;
959 /* apply the quirk only to on-board controllers */
960 return slot == PCI_SLOT(pdev->devfn);
966 static bool ahci_broken_suspend(struct pci_dev *pdev)
968 static const struct dmi_system_id sysids[] = {
970 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
971 * to the harddisk doesn't become online after
972 * resuming from STR. Warn and fail suspend.
974 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
976 * Use dates instead of versions to match as HP is
977 * apparently recycling both product and version
980 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
985 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
986 DMI_MATCH(DMI_PRODUCT_NAME,
987 "HP Pavilion dv4 Notebook PC"),
989 .driver_data = "20090105", /* F.30 */
994 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
995 DMI_MATCH(DMI_PRODUCT_NAME,
996 "HP Pavilion dv5 Notebook PC"),
998 .driver_data = "20090506", /* F.16 */
1003 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1004 DMI_MATCH(DMI_PRODUCT_NAME,
1005 "HP Pavilion dv6 Notebook PC"),
1007 .driver_data = "20090423", /* F.21 */
1012 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1013 DMI_MATCH(DMI_PRODUCT_NAME,
1014 "HP HDX18 Notebook PC"),
1016 .driver_data = "20090430", /* F.23 */
1019 * Acer eMachines G725 has the same problem. BIOS
1020 * V1.03 is known to be broken. V3.04 is known to
1021 * work. Between, there are V1.06, V2.06 and V3.03
1022 * that we don't have much idea about. For now,
1023 * blacklist anything older than V3.04.
1025 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1030 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1031 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1033 .driver_data = "20091216", /* V3.04 */
1035 { } /* terminate list */
1037 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1038 int year, month, date;
1041 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1044 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1045 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1047 return strcmp(buf, dmi->driver_data) < 0;
1050 static bool ahci_broken_online(struct pci_dev *pdev)
1052 #define ENCODE_BUSDEVFN(bus, slot, func) \
1053 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1054 static const struct dmi_system_id sysids[] = {
1056 * There are several gigabyte boards which use
1057 * SIMG5723s configured as hardware RAID. Certain
1058 * 5723 firmware revisions shipped there keep the link
1059 * online but fail to answer properly to SRST or
1060 * IDENTIFY when no device is attached downstream
1061 * causing libata to retry quite a few times leading
1062 * to excessive detection delay.
1064 * As these firmwares respond to the second reset try
1065 * with invalid device signature, considering unknown
1066 * sig as offline works around the problem acceptably.
1069 .ident = "EP45-DQ6",
1071 DMI_MATCH(DMI_BOARD_VENDOR,
1072 "Gigabyte Technology Co., Ltd."),
1073 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1075 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1078 .ident = "EP45-DS5",
1080 DMI_MATCH(DMI_BOARD_VENDOR,
1081 "Gigabyte Technology Co., Ltd."),
1082 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1084 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1086 { } /* terminate list */
1088 #undef ENCODE_BUSDEVFN
1089 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1095 val = (unsigned long)dmi->driver_data;
1097 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1100 #ifdef CONFIG_ATA_ACPI
1101 static void ahci_gtf_filter_workaround(struct ata_host *host)
1103 static const struct dmi_system_id sysids[] = {
1105 * Aspire 3810T issues a bunch of SATA enable commands
1106 * via _GTF including an invalid one and one which is
1107 * rejected by the device. Among the successful ones
1108 * is FPDMA non-zero offset enable which when enabled
1109 * only on the drive side leads to NCQ command
1110 * failures. Filter it out.
1113 .ident = "Aspire 3810T",
1115 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1116 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1118 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1122 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1123 unsigned int filter;
1129 filter = (unsigned long)dmi->driver_data;
1130 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1131 filter, dmi->ident);
1133 for (i = 0; i < host->n_ports; i++) {
1134 struct ata_port *ap = host->ports[i];
1135 struct ata_link *link;
1136 struct ata_device *dev;
1138 ata_for_each_link(link, ap, EDGE)
1139 ata_for_each_dev(dev, link, ALL)
1140 dev->gtf_filter |= filter;
1144 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1148 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1151 unsigned int maxvec;
1153 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1154 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1156 if ((rc == maxvec) || (rc == 1))
1159 * Assume that advantage of multipe MSIs is negated,
1160 * so fallback to single MSI mode to save resources
1162 pci_disable_msi(pdev);
1163 if (!pci_enable_msi(pdev))
1173 * ahci_host_activate - start AHCI host, request IRQs and register it
1174 * @host: target ATA host
1175 * @irq: base IRQ number to request
1176 * @n_msis: number of MSIs allocated for this host
1177 * @irq_handler: irq_handler used when requesting IRQs
1178 * @irq_flags: irq_flags used when requesting IRQs
1180 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1181 * when multiple MSIs were allocated. That is one MSI per port, starting
1185 * Inherited from calling layer (may sleep).
1188 * 0 on success, -errno otherwise.
1190 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1194 /* Sharing Last Message among several ports is not supported */
1195 if (n_msis < host->n_ports)
1198 rc = ata_host_start(host);
1202 for (i = 0; i < host->n_ports; i++) {
1204 struct ahci_port_priv *pp = host->ports[i]->private_data;
1206 /* pp is NULL for dummy ports */
1208 desc = pp->irq_desc;
1210 desc = dev_driver_string(host->dev);
1212 rc = devm_request_threaded_irq(host->dev,
1213 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1214 desc, host->ports[i]);
1219 for (i = 0; i < host->n_ports; i++)
1220 ata_port_desc(host->ports[i], "irq %d", irq + i);
1222 rc = ata_host_register(host, &ahci_sht);
1224 goto out_free_all_irqs;
1231 for (i--; i >= 0; i--)
1232 devm_free_irq(host->dev, irq + i, host->ports[i]);
1237 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1239 unsigned int board_id = ent->driver_data;
1240 struct ata_port_info pi = ahci_port_info[board_id];
1241 const struct ata_port_info *ppi[] = { &pi, NULL };
1242 struct device *dev = &pdev->dev;
1243 struct ahci_host_priv *hpriv;
1244 struct ata_host *host;
1245 int n_ports, n_msis, i, rc;
1246 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1250 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1252 ata_print_version_once(&pdev->dev, DRV_VERSION);
1254 /* The AHCI driver can only drive the SATA ports, the PATA driver
1255 can drive them all so if both drivers are selected make sure
1256 AHCI stays out of the way */
1257 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1260 /* Apple BIOS on MCP89 prevents us using AHCI */
1261 if (is_mcp89_apple(pdev))
1262 ahci_mcp89_apple_enable(pdev);
1264 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1265 * At the moment, we can only use the AHCI mode. Let the users know
1266 * that for SAS drives they're out of luck.
1268 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1269 dev_info(&pdev->dev,
1270 "PDC42819 can only drive SATA devices with this driver\n");
1272 /* Both Connext and Enmotus devices use non-standard BARs */
1273 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1274 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1275 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1276 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1278 /* acquire resources */
1279 rc = pcim_enable_device(pdev);
1283 /* AHCI controllers often implement SFF compatible interface.
1284 * Grab all PCI BARs just in case.
1286 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1288 pcim_pin_device(pdev);
1292 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1293 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1296 /* ICH6s share the same PCI ID for both piix and ahci
1297 * modes. Enabling ahci mode while MAP indicates
1298 * combined mode is a bad idea. Yield to ata_piix.
1300 pci_read_config_byte(pdev, ICH_MAP, &map);
1302 dev_info(&pdev->dev,
1303 "controller is in combined mode, can't enable AHCI mode\n");
1308 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1311 hpriv->flags |= (unsigned long)pi.private_data;
1313 /* MCP65 revision A1 and A2 can't do MSI */
1314 if (board_id == board_ahci_mcp65 &&
1315 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1316 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1318 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1319 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1320 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1322 /* only some SB600s can do 64bit DMA */
1323 if (ahci_sb600_enable_64bit(pdev))
1324 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1326 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1328 n_msis = ahci_init_interrupts(pdev, hpriv);
1330 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1332 /* save initial config */
1333 ahci_pci_save_initial_config(pdev, hpriv);
1336 if (hpriv->cap & HOST_CAP_NCQ) {
1337 pi.flags |= ATA_FLAG_NCQ;
1339 * Auto-activate optimization is supposed to be
1340 * supported on all AHCI controllers indicating NCQ
1341 * capability, but it seems to be broken on some
1342 * chipsets including NVIDIAs.
1344 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1345 pi.flags |= ATA_FLAG_FPDMA_AA;
1348 * All AHCI controllers should be forward-compatible
1349 * with the new auxiliary field. This code should be
1350 * conditionalized if any buggy AHCI controllers are
1353 pi.flags |= ATA_FLAG_FPDMA_AUX;
1356 if (hpriv->cap & HOST_CAP_PMP)
1357 pi.flags |= ATA_FLAG_PMP;
1359 ahci_set_em_messages(hpriv, &pi);
1361 if (ahci_broken_system_poweroff(pdev)) {
1362 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1363 dev_info(&pdev->dev,
1364 "quirky BIOS, skipping spindown on poweroff\n");
1367 if (ahci_broken_suspend(pdev)) {
1368 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1369 dev_warn(&pdev->dev,
1370 "BIOS update required for suspend/resume\n");
1373 if (ahci_broken_online(pdev)) {
1374 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1375 dev_info(&pdev->dev,
1376 "online status unreliable, applying workaround\n");
1379 /* CAP.NP sometimes indicate the index of the last enabled
1380 * port, at other times, that of the last possible port, so
1381 * determining the maximum port number requires looking at
1382 * both CAP.NP and port_map.
1384 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1386 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1389 host->private_data = hpriv;
1391 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1392 host->flags |= ATA_HOST_PARALLEL_SCAN;
1394 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1396 if (pi.flags & ATA_FLAG_EM)
1397 ahci_reset_em(host);
1399 for (i = 0; i < host->n_ports; i++) {
1400 struct ata_port *ap = host->ports[i];
1402 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1403 ata_port_pbar_desc(ap, ahci_pci_bar,
1404 0x100 + ap->port_no * 0x80, "port");
1406 /* set enclosure management message type */
1407 if (ap->flags & ATA_FLAG_EM)
1408 ap->em_message_type = hpriv->em_msg_type;
1411 /* disabled/not-implemented port */
1412 if (!(hpriv->port_map & (1 << i)))
1413 ap->ops = &ata_dummy_port_ops;
1416 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1417 ahci_p5wdh_workaround(host);
1419 /* apply gtf filter quirk */
1420 ahci_gtf_filter_workaround(host);
1422 /* initialize adapter */
1423 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1427 rc = ahci_pci_reset_controller(host);
1431 ahci_pci_init_controller(host);
1432 ahci_pci_print_info(host);
1434 pci_set_master(pdev);
1436 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1437 return ahci_host_activate(host, pdev->irq, n_msis);
1439 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1443 module_pci_driver(ahci_pci_driver);
1445 MODULE_AUTHOR("Jeff Garzik");
1446 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1447 MODULE_LICENSE("GPL");
1448 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1449 MODULE_VERSION(DRV_VERSION);