2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
59 /* board IDs by feature in alphabetical order */
65 /* board IDs for specific chipsets in alphabetical order */
71 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 static struct ata_port_operations ahci_vt8251_ops = {
94 .inherits = &ahci_ops,
95 .hardreset = ahci_vt8251_hardreset,
98 static struct ata_port_operations ahci_p5wdh_ops = {
99 .inherits = &ahci_ops,
100 .hardreset = ahci_p5wdh_hardreset,
103 static struct ata_port_operations ahci_sb600_ops = {
104 .inherits = &ahci_ops,
105 .softreset = ahci_sb600_softreset,
106 .pmp_softreset = ahci_sb600_softreset,
109 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
111 static const struct ata_port_info ahci_port_info[] = {
115 .flags = AHCI_FLAG_COMMON,
116 .pio_mask = ATA_PIO4,
117 .udma_mask = ATA_UDMA6,
118 .port_ops = &ahci_ops,
120 [board_ahci_ign_iferr] =
122 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_nosntf] =
130 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_yes_fbs] =
138 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
156 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
164 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_ops,
172 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
173 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
174 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
175 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
182 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
183 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
184 AHCI_HFLAG_32BIT_ONLY),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_sb600_ops,
190 [board_ahci_sb700] = /* for SB700 and SB800 */
192 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_sb600_ops,
198 [board_ahci_vt8251] =
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
201 .flags = AHCI_FLAG_COMMON,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
204 .port_ops = &ahci_vt8251_ops,
208 static const struct pci_device_id ahci_pci_tbl[] = {
210 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
211 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
212 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
213 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
214 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
215 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
216 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
217 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
220 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
221 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
222 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
224 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
236 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
238 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
240 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
241 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
242 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
250 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
251 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
257 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
258 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
260 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
261 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
262 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
265 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
266 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
267 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
268 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
269 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
270 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
275 /* AMD is using RAID class only for ahci controllers */
276 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
277 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
280 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
281 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
284 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
285 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
286 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
287 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
288 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
293 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
294 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
295 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
296 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
305 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
306 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
307 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
308 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
321 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
322 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
323 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
324 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
333 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
334 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
335 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
345 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
346 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
347 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
357 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
358 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
359 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
360 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
371 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
372 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
375 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
376 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
377 { PCI_DEVICE(0x1b4b, 0x9123),
378 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
381 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
383 /* Generic, PCI class code for AHCI */
384 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
385 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
387 { } /* terminate list */
391 static struct pci_driver ahci_pci_driver = {
393 .id_table = ahci_pci_tbl,
394 .probe = ahci_init_one,
395 .remove = ata_pci_remove_one,
397 .suspend = ahci_pci_device_suspend,
398 .resume = ahci_pci_device_resume,
402 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
403 static int marvell_enable;
405 static int marvell_enable = 1;
407 module_param(marvell_enable, int, 0644);
408 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
411 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
412 struct ahci_host_priv *hpriv)
414 unsigned int force_port_map = 0;
415 unsigned int mask_port_map = 0;
417 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
418 dev_info(&pdev->dev, "JMB361 has only one port\n");
423 * Temporary Marvell 6145 hack: PATA port presence
424 * is asserted through the standard AHCI port
425 * presence register, as bit 4 (counting from 0)
427 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
428 if (pdev->device == 0x6121)
433 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
436 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
440 static int ahci_pci_reset_controller(struct ata_host *host)
442 struct pci_dev *pdev = to_pci_dev(host->dev);
444 ahci_reset_controller(host);
446 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
447 struct ahci_host_priv *hpriv = host->private_data;
451 pci_read_config_word(pdev, 0x92, &tmp16);
452 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
453 tmp16 |= hpriv->port_map;
454 pci_write_config_word(pdev, 0x92, tmp16);
461 static void ahci_pci_init_controller(struct ata_host *host)
463 struct ahci_host_priv *hpriv = host->private_data;
464 struct pci_dev *pdev = to_pci_dev(host->dev);
465 void __iomem *port_mmio;
469 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
470 if (pdev->device == 0x6121)
474 port_mmio = __ahci_port_base(host, mv);
476 writel(0, port_mmio + PORT_IRQ_MASK);
479 tmp = readl(port_mmio + PORT_IRQ_STAT);
480 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
482 writel(tmp, port_mmio + PORT_IRQ_STAT);
485 ahci_init_controller(host);
488 static int ahci_sb600_check_ready(struct ata_link *link)
490 void __iomem *port_mmio = ahci_port_base(link->ap);
491 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
492 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
495 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
496 * which can save timeout delay.
498 if (irq_status & PORT_IRQ_BAD_PMP)
501 return ata_check_ready(status);
504 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
505 unsigned long deadline)
507 struct ata_port *ap = link->ap;
508 void __iomem *port_mmio = ahci_port_base(ap);
509 int pmp = sata_srst_pmp(link);
515 rc = ahci_do_softreset(link, class, pmp, deadline,
516 ahci_sb600_check_ready);
519 * Soft reset fails on some ATI chips with IPMS set when PMP
520 * is enabled but SATA HDD/ODD is connected to SATA port,
521 * do soft reset again to port 0.
524 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
525 if (irq_sts & PORT_IRQ_BAD_PMP) {
526 ata_link_printk(link, KERN_WARNING,
527 "applying SB600 PMP SRST workaround "
529 rc = ahci_do_softreset(link, class, 0, deadline,
537 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
538 unsigned long deadline)
540 struct ata_port *ap = link->ap;
546 ahci_stop_engine(ap);
548 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
549 deadline, &online, NULL);
551 ahci_start_engine(ap);
553 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
555 /* vt8251 doesn't clear BSY on signature FIS reception,
556 * request follow-up softreset.
558 return online ? -EAGAIN : rc;
561 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
562 unsigned long deadline)
564 struct ata_port *ap = link->ap;
565 struct ahci_port_priv *pp = ap->private_data;
566 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
567 struct ata_taskfile tf;
571 ahci_stop_engine(ap);
573 /* clear D2H reception area to properly wait for D2H FIS */
574 ata_tf_init(link->device, &tf);
576 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
578 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
579 deadline, &online, NULL);
581 ahci_start_engine(ap);
583 /* The pseudo configuration device on SIMG4726 attached to
584 * ASUS P5W-DH Deluxe doesn't send signature FIS after
585 * hardreset if no device is attached to the first downstream
586 * port && the pseudo device locks up on SRST w/ PMP==0. To
587 * work around this, wait for !BSY only briefly. If BSY isn't
588 * cleared, perform CLO and proceed to IDENTIFY (achieved by
589 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
591 * Wait for two seconds. Devices attached to downstream port
592 * which can't process the following IDENTIFY after this will
593 * have to be reset again. For most cases, this should
594 * suffice while making probing snappish enough.
597 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
600 ahci_kick_engine(ap);
606 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
608 struct ata_host *host = dev_get_drvdata(&pdev->dev);
609 struct ahci_host_priv *hpriv = host->private_data;
610 void __iomem *mmio = hpriv->mmio;
613 if (mesg.event & PM_EVENT_SUSPEND &&
614 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
615 dev_printk(KERN_ERR, &pdev->dev,
616 "BIOS update required for suspend/resume\n");
620 if (mesg.event & PM_EVENT_SLEEP) {
621 /* AHCI spec rev1.1 section 8.3.3:
622 * Software must disable interrupts prior to requesting a
623 * transition of the HBA to D3 state.
625 ctl = readl(mmio + HOST_CTL);
627 writel(ctl, mmio + HOST_CTL);
628 readl(mmio + HOST_CTL); /* flush */
631 return ata_pci_device_suspend(pdev, mesg);
634 static int ahci_pci_device_resume(struct pci_dev *pdev)
636 struct ata_host *host = dev_get_drvdata(&pdev->dev);
639 rc = ata_pci_device_do_resume(pdev);
643 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
644 rc = ahci_pci_reset_controller(host);
648 ahci_pci_init_controller(host);
651 ata_host_resume(host);
657 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
662 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
663 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
665 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
667 dev_printk(KERN_ERR, &pdev->dev,
668 "64-bit DMA enable failed\n");
673 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
675 dev_printk(KERN_ERR, &pdev->dev,
676 "32-bit DMA enable failed\n");
679 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
681 dev_printk(KERN_ERR, &pdev->dev,
682 "32-bit consistent DMA enable failed\n");
689 static void ahci_pci_print_info(struct ata_host *host)
691 struct pci_dev *pdev = to_pci_dev(host->dev);
695 pci_read_config_word(pdev, 0x0a, &cc);
696 if (cc == PCI_CLASS_STORAGE_IDE)
698 else if (cc == PCI_CLASS_STORAGE_SATA)
700 else if (cc == PCI_CLASS_STORAGE_RAID)
705 ahci_print_info(host, scc_s);
708 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
709 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
710 * support PMP and the 4726 either directly exports the device
711 * attached to the first downstream port or acts as a hardware storage
712 * controller and emulate a single ATA device (can be RAID 0/1 or some
713 * other configuration).
715 * When there's no device attached to the first downstream port of the
716 * 4726, "Config Disk" appears, which is a pseudo ATA device to
717 * configure the 4726. However, ATA emulation of the device is very
718 * lame. It doesn't send signature D2H Reg FIS after the initial
719 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
721 * The following function works around the problem by always using
722 * hardreset on the port and not depending on receiving signature FIS
723 * afterward. If signature FIS isn't received soon, ATA class is
724 * assumed without follow-up softreset.
726 static void ahci_p5wdh_workaround(struct ata_host *host)
728 static struct dmi_system_id sysids[] = {
730 .ident = "P5W DH Deluxe",
732 DMI_MATCH(DMI_SYS_VENDOR,
733 "ASUSTEK COMPUTER INC"),
734 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
739 struct pci_dev *pdev = to_pci_dev(host->dev);
741 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
742 dmi_check_system(sysids)) {
743 struct ata_port *ap = host->ports[1];
745 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
746 "Deluxe on-board SIMG4726 workaround\n");
748 ap->ops = &ahci_p5wdh_ops;
749 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
753 /* only some SB600 ahci controllers can do 64bit DMA */
754 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
756 static const struct dmi_system_id sysids[] = {
758 * The oldest version known to be broken is 0901 and
759 * working is 1501 which was released on 2007-10-26.
760 * Enable 64bit DMA on 1501 and anything newer.
762 * Please read bko#9412 for more info.
765 .ident = "ASUS M2A-VM",
767 DMI_MATCH(DMI_BOARD_VENDOR,
768 "ASUSTeK Computer INC."),
769 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
771 .driver_data = "20071026", /* yyyymmdd */
774 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
777 * BIOS versions earlier than 1.5 had the Manufacturer DMI
778 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
779 * This spelling mistake was fixed in BIOS version 1.5, so
780 * 1.5 and later have the Manufacturer as
781 * "MICRO-STAR INTERNATIONAL CO.,LTD".
782 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
784 * BIOS versions earlier than 1.9 had a Board Product Name
785 * DMI field of "MS-7376". This was changed to be
786 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
787 * match on DMI_BOARD_NAME of "MS-7376".
790 .ident = "MSI K9A2 Platinum",
792 DMI_MATCH(DMI_BOARD_VENDOR,
794 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
799 const struct dmi_system_id *match;
800 int year, month, date;
803 match = dmi_first_match(sysids);
804 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
808 if (!match->driver_data)
811 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
812 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
814 if (strcmp(buf, match->driver_data) >= 0)
817 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
818 "forcing 32bit DMA, update BIOS\n", match->ident);
823 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
828 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
830 static const struct dmi_system_id broken_systems[] = {
832 .ident = "HP Compaq nx6310",
834 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
835 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
837 /* PCI slot number of the controller */
838 .driver_data = (void *)0x1FUL,
841 .ident = "HP Compaq 6720s",
843 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
844 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
846 /* PCI slot number of the controller */
847 .driver_data = (void *)0x1FUL,
850 { } /* terminate list */
852 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
855 unsigned long slot = (unsigned long)dmi->driver_data;
856 /* apply the quirk only to on-board controllers */
857 return slot == PCI_SLOT(pdev->devfn);
863 static bool ahci_broken_suspend(struct pci_dev *pdev)
865 static const struct dmi_system_id sysids[] = {
867 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
868 * to the harddisk doesn't become online after
869 * resuming from STR. Warn and fail suspend.
871 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
873 * Use dates instead of versions to match as HP is
874 * apparently recycling both product and version
877 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
882 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
883 DMI_MATCH(DMI_PRODUCT_NAME,
884 "HP Pavilion dv4 Notebook PC"),
886 .driver_data = "20090105", /* F.30 */
891 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
892 DMI_MATCH(DMI_PRODUCT_NAME,
893 "HP Pavilion dv5 Notebook PC"),
895 .driver_data = "20090506", /* F.16 */
900 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
901 DMI_MATCH(DMI_PRODUCT_NAME,
902 "HP Pavilion dv6 Notebook PC"),
904 .driver_data = "20090423", /* F.21 */
909 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
910 DMI_MATCH(DMI_PRODUCT_NAME,
911 "HP HDX18 Notebook PC"),
913 .driver_data = "20090430", /* F.23 */
916 * Acer eMachines G725 has the same problem. BIOS
917 * V1.03 is known to be broken. V3.04 is known to
918 * work. Inbetween, there are V1.06, V2.06 and V3.03
919 * that we don't have much idea about. For now,
920 * blacklist anything older than V3.04.
922 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
927 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
928 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
930 .driver_data = "20091216", /* V3.04 */
932 { } /* terminate list */
934 const struct dmi_system_id *dmi = dmi_first_match(sysids);
935 int year, month, date;
938 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
941 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
942 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
944 return strcmp(buf, dmi->driver_data) < 0;
947 static bool ahci_broken_online(struct pci_dev *pdev)
949 #define ENCODE_BUSDEVFN(bus, slot, func) \
950 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
951 static const struct dmi_system_id sysids[] = {
953 * There are several gigabyte boards which use
954 * SIMG5723s configured as hardware RAID. Certain
955 * 5723 firmware revisions shipped there keep the link
956 * online but fail to answer properly to SRST or
957 * IDENTIFY when no device is attached downstream
958 * causing libata to retry quite a few times leading
959 * to excessive detection delay.
961 * As these firmwares respond to the second reset try
962 * with invalid device signature, considering unknown
963 * sig as offline works around the problem acceptably.
968 DMI_MATCH(DMI_BOARD_VENDOR,
969 "Gigabyte Technology Co., Ltd."),
970 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
972 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
977 DMI_MATCH(DMI_BOARD_VENDOR,
978 "Gigabyte Technology Co., Ltd."),
979 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
981 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
983 { } /* terminate list */
985 #undef ENCODE_BUSDEVFN
986 const struct dmi_system_id *dmi = dmi_first_match(sysids);
992 val = (unsigned long)dmi->driver_data;
994 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
997 #ifdef CONFIG_ATA_ACPI
998 static void ahci_gtf_filter_workaround(struct ata_host *host)
1000 static const struct dmi_system_id sysids[] = {
1002 * Aspire 3810T issues a bunch of SATA enable commands
1003 * via _GTF including an invalid one and one which is
1004 * rejected by the device. Among the successful ones
1005 * is FPDMA non-zero offset enable which when enabled
1006 * only on the drive side leads to NCQ command
1007 * failures. Filter it out.
1010 .ident = "Aspire 3810T",
1012 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1013 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1015 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1019 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1020 unsigned int filter;
1026 filter = (unsigned long)dmi->driver_data;
1027 dev_printk(KERN_INFO, host->dev,
1028 "applying extra ACPI _GTF filter 0x%x for %s\n",
1029 filter, dmi->ident);
1031 for (i = 0; i < host->n_ports; i++) {
1032 struct ata_port *ap = host->ports[i];
1033 struct ata_link *link;
1034 struct ata_device *dev;
1036 ata_for_each_link(link, ap, EDGE)
1037 ata_for_each_dev(dev, link, ALL)
1038 dev->gtf_filter |= filter;
1042 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1046 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1048 static int printed_version;
1049 unsigned int board_id = ent->driver_data;
1050 struct ata_port_info pi = ahci_port_info[board_id];
1051 const struct ata_port_info *ppi[] = { &pi, NULL };
1052 struct device *dev = &pdev->dev;
1053 struct ahci_host_priv *hpriv;
1054 struct ata_host *host;
1059 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1061 if (!printed_version++)
1062 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1064 /* The AHCI driver can only drive the SATA ports, the PATA driver
1065 can drive them all so if both drivers are selected make sure
1066 AHCI stays out of the way */
1067 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1071 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1072 * ahci, use ata_generic instead.
1074 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1075 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1076 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1077 pdev->subsystem_device == 0xcb89)
1080 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1081 * At the moment, we can only use the AHCI mode. Let the users know
1082 * that for SAS drives they're out of luck.
1084 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1085 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1086 "can only drive SATA devices with this driver\n");
1088 /* acquire resources */
1089 rc = pcim_enable_device(pdev);
1093 /* AHCI controllers often implement SFF compatible interface.
1094 * Grab all PCI BARs just in case.
1096 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1098 pcim_pin_device(pdev);
1102 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1103 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1106 /* ICH6s share the same PCI ID for both piix and ahci
1107 * modes. Enabling ahci mode while MAP indicates
1108 * combined mode is a bad idea. Yield to ata_piix.
1110 pci_read_config_byte(pdev, ICH_MAP, &map);
1112 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1113 "combined mode, can't enable AHCI mode\n");
1118 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1121 hpriv->flags |= (unsigned long)pi.private_data;
1123 /* MCP65 revision A1 and A2 can't do MSI */
1124 if (board_id == board_ahci_mcp65 &&
1125 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1126 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1128 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1129 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1130 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1132 /* only some SB600s can do 64bit DMA */
1133 if (ahci_sb600_enable_64bit(pdev))
1134 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1136 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1139 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1141 /* save initial config */
1142 ahci_pci_save_initial_config(pdev, hpriv);
1145 if (hpriv->cap & HOST_CAP_NCQ) {
1146 pi.flags |= ATA_FLAG_NCQ;
1148 * Auto-activate optimization is supposed to be
1149 * supported on all AHCI controllers indicating NCQ
1150 * capability, but it seems to be broken on some
1151 * chipsets including NVIDIAs.
1153 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1154 pi.flags |= ATA_FLAG_FPDMA_AA;
1157 if (hpriv->cap & HOST_CAP_PMP)
1158 pi.flags |= ATA_FLAG_PMP;
1160 ahci_set_em_messages(hpriv, &pi);
1162 if (ahci_broken_system_poweroff(pdev)) {
1163 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1164 dev_info(&pdev->dev,
1165 "quirky BIOS, skipping spindown on poweroff\n");
1168 if (ahci_broken_suspend(pdev)) {
1169 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1170 dev_printk(KERN_WARNING, &pdev->dev,
1171 "BIOS update required for suspend/resume\n");
1174 if (ahci_broken_online(pdev)) {
1175 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1176 dev_info(&pdev->dev,
1177 "online status unreliable, applying workaround\n");
1180 /* CAP.NP sometimes indicate the index of the last enabled
1181 * port, at other times, that of the last possible port, so
1182 * determining the maximum port number requires looking at
1183 * both CAP.NP and port_map.
1185 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1187 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1190 host->private_data = hpriv;
1192 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1193 host->flags |= ATA_HOST_PARALLEL_SCAN;
1195 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1197 if (pi.flags & ATA_FLAG_EM)
1198 ahci_reset_em(host);
1200 for (i = 0; i < host->n_ports; i++) {
1201 struct ata_port *ap = host->ports[i];
1203 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1204 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1205 0x100 + ap->port_no * 0x80, "port");
1207 /* set initial link pm policy */
1208 ap->pm_policy = NOT_AVAILABLE;
1210 /* set enclosure management message type */
1211 if (ap->flags & ATA_FLAG_EM)
1212 ap->em_message_type = hpriv->em_msg_type;
1215 /* disabled/not-implemented port */
1216 if (!(hpriv->port_map & (1 << i)))
1217 ap->ops = &ata_dummy_port_ops;
1220 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1221 ahci_p5wdh_workaround(host);
1223 /* apply gtf filter quirk */
1224 ahci_gtf_filter_workaround(host);
1226 /* initialize adapter */
1227 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1231 rc = ahci_pci_reset_controller(host);
1235 ahci_pci_init_controller(host);
1236 ahci_pci_print_info(host);
1238 pci_set_master(pdev);
1239 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1243 static int __init ahci_init(void)
1245 return pci_register_driver(&ahci_pci_driver);
1248 static void __exit ahci_exit(void)
1250 pci_unregister_driver(&ahci_pci_driver);
1254 MODULE_AUTHOR("Jeff Garzik");
1255 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1256 MODULE_LICENSE("GPL");
1257 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1258 MODULE_VERSION(DRV_VERSION);
1260 module_init(ahci_init);
1261 module_exit(ahci_exit);