2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 1,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
81 board_ahci_vt8251 = 1,
82 board_ahci_ign_iferr = 2,
86 /* global controller registers */
87 HOST_CAP = 0x00, /* host capabilities */
88 HOST_CTL = 0x04, /* global host control */
89 HOST_IRQ_STAT = 0x08, /* interrupt status */
90 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
94 HOST_RESET = (1 << 0), /* reset controller; self-clear */
95 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
96 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
99 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
100 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
101 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
102 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
103 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
104 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
105 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
107 /* registers for each SATA port */
108 PORT_LST_ADDR = 0x00, /* command list DMA addr */
109 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
110 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
111 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
112 PORT_IRQ_STAT = 0x10, /* interrupt status */
113 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
114 PORT_CMD = 0x18, /* port command */
115 PORT_TFDATA = 0x20, /* taskfile data */
116 PORT_SIG = 0x24, /* device TF signature */
117 PORT_CMD_ISSUE = 0x38, /* command issue */
118 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
119 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
120 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
121 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
122 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
124 /* PORT_IRQ_{STAT,MASK} bits */
125 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
126 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
127 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
128 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
129 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
130 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
131 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
132 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
134 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
135 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
136 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
137 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
138 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
139 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
140 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
141 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
142 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
144 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
150 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
152 PORT_IRQ_HBUS_DATA_ERR,
153 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
154 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
155 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
158 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
159 PORT_CMD_PMP = (1 << 17), /* PMP attached */
160 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
161 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
162 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
163 PORT_CMD_CLO = (1 << 3), /* Command list override */
164 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
165 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
166 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
168 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
169 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
170 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
171 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
173 /* hpriv->flags bits */
174 AHCI_HFLAG_NO_NCQ = (1 << 0),
175 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
176 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
177 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
178 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
179 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
180 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
183 AHCI_FLAG_NO_HOTPLUG = (1 << 24), /* ignore PxSERR.DIAG.N */
185 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
186 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
187 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
188 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
191 struct ahci_cmd_hdr {
206 struct ahci_host_priv {
207 unsigned int flags; /* AHCI_HFLAG_* */
208 u32 cap; /* cap to use */
209 u32 port_map; /* port map to use */
210 u32 saved_cap; /* saved initial cap */
211 u32 saved_port_map; /* saved initial port_map */
214 struct ahci_port_priv {
215 struct ata_link *active_link;
216 struct ahci_cmd_hdr *cmd_slot;
217 dma_addr_t cmd_slot_dma;
219 dma_addr_t cmd_tbl_dma;
221 dma_addr_t rx_fis_dma;
222 /* for NCQ spurious interrupt analysis */
223 unsigned int ncq_saw_d2h:1;
224 unsigned int ncq_saw_dmas:1;
225 unsigned int ncq_saw_sdb:1;
226 u32 intr_mask; /* interrupts to enable */
229 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
230 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
231 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
232 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
233 static void ahci_irq_clear(struct ata_port *ap);
234 static int ahci_port_start(struct ata_port *ap);
235 static void ahci_port_stop(struct ata_port *ap);
236 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
237 static void ahci_qc_prep(struct ata_queued_cmd *qc);
238 static u8 ahci_check_status(struct ata_port *ap);
239 static void ahci_freeze(struct ata_port *ap);
240 static void ahci_thaw(struct ata_port *ap);
241 static void ahci_pmp_attach(struct ata_port *ap);
242 static void ahci_pmp_detach(struct ata_port *ap);
243 static void ahci_error_handler(struct ata_port *ap);
244 static void ahci_vt8251_error_handler(struct ata_port *ap);
245 static void ahci_p5wdh_error_handler(struct ata_port *ap);
246 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
247 static int ahci_port_resume(struct ata_port *ap);
248 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
249 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
252 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
253 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
254 static int ahci_pci_device_resume(struct pci_dev *pdev);
257 static struct scsi_host_template ahci_sht = {
258 .module = THIS_MODULE,
260 .ioctl = ata_scsi_ioctl,
261 .queuecommand = ata_scsi_queuecmd,
262 .change_queue_depth = ata_scsi_change_queue_depth,
263 .can_queue = AHCI_MAX_CMDS - 1,
264 .this_id = ATA_SHT_THIS_ID,
265 .sg_tablesize = AHCI_MAX_SG,
266 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
267 .emulated = ATA_SHT_EMULATED,
268 .use_clustering = AHCI_USE_CLUSTERING,
269 .proc_name = DRV_NAME,
270 .dma_boundary = AHCI_DMA_BOUNDARY,
271 .slave_configure = ata_scsi_slave_config,
272 .slave_destroy = ata_scsi_slave_destroy,
273 .bios_param = ata_std_bios_param,
276 static const struct ata_port_operations ahci_ops = {
277 .check_status = ahci_check_status,
278 .check_altstatus = ahci_check_status,
279 .dev_select = ata_noop_dev_select,
281 .tf_read = ahci_tf_read,
283 .qc_defer = sata_pmp_qc_defer_cmd_switch,
284 .qc_prep = ahci_qc_prep,
285 .qc_issue = ahci_qc_issue,
287 .irq_clear = ahci_irq_clear,
289 .scr_read = ahci_scr_read,
290 .scr_write = ahci_scr_write,
292 .freeze = ahci_freeze,
295 .error_handler = ahci_error_handler,
296 .post_internal_cmd = ahci_post_internal_cmd,
298 .pmp_attach = ahci_pmp_attach,
299 .pmp_detach = ahci_pmp_detach,
302 .port_suspend = ahci_port_suspend,
303 .port_resume = ahci_port_resume,
306 .port_start = ahci_port_start,
307 .port_stop = ahci_port_stop,
310 static const struct ata_port_operations ahci_vt8251_ops = {
311 .check_status = ahci_check_status,
312 .check_altstatus = ahci_check_status,
313 .dev_select = ata_noop_dev_select,
315 .tf_read = ahci_tf_read,
317 .qc_defer = sata_pmp_qc_defer_cmd_switch,
318 .qc_prep = ahci_qc_prep,
319 .qc_issue = ahci_qc_issue,
321 .irq_clear = ahci_irq_clear,
323 .scr_read = ahci_scr_read,
324 .scr_write = ahci_scr_write,
326 .freeze = ahci_freeze,
329 .error_handler = ahci_vt8251_error_handler,
330 .post_internal_cmd = ahci_post_internal_cmd,
332 .pmp_attach = ahci_pmp_attach,
333 .pmp_detach = ahci_pmp_detach,
336 .port_suspend = ahci_port_suspend,
337 .port_resume = ahci_port_resume,
340 .port_start = ahci_port_start,
341 .port_stop = ahci_port_stop,
344 static const struct ata_port_operations ahci_p5wdh_ops = {
345 .check_status = ahci_check_status,
346 .check_altstatus = ahci_check_status,
347 .dev_select = ata_noop_dev_select,
349 .tf_read = ahci_tf_read,
351 .qc_defer = sata_pmp_qc_defer_cmd_switch,
352 .qc_prep = ahci_qc_prep,
353 .qc_issue = ahci_qc_issue,
355 .irq_clear = ahci_irq_clear,
357 .scr_read = ahci_scr_read,
358 .scr_write = ahci_scr_write,
360 .freeze = ahci_freeze,
363 .error_handler = ahci_p5wdh_error_handler,
364 .post_internal_cmd = ahci_post_internal_cmd,
366 .pmp_attach = ahci_pmp_attach,
367 .pmp_detach = ahci_pmp_detach,
370 .port_suspend = ahci_port_suspend,
371 .port_resume = ahci_port_resume,
374 .port_start = ahci_port_start,
375 .port_stop = ahci_port_stop,
378 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
380 static const struct ata_port_info ahci_port_info[] = {
383 .flags = AHCI_FLAG_COMMON,
384 .link_flags = AHCI_LFLAG_COMMON,
385 .pio_mask = 0x1f, /* pio0-4 */
386 .udma_mask = ATA_UDMA6,
387 .port_ops = &ahci_ops,
389 /* board_ahci_vt8251 */
391 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
392 .flags = AHCI_FLAG_COMMON,
393 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
394 .pio_mask = 0x1f, /* pio0-4 */
395 .udma_mask = ATA_UDMA6,
396 .port_ops = &ahci_vt8251_ops,
398 /* board_ahci_ign_iferr */
400 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
401 .flags = AHCI_FLAG_COMMON,
402 .link_flags = AHCI_LFLAG_COMMON,
403 .pio_mask = 0x1f, /* pio0-4 */
404 .udma_mask = ATA_UDMA6,
405 .port_ops = &ahci_ops,
407 /* board_ahci_sb600 */
409 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
410 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
411 .flags = AHCI_FLAG_COMMON,
412 .link_flags = AHCI_LFLAG_COMMON,
413 .pio_mask = 0x1f, /* pio0-4 */
414 .udma_mask = ATA_UDMA6,
415 .port_ops = &ahci_ops,
419 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
421 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
422 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
423 .link_flags = AHCI_LFLAG_COMMON,
424 .pio_mask = 0x1f, /* pio0-4 */
425 .udma_mask = ATA_UDMA6,
426 .port_ops = &ahci_ops,
430 static const struct pci_device_id ahci_pci_tbl[] = {
432 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
433 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
434 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
435 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
436 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
437 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
438 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
439 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
440 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
441 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
442 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
443 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
444 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
445 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
446 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
447 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
448 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
449 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
450 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
451 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
452 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
453 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
454 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
455 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
456 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
457 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
458 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
459 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
460 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
462 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
463 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
464 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
467 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
468 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
469 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
470 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
471 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
472 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
473 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
476 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
477 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
480 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
482 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
484 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
485 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
486 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
487 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
488 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
496 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
497 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
498 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
499 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
500 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
501 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
502 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
503 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
504 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
505 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
506 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
507 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
508 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
509 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
510 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
511 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
513 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
514 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
515 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
516 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
517 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
518 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
519 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
520 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
521 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
522 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
523 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
525 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
526 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
527 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
528 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
529 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
530 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
531 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
534 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
535 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
536 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
539 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
541 /* Generic, PCI class code for AHCI */
542 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
543 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
545 { } /* terminate list */
549 static struct pci_driver ahci_pci_driver = {
551 .id_table = ahci_pci_tbl,
552 .probe = ahci_init_one,
553 .remove = ata_pci_remove_one,
555 .suspend = ahci_pci_device_suspend,
556 .resume = ahci_pci_device_resume,
561 static inline int ahci_nr_ports(u32 cap)
563 return (cap & 0x1f) + 1;
566 static inline void __iomem *__ahci_port_base(struct ata_host *host,
567 unsigned int port_no)
569 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
571 return mmio + 0x100 + (port_no * 0x80);
574 static inline void __iomem *ahci_port_base(struct ata_port *ap)
576 return __ahci_port_base(ap->host, ap->port_no);
580 * ahci_save_initial_config - Save and fixup initial config values
581 * @pdev: target PCI device
582 * @hpriv: host private area to store config values
584 * Some registers containing configuration info might be setup by
585 * BIOS and might be cleared on reset. This function saves the
586 * initial values of those registers into @hpriv such that they
587 * can be restored after controller reset.
589 * If inconsistent, config values are fixed up by this function.
594 static void ahci_save_initial_config(struct pci_dev *pdev,
595 struct ahci_host_priv *hpriv)
597 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
601 /* Values prefixed with saved_ are written back to host after
602 * reset. Values without are used for driver operation.
604 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
605 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
607 /* some chips have errata preventing 64bit use */
608 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
609 dev_printk(KERN_INFO, &pdev->dev,
610 "controller can't do 64bit DMA, forcing 32bit\n");
614 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
615 dev_printk(KERN_INFO, &pdev->dev,
616 "controller can't do NCQ, turning off CAP_NCQ\n");
617 cap &= ~HOST_CAP_NCQ;
620 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
621 dev_printk(KERN_INFO, &pdev->dev,
622 "controller can't do PMP, turning off CAP_PMP\n");
623 cap &= ~HOST_CAP_PMP;
627 * Temporary Marvell 6145 hack: PATA port presence
628 * is asserted through the standard AHCI port
629 * presence register, as bit 4 (counting from 0)
631 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
632 dev_printk(KERN_ERR, &pdev->dev,
633 "MV_AHCI HACK: port_map %x -> %x\n",
635 hpriv->port_map & 0xf);
640 /* cross check port_map and cap.n_ports */
642 u32 tmp_port_map = port_map;
643 int n_ports = ahci_nr_ports(cap);
645 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
646 if (tmp_port_map & (1 << i)) {
648 tmp_port_map &= ~(1 << i);
652 /* If n_ports and port_map are inconsistent, whine and
653 * clear port_map and let it be generated from n_ports.
655 if (n_ports || tmp_port_map) {
656 dev_printk(KERN_WARNING, &pdev->dev,
657 "nr_ports (%u) and implemented port map "
658 "(0x%x) don't match, using nr_ports\n",
659 ahci_nr_ports(cap), port_map);
664 /* fabricate port_map from cap.nr_ports */
666 port_map = (1 << ahci_nr_ports(cap)) - 1;
667 dev_printk(KERN_WARNING, &pdev->dev,
668 "forcing PORTS_IMPL to 0x%x\n", port_map);
670 /* write the fixed up value to the PI register */
671 hpriv->saved_port_map = port_map;
674 /* record values to use during operation */
676 hpriv->port_map = port_map;
680 * ahci_restore_initial_config - Restore initial config
681 * @host: target ATA host
683 * Restore initial config stored by ahci_save_initial_config().
688 static void ahci_restore_initial_config(struct ata_host *host)
690 struct ahci_host_priv *hpriv = host->private_data;
691 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
693 writel(hpriv->saved_cap, mmio + HOST_CAP);
694 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
695 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
698 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
700 static const int offset[] = {
701 [SCR_STATUS] = PORT_SCR_STAT,
702 [SCR_CONTROL] = PORT_SCR_CTL,
703 [SCR_ERROR] = PORT_SCR_ERR,
704 [SCR_ACTIVE] = PORT_SCR_ACT,
705 [SCR_NOTIFICATION] = PORT_SCR_NTF,
707 struct ahci_host_priv *hpriv = ap->host->private_data;
709 if (sc_reg < ARRAY_SIZE(offset) &&
710 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
711 return offset[sc_reg];
715 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
717 void __iomem *port_mmio = ahci_port_base(ap);
718 int offset = ahci_scr_offset(ap, sc_reg);
721 *val = readl(port_mmio + offset);
727 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
729 void __iomem *port_mmio = ahci_port_base(ap);
730 int offset = ahci_scr_offset(ap, sc_reg);
733 writel(val, port_mmio + offset);
739 static void ahci_start_engine(struct ata_port *ap)
741 void __iomem *port_mmio = ahci_port_base(ap);
745 tmp = readl(port_mmio + PORT_CMD);
746 tmp |= PORT_CMD_START;
747 writel(tmp, port_mmio + PORT_CMD);
748 readl(port_mmio + PORT_CMD); /* flush */
751 static int ahci_stop_engine(struct ata_port *ap)
753 void __iomem *port_mmio = ahci_port_base(ap);
756 tmp = readl(port_mmio + PORT_CMD);
758 /* check if the HBA is idle */
759 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
762 /* setting HBA to idle */
763 tmp &= ~PORT_CMD_START;
764 writel(tmp, port_mmio + PORT_CMD);
766 /* wait for engine to stop. This could be as long as 500 msec */
767 tmp = ata_wait_register(port_mmio + PORT_CMD,
768 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
769 if (tmp & PORT_CMD_LIST_ON)
775 static void ahci_start_fis_rx(struct ata_port *ap)
777 void __iomem *port_mmio = ahci_port_base(ap);
778 struct ahci_host_priv *hpriv = ap->host->private_data;
779 struct ahci_port_priv *pp = ap->private_data;
782 /* set FIS registers */
783 if (hpriv->cap & HOST_CAP_64)
784 writel((pp->cmd_slot_dma >> 16) >> 16,
785 port_mmio + PORT_LST_ADDR_HI);
786 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
788 if (hpriv->cap & HOST_CAP_64)
789 writel((pp->rx_fis_dma >> 16) >> 16,
790 port_mmio + PORT_FIS_ADDR_HI);
791 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
793 /* enable FIS reception */
794 tmp = readl(port_mmio + PORT_CMD);
795 tmp |= PORT_CMD_FIS_RX;
796 writel(tmp, port_mmio + PORT_CMD);
799 readl(port_mmio + PORT_CMD);
802 static int ahci_stop_fis_rx(struct ata_port *ap)
804 void __iomem *port_mmio = ahci_port_base(ap);
807 /* disable FIS reception */
808 tmp = readl(port_mmio + PORT_CMD);
809 tmp &= ~PORT_CMD_FIS_RX;
810 writel(tmp, port_mmio + PORT_CMD);
812 /* wait for completion, spec says 500ms, give it 1000 */
813 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
814 PORT_CMD_FIS_ON, 10, 1000);
815 if (tmp & PORT_CMD_FIS_ON)
821 static void ahci_power_up(struct ata_port *ap)
823 struct ahci_host_priv *hpriv = ap->host->private_data;
824 void __iomem *port_mmio = ahci_port_base(ap);
827 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
830 if (hpriv->cap & HOST_CAP_SSS) {
831 cmd |= PORT_CMD_SPIN_UP;
832 writel(cmd, port_mmio + PORT_CMD);
836 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
840 static void ahci_power_down(struct ata_port *ap)
842 struct ahci_host_priv *hpriv = ap->host->private_data;
843 void __iomem *port_mmio = ahci_port_base(ap);
846 if (!(hpriv->cap & HOST_CAP_SSS))
849 /* put device into listen mode, first set PxSCTL.DET to 0 */
850 scontrol = readl(port_mmio + PORT_SCR_CTL);
852 writel(scontrol, port_mmio + PORT_SCR_CTL);
854 /* then set PxCMD.SUD to 0 */
855 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
856 cmd &= ~PORT_CMD_SPIN_UP;
857 writel(cmd, port_mmio + PORT_CMD);
861 static void ahci_start_port(struct ata_port *ap)
863 /* enable FIS reception */
864 ahci_start_fis_rx(ap);
867 ahci_start_engine(ap);
870 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
875 rc = ahci_stop_engine(ap);
877 *emsg = "failed to stop engine";
881 /* disable FIS reception */
882 rc = ahci_stop_fis_rx(ap);
884 *emsg = "failed stop FIS RX";
891 static int ahci_reset_controller(struct ata_host *host)
893 struct pci_dev *pdev = to_pci_dev(host->dev);
894 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
897 /* we must be in AHCI mode, before using anything
898 * AHCI-specific, such as HOST_RESET.
900 tmp = readl(mmio + HOST_CTL);
901 if (!(tmp & HOST_AHCI_EN))
902 writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
904 /* global controller reset */
905 if ((tmp & HOST_RESET) == 0) {
906 writel(tmp | HOST_RESET, mmio + HOST_CTL);
907 readl(mmio + HOST_CTL); /* flush */
910 /* reset must complete within 1 second, or
911 * the hardware should be considered fried.
915 tmp = readl(mmio + HOST_CTL);
916 if (tmp & HOST_RESET) {
917 dev_printk(KERN_ERR, host->dev,
918 "controller reset failed (0x%x)\n", tmp);
922 /* turn on AHCI mode */
923 writel(HOST_AHCI_EN, mmio + HOST_CTL);
924 (void) readl(mmio + HOST_CTL); /* flush */
926 /* some registers might be cleared on reset. restore initial values */
927 ahci_restore_initial_config(host);
929 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
933 pci_read_config_word(pdev, 0x92, &tmp16);
935 pci_write_config_word(pdev, 0x92, tmp16);
941 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
942 int port_no, void __iomem *mmio,
943 void __iomem *port_mmio)
945 const char *emsg = NULL;
949 /* make sure port is not active */
950 rc = ahci_deinit_port(ap, &emsg);
952 dev_printk(KERN_WARNING, &pdev->dev,
953 "%s (%d)\n", emsg, rc);
956 tmp = readl(port_mmio + PORT_SCR_ERR);
957 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
958 writel(tmp, port_mmio + PORT_SCR_ERR);
961 tmp = readl(port_mmio + PORT_IRQ_STAT);
962 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
964 writel(tmp, port_mmio + PORT_IRQ_STAT);
966 writel(1 << port_no, mmio + HOST_IRQ_STAT);
969 static void ahci_init_controller(struct ata_host *host)
971 struct ahci_host_priv *hpriv = host->private_data;
972 struct pci_dev *pdev = to_pci_dev(host->dev);
973 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
975 void __iomem *port_mmio;
978 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
979 port_mmio = __ahci_port_base(host, 4);
981 writel(0, port_mmio + PORT_IRQ_MASK);
984 tmp = readl(port_mmio + PORT_IRQ_STAT);
985 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
987 writel(tmp, port_mmio + PORT_IRQ_STAT);
990 for (i = 0; i < host->n_ports; i++) {
991 struct ata_port *ap = host->ports[i];
993 port_mmio = ahci_port_base(ap);
994 if (ata_port_is_dummy(ap))
997 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1000 tmp = readl(mmio + HOST_CTL);
1001 VPRINTK("HOST_CTL 0x%x\n", tmp);
1002 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1003 tmp = readl(mmio + HOST_CTL);
1004 VPRINTK("HOST_CTL 0x%x\n", tmp);
1007 static unsigned int ahci_dev_classify(struct ata_port *ap)
1009 void __iomem *port_mmio = ahci_port_base(ap);
1010 struct ata_taskfile tf;
1013 tmp = readl(port_mmio + PORT_SIG);
1014 tf.lbah = (tmp >> 24) & 0xff;
1015 tf.lbam = (tmp >> 16) & 0xff;
1016 tf.lbal = (tmp >> 8) & 0xff;
1017 tf.nsect = (tmp) & 0xff;
1019 return ata_dev_classify(&tf);
1022 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1025 dma_addr_t cmd_tbl_dma;
1027 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1029 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1030 pp->cmd_slot[tag].status = 0;
1031 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1032 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1035 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1037 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1038 struct ahci_host_priv *hpriv = ap->host->private_data;
1042 /* do we need to kick the port? */
1043 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1044 if (!busy && !force_restart)
1048 rc = ahci_stop_engine(ap);
1052 /* need to do CLO? */
1058 if (!(hpriv->cap & HOST_CAP_CLO)) {
1064 tmp = readl(port_mmio + PORT_CMD);
1065 tmp |= PORT_CMD_CLO;
1066 writel(tmp, port_mmio + PORT_CMD);
1069 tmp = ata_wait_register(port_mmio + PORT_CMD,
1070 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1071 if (tmp & PORT_CMD_CLO)
1074 /* restart engine */
1076 ahci_start_engine(ap);
1080 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1081 struct ata_taskfile *tf, int is_cmd, u16 flags,
1082 unsigned long timeout_msec)
1084 const u32 cmd_fis_len = 5; /* five dwords */
1085 struct ahci_port_priv *pp = ap->private_data;
1086 void __iomem *port_mmio = ahci_port_base(ap);
1087 u8 *fis = pp->cmd_tbl;
1090 /* prep the command */
1091 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1092 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1095 writel(1, port_mmio + PORT_CMD_ISSUE);
1098 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1101 ahci_kick_engine(ap, 1);
1105 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1110 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1111 int pmp, unsigned long deadline)
1113 struct ata_port *ap = link->ap;
1114 const char *reason = NULL;
1115 unsigned long now, msecs;
1116 struct ata_taskfile tf;
1121 if (ata_link_offline(link)) {
1122 DPRINTK("PHY reports no device\n");
1123 *class = ATA_DEV_NONE;
1127 /* prepare for SRST (AHCI-1.1 10.4.1) */
1128 rc = ahci_kick_engine(ap, 1);
1130 ata_link_printk(link, KERN_WARNING,
1131 "failed to reset engine (errno=%d)", rc);
1133 ata_tf_init(link->device, &tf);
1135 /* issue the first D2H Register FIS */
1138 if (time_after(now, deadline))
1139 msecs = jiffies_to_msecs(deadline - now);
1142 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1143 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1145 reason = "1st FIS failed";
1149 /* spec says at least 5us, but be generous and sleep for 1ms */
1152 /* issue the second D2H Register FIS */
1153 tf.ctl &= ~ATA_SRST;
1154 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1156 /* spec mandates ">= 2ms" before checking status.
1157 * We wait 150ms, because that was the magic delay used for
1158 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1159 * between when the ATA command register is written, and then
1160 * status is checked. Because waiting for "a while" before
1161 * checking status is fine, post SRST, we perform this magic
1162 * delay here as well.
1166 rc = ata_wait_ready(ap, deadline);
1167 /* link occupied, -ENODEV too is an error */
1169 reason = "device not ready";
1172 *class = ahci_dev_classify(ap);
1174 DPRINTK("EXIT, class=%u\n", *class);
1178 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1182 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1183 unsigned long deadline)
1187 if (link->ap->flags & ATA_FLAG_PMP)
1188 pmp = SATA_PMP_CTRL_PORT;
1190 return ahci_do_softreset(link, class, pmp, deadline);
1193 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1194 unsigned long deadline)
1196 struct ata_port *ap = link->ap;
1197 struct ahci_port_priv *pp = ap->private_data;
1198 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1199 struct ata_taskfile tf;
1204 ahci_stop_engine(ap);
1206 /* clear D2H reception area to properly wait for D2H FIS */
1207 ata_tf_init(link->device, &tf);
1209 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1211 rc = sata_std_hardreset(link, class, deadline);
1213 ahci_start_engine(ap);
1215 if (rc == 0 && ata_link_online(link))
1216 *class = ahci_dev_classify(ap);
1217 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1218 *class = ATA_DEV_NONE;
1220 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1224 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1225 unsigned long deadline)
1227 struct ata_port *ap = link->ap;
1233 ahci_stop_engine(ap);
1235 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1238 /* vt8251 needs SError cleared for the port to operate */
1239 ahci_scr_read(ap, SCR_ERROR, &serror);
1240 ahci_scr_write(ap, SCR_ERROR, serror);
1242 ahci_start_engine(ap);
1244 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1246 /* vt8251 doesn't clear BSY on signature FIS reception,
1247 * request follow-up softreset.
1249 return rc ?: -EAGAIN;
1252 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1253 unsigned long deadline)
1255 struct ata_port *ap = link->ap;
1256 struct ahci_port_priv *pp = ap->private_data;
1257 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1258 struct ata_taskfile tf;
1261 ahci_stop_engine(ap);
1263 /* clear D2H reception area to properly wait for D2H FIS */
1264 ata_tf_init(link->device, &tf);
1266 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1268 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1271 ahci_start_engine(ap);
1273 if (rc || ata_link_offline(link))
1276 /* spec mandates ">= 2ms" before checking status */
1279 /* The pseudo configuration device on SIMG4726 attached to
1280 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1281 * hardreset if no device is attached to the first downstream
1282 * port && the pseudo device locks up on SRST w/ PMP==0. To
1283 * work around this, wait for !BSY only briefly. If BSY isn't
1284 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1285 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1287 * Wait for two seconds. Devices attached to downstream port
1288 * which can't process the following IDENTIFY after this will
1289 * have to be reset again. For most cases, this should
1290 * suffice while making probing snappish enough.
1292 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1294 ahci_kick_engine(ap, 0);
1299 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1301 struct ata_port *ap = link->ap;
1302 void __iomem *port_mmio = ahci_port_base(ap);
1305 ata_std_postreset(link, class);
1307 /* Make sure port's ATAPI bit is set appropriately */
1308 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1309 if (*class == ATA_DEV_ATAPI)
1310 new_tmp |= PORT_CMD_ATAPI;
1312 new_tmp &= ~PORT_CMD_ATAPI;
1313 if (new_tmp != tmp) {
1314 writel(new_tmp, port_mmio + PORT_CMD);
1315 readl(port_mmio + PORT_CMD); /* flush */
1319 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1320 unsigned long deadline)
1322 return ahci_do_softreset(link, class, link->pmp, deadline);
1325 static u8 ahci_check_status(struct ata_port *ap)
1327 void __iomem *mmio = ap->ioaddr.cmd_addr;
1329 return readl(mmio + PORT_TFDATA) & 0xFF;
1332 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1334 struct ahci_port_priv *pp = ap->private_data;
1335 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1337 ata_tf_from_fis(d2h_fis, tf);
1340 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1342 struct scatterlist *sg;
1343 struct ahci_sg *ahci_sg;
1344 unsigned int n_sg = 0;
1349 * Next, the S/G list.
1351 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1352 ata_for_each_sg(sg, qc) {
1353 dma_addr_t addr = sg_dma_address(sg);
1354 u32 sg_len = sg_dma_len(sg);
1356 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1357 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1358 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1367 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1369 struct ata_port *ap = qc->ap;
1370 struct ahci_port_priv *pp = ap->private_data;
1371 int is_atapi = is_atapi_taskfile(&qc->tf);
1374 const u32 cmd_fis_len = 5; /* five dwords */
1375 unsigned int n_elem;
1378 * Fill in command table information. First, the header,
1379 * a SATA Register - Host to Device command FIS.
1381 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1383 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1385 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1386 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1390 if (qc->flags & ATA_QCFLAG_DMAMAP)
1391 n_elem = ahci_fill_sg(qc, cmd_tbl);
1394 * Fill in command slot information.
1396 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1397 if (qc->tf.flags & ATA_TFLAG_WRITE)
1398 opts |= AHCI_CMD_WRITE;
1400 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1402 ahci_fill_cmd_slot(pp, qc->tag, opts);
1405 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1407 struct ahci_host_priv *hpriv = ap->host->private_data;
1408 struct ahci_port_priv *pp = ap->private_data;
1409 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1410 struct ata_link *link = NULL;
1411 struct ata_queued_cmd *active_qc;
1412 struct ata_eh_info *active_ehi;
1415 /* determine active link */
1416 ata_port_for_each_link(link, ap)
1417 if (ata_link_active(link))
1422 active_qc = ata_qc_from_tag(ap, link->active_tag);
1423 active_ehi = &link->eh_info;
1425 /* record irq stat */
1426 ata_ehi_clear_desc(host_ehi);
1427 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1429 /* AHCI needs SError cleared; otherwise, it might lock up */
1430 ahci_scr_read(ap, SCR_ERROR, &serror);
1431 ahci_scr_write(ap, SCR_ERROR, serror);
1432 host_ehi->serror |= serror;
1434 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1435 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1436 irq_stat &= ~PORT_IRQ_IF_ERR;
1438 if (irq_stat & PORT_IRQ_TF_ERR) {
1439 /* If qc is active, charge it; otherwise, the active
1440 * link. There's no active qc on NCQ errors. It will
1441 * be determined by EH by reading log page 10h.
1444 active_qc->err_mask |= AC_ERR_DEV;
1446 active_ehi->err_mask |= AC_ERR_DEV;
1448 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1449 host_ehi->serror &= ~SERR_INTERNAL;
1452 if (irq_stat & PORT_IRQ_UNK_FIS) {
1453 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1455 active_ehi->err_mask |= AC_ERR_HSM;
1456 active_ehi->action |= ATA_EH_SOFTRESET;
1457 ata_ehi_push_desc(active_ehi,
1458 "unknown FIS %08x %08x %08x %08x" ,
1459 unk[0], unk[1], unk[2], unk[3]);
1462 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1463 active_ehi->err_mask |= AC_ERR_HSM;
1464 active_ehi->action |= ATA_EH_SOFTRESET;
1465 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1468 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1469 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1470 host_ehi->action |= ATA_EH_SOFTRESET;
1471 ata_ehi_push_desc(host_ehi, "host bus error");
1474 if (irq_stat & PORT_IRQ_IF_ERR) {
1475 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1476 host_ehi->action |= ATA_EH_SOFTRESET;
1477 ata_ehi_push_desc(host_ehi, "interface fatal error");
1480 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1481 ata_ehi_hotplugged(host_ehi);
1482 ata_ehi_push_desc(host_ehi, "%s",
1483 irq_stat & PORT_IRQ_CONNECT ?
1484 "connection status changed" : "PHY RDY changed");
1487 /* okay, let's hand over to EH */
1489 if (irq_stat & PORT_IRQ_FREEZE)
1490 ata_port_freeze(ap);
1495 static void ahci_port_intr(struct ata_port *ap)
1497 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1498 struct ata_eh_info *ehi = &ap->link.eh_info;
1499 struct ahci_port_priv *pp = ap->private_data;
1500 struct ahci_host_priv *hpriv = ap->host->private_data;
1501 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1502 u32 status, qc_active;
1503 int rc, known_irq = 0;
1505 status = readl(port_mmio + PORT_IRQ_STAT);
1506 writel(status, port_mmio + PORT_IRQ_STAT);
1508 /* ignore BAD_PMP while resetting */
1509 if (unlikely(resetting))
1510 status &= ~PORT_IRQ_BAD_PMP;
1512 if (unlikely(status & PORT_IRQ_ERROR)) {
1513 ahci_error_intr(ap, status);
1517 if (status & PORT_IRQ_SDB_FIS) {
1518 /* If SNotification is available, leave notification
1519 * handling to sata_async_notification(). If not,
1520 * emulate it by snooping SDB FIS RX area.
1522 * Snooping FIS RX area is probably cheaper than
1523 * poking SNotification but some constrollers which
1524 * implement SNotification, ICH9 for example, don't
1525 * store AN SDB FIS into receive area.
1527 if (hpriv->cap & HOST_CAP_SNTF)
1528 sata_async_notification(ap);
1530 /* If the 'N' bit in word 0 of the FIS is set,
1531 * we just received asynchronous notification.
1532 * Tell libata about it.
1534 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1535 u32 f0 = le32_to_cpu(f[0]);
1538 sata_async_notification(ap);
1542 /* pp->active_link is valid iff any command is in flight */
1543 if (ap->qc_active && pp->active_link->sactive)
1544 qc_active = readl(port_mmio + PORT_SCR_ACT);
1546 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1548 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1550 /* If resetting, spurious or invalid completions are expected,
1551 * return unconditionally.
1559 ehi->err_mask |= AC_ERR_HSM;
1560 ehi->action |= ATA_EH_SOFTRESET;
1561 ata_port_freeze(ap);
1565 /* hmmm... a spurious interrupt */
1567 /* if !NCQ, ignore. No modern ATA device has broken HSM
1568 * implementation for non-NCQ commands.
1570 if (!ap->link.sactive)
1573 if (status & PORT_IRQ_D2H_REG_FIS) {
1574 if (!pp->ncq_saw_d2h)
1575 ata_port_printk(ap, KERN_INFO,
1576 "D2H reg with I during NCQ, "
1577 "this message won't be printed again\n");
1578 pp->ncq_saw_d2h = 1;
1582 if (status & PORT_IRQ_DMAS_FIS) {
1583 if (!pp->ncq_saw_dmas)
1584 ata_port_printk(ap, KERN_INFO,
1585 "DMAS FIS during NCQ, "
1586 "this message won't be printed again\n");
1587 pp->ncq_saw_dmas = 1;
1591 if (status & PORT_IRQ_SDB_FIS) {
1592 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1594 if (le32_to_cpu(f[1])) {
1595 /* SDB FIS containing spurious completions
1596 * might be dangerous, whine and fail commands
1597 * with HSM violation. EH will turn off NCQ
1598 * after several such failures.
1600 ata_ehi_push_desc(ehi,
1601 "spurious completions during NCQ "
1602 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1603 readl(port_mmio + PORT_CMD_ISSUE),
1604 readl(port_mmio + PORT_SCR_ACT),
1605 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1606 ehi->err_mask |= AC_ERR_HSM;
1607 ehi->action |= ATA_EH_SOFTRESET;
1608 ata_port_freeze(ap);
1610 if (!pp->ncq_saw_sdb)
1611 ata_port_printk(ap, KERN_INFO,
1612 "spurious SDB FIS %08x:%08x during NCQ, "
1613 "this message won't be printed again\n",
1614 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1615 pp->ncq_saw_sdb = 1;
1621 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1622 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1623 status, ap->link.active_tag, ap->link.sactive);
1626 static void ahci_irq_clear(struct ata_port *ap)
1631 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1633 struct ata_host *host = dev_instance;
1634 struct ahci_host_priv *hpriv;
1635 unsigned int i, handled = 0;
1637 u32 irq_stat, irq_ack = 0;
1641 hpriv = host->private_data;
1642 mmio = host->iomap[AHCI_PCI_BAR];
1644 /* sigh. 0xffffffff is a valid return from h/w */
1645 irq_stat = readl(mmio + HOST_IRQ_STAT);
1646 irq_stat &= hpriv->port_map;
1650 spin_lock(&host->lock);
1652 for (i = 0; i < host->n_ports; i++) {
1653 struct ata_port *ap;
1655 if (!(irq_stat & (1 << i)))
1658 ap = host->ports[i];
1661 VPRINTK("port %u\n", i);
1663 VPRINTK("port %u (no irq)\n", i);
1664 if (ata_ratelimit())
1665 dev_printk(KERN_WARNING, host->dev,
1666 "interrupt on disabled port %u\n", i);
1669 irq_ack |= (1 << i);
1673 writel(irq_ack, mmio + HOST_IRQ_STAT);
1677 spin_unlock(&host->lock);
1681 return IRQ_RETVAL(handled);
1684 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1686 struct ata_port *ap = qc->ap;
1687 void __iomem *port_mmio = ahci_port_base(ap);
1688 struct ahci_port_priv *pp = ap->private_data;
1690 /* Keep track of the currently active link. It will be used
1691 * in completion path to determine whether NCQ phase is in
1694 pp->active_link = qc->dev->link;
1696 if (qc->tf.protocol == ATA_PROT_NCQ)
1697 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1698 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1699 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1704 static void ahci_freeze(struct ata_port *ap)
1706 void __iomem *port_mmio = ahci_port_base(ap);
1709 writel(0, port_mmio + PORT_IRQ_MASK);
1712 static void ahci_thaw(struct ata_port *ap)
1714 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1715 void __iomem *port_mmio = ahci_port_base(ap);
1717 struct ahci_port_priv *pp = ap->private_data;
1720 tmp = readl(port_mmio + PORT_IRQ_STAT);
1721 writel(tmp, port_mmio + PORT_IRQ_STAT);
1722 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1724 /* turn IRQ back on */
1725 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1728 static void ahci_error_handler(struct ata_port *ap)
1730 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1731 /* restart engine */
1732 ahci_stop_engine(ap);
1733 ahci_start_engine(ap);
1736 /* perform recovery */
1737 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1738 ahci_hardreset, ahci_postreset,
1739 sata_pmp_std_prereset, ahci_pmp_softreset,
1740 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1743 static void ahci_vt8251_error_handler(struct ata_port *ap)
1745 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1746 /* restart engine */
1747 ahci_stop_engine(ap);
1748 ahci_start_engine(ap);
1751 /* perform recovery */
1752 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1756 static void ahci_p5wdh_error_handler(struct ata_port *ap)
1758 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1759 /* restart engine */
1760 ahci_stop_engine(ap);
1761 ahci_start_engine(ap);
1764 /* perform recovery */
1765 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1769 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1771 struct ata_port *ap = qc->ap;
1773 /* make DMA engine forget about the failed command */
1774 if (qc->flags & ATA_QCFLAG_FAILED)
1775 ahci_kick_engine(ap, 1);
1778 static void ahci_pmp_attach(struct ata_port *ap)
1780 void __iomem *port_mmio = ahci_port_base(ap);
1781 struct ahci_port_priv *pp = ap->private_data;
1784 cmd = readl(port_mmio + PORT_CMD);
1785 cmd |= PORT_CMD_PMP;
1786 writel(cmd, port_mmio + PORT_CMD);
1788 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1789 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1792 static void ahci_pmp_detach(struct ata_port *ap)
1794 void __iomem *port_mmio = ahci_port_base(ap);
1795 struct ahci_port_priv *pp = ap->private_data;
1798 cmd = readl(port_mmio + PORT_CMD);
1799 cmd &= ~PORT_CMD_PMP;
1800 writel(cmd, port_mmio + PORT_CMD);
1802 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1803 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1806 static int ahci_port_resume(struct ata_port *ap)
1809 ahci_start_port(ap);
1811 if (ap->nr_pmp_links)
1812 ahci_pmp_attach(ap);
1814 ahci_pmp_detach(ap);
1820 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1822 const char *emsg = NULL;
1825 rc = ahci_deinit_port(ap, &emsg);
1827 ahci_power_down(ap);
1829 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1830 ahci_start_port(ap);
1836 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1838 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1839 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1842 if (mesg.event == PM_EVENT_SUSPEND) {
1843 /* AHCI spec rev1.1 section 8.3.3:
1844 * Software must disable interrupts prior to requesting a
1845 * transition of the HBA to D3 state.
1847 ctl = readl(mmio + HOST_CTL);
1848 ctl &= ~HOST_IRQ_EN;
1849 writel(ctl, mmio + HOST_CTL);
1850 readl(mmio + HOST_CTL); /* flush */
1853 return ata_pci_device_suspend(pdev, mesg);
1856 static int ahci_pci_device_resume(struct pci_dev *pdev)
1858 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1861 rc = ata_pci_device_do_resume(pdev);
1865 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1866 rc = ahci_reset_controller(host);
1870 ahci_init_controller(host);
1873 ata_host_resume(host);
1879 static int ahci_port_start(struct ata_port *ap)
1881 struct device *dev = ap->host->dev;
1882 struct ahci_port_priv *pp;
1887 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1891 rc = ata_pad_alloc(ap, dev);
1895 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1899 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1902 * First item in chunk of DMA memory: 32-slot command table,
1903 * 32 bytes each in size
1906 pp->cmd_slot_dma = mem_dma;
1908 mem += AHCI_CMD_SLOT_SZ;
1909 mem_dma += AHCI_CMD_SLOT_SZ;
1912 * Second item: Received-FIS area
1915 pp->rx_fis_dma = mem_dma;
1917 mem += AHCI_RX_FIS_SZ;
1918 mem_dma += AHCI_RX_FIS_SZ;
1921 * Third item: data area for storing a single command
1922 * and its scatter-gather table
1925 pp->cmd_tbl_dma = mem_dma;
1928 * Save off initial list of interrupts to be enabled.
1929 * This could be changed later
1931 pp->intr_mask = DEF_PORT_IRQ;
1933 ap->private_data = pp;
1935 /* engage engines, captain */
1936 return ahci_port_resume(ap);
1939 static void ahci_port_stop(struct ata_port *ap)
1941 const char *emsg = NULL;
1944 /* de-initialize port */
1945 rc = ahci_deinit_port(ap, &emsg);
1947 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1950 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1955 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1956 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1958 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1960 dev_printk(KERN_ERR, &pdev->dev,
1961 "64-bit DMA enable failed\n");
1966 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1968 dev_printk(KERN_ERR, &pdev->dev,
1969 "32-bit DMA enable failed\n");
1972 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1974 dev_printk(KERN_ERR, &pdev->dev,
1975 "32-bit consistent DMA enable failed\n");
1982 static void ahci_print_info(struct ata_host *host)
1984 struct ahci_host_priv *hpriv = host->private_data;
1985 struct pci_dev *pdev = to_pci_dev(host->dev);
1986 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1987 u32 vers, cap, impl, speed;
1988 const char *speed_s;
1992 vers = readl(mmio + HOST_VERSION);
1994 impl = hpriv->port_map;
1996 speed = (cap >> 20) & 0xf;
1999 else if (speed == 2)
2004 pci_read_config_word(pdev, 0x0a, &cc);
2005 if (cc == PCI_CLASS_STORAGE_IDE)
2007 else if (cc == PCI_CLASS_STORAGE_SATA)
2009 else if (cc == PCI_CLASS_STORAGE_RAID)
2014 dev_printk(KERN_INFO, &pdev->dev,
2015 "AHCI %02x%02x.%02x%02x "
2016 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2019 (vers >> 24) & 0xff,
2020 (vers >> 16) & 0xff,
2024 ((cap >> 8) & 0x1f) + 1,
2030 dev_printk(KERN_INFO, &pdev->dev,
2036 cap & (1 << 31) ? "64bit " : "",
2037 cap & (1 << 30) ? "ncq " : "",
2038 cap & (1 << 29) ? "sntf " : "",
2039 cap & (1 << 28) ? "ilck " : "",
2040 cap & (1 << 27) ? "stag " : "",
2041 cap & (1 << 26) ? "pm " : "",
2042 cap & (1 << 25) ? "led " : "",
2044 cap & (1 << 24) ? "clo " : "",
2045 cap & (1 << 19) ? "nz " : "",
2046 cap & (1 << 18) ? "only " : "",
2047 cap & (1 << 17) ? "pmp " : "",
2048 cap & (1 << 15) ? "pio " : "",
2049 cap & (1 << 14) ? "slum " : "",
2050 cap & (1 << 13) ? "part " : ""
2054 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2055 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2056 * support PMP and the 4726 either directly exports the device
2057 * attached to the first downstream port or acts as a hardware storage
2058 * controller and emulate a single ATA device (can be RAID 0/1 or some
2059 * other configuration).
2061 * When there's no device attached to the first downstream port of the
2062 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2063 * configure the 4726. However, ATA emulation of the device is very
2064 * lame. It doesn't send signature D2H Reg FIS after the initial
2065 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2067 * The following function works around the problem by always using
2068 * hardreset on the port and not depending on receiving signature FIS
2069 * afterward. If signature FIS isn't received soon, ATA class is
2070 * assumed without follow-up softreset.
2072 static void ahci_p5wdh_workaround(struct ata_host *host)
2074 static struct dmi_system_id sysids[] = {
2076 .ident = "P5W DH Deluxe",
2078 DMI_MATCH(DMI_SYS_VENDOR,
2079 "ASUSTEK COMPUTER INC"),
2080 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2085 struct pci_dev *pdev = to_pci_dev(host->dev);
2087 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2088 dmi_check_system(sysids)) {
2089 struct ata_port *ap = host->ports[1];
2091 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2092 "Deluxe on-board SIMG4726 workaround\n");
2094 ap->ops = &ahci_p5wdh_ops;
2095 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2099 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2101 static int printed_version;
2102 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2103 const struct ata_port_info *ppi[] = { &pi, NULL };
2104 struct device *dev = &pdev->dev;
2105 struct ahci_host_priv *hpriv;
2106 struct ata_host *host;
2111 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2113 if (!printed_version++)
2114 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2116 /* acquire resources */
2117 rc = pcim_enable_device(pdev);
2121 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2123 pcim_pin_device(pdev);
2127 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2130 hpriv->flags |= (unsigned long)pi.private_data;
2132 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2135 /* save initial config */
2136 ahci_save_initial_config(pdev, hpriv);
2139 if (hpriv->cap & HOST_CAP_NCQ)
2140 pi.flags |= ATA_FLAG_NCQ;
2142 if (hpriv->cap & HOST_CAP_PMP)
2143 pi.flags |= ATA_FLAG_PMP;
2145 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2148 host->iomap = pcim_iomap_table(pdev);
2149 host->private_data = hpriv;
2151 for (i = 0; i < host->n_ports; i++) {
2152 struct ata_port *ap = host->ports[i];
2153 void __iomem *port_mmio = ahci_port_base(ap);
2155 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2156 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2157 0x100 + ap->port_no * 0x80, "port");
2159 /* standard SATA port setup */
2160 if (hpriv->port_map & (1 << i))
2161 ap->ioaddr.cmd_addr = port_mmio;
2163 /* disabled/not-implemented port */
2165 ap->ops = &ata_dummy_port_ops;
2168 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2169 ahci_p5wdh_workaround(host);
2171 /* initialize adapter */
2172 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2176 rc = ahci_reset_controller(host);
2180 ahci_init_controller(host);
2181 ahci_print_info(host);
2183 pci_set_master(pdev);
2184 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2188 static int __init ahci_init(void)
2190 return pci_register_driver(&ahci_pci_driver);
2193 static void __exit ahci_exit(void)
2195 pci_unregister_driver(&ahci_pci_driver);
2199 MODULE_AUTHOR("Jeff Garzik");
2200 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2201 MODULE_LICENSE("GPL");
2202 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2203 MODULE_VERSION(DRV_VERSION);
2205 module_init(ahci_init);
2206 module_exit(ahci_exit);