2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
58 board_ahci_vt8251 = 1,
59 board_ahci_ign_iferr = 2,
62 board_ahci_sb700 = 5, /* for SB700 and SB800 */
65 board_ahci_yesncq = 8,
66 board_ahci_nosntf = 9,
69 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
70 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
71 unsigned long deadline);
72 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
73 unsigned long deadline);
74 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
75 unsigned long deadline);
77 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
78 static int ahci_pci_device_resume(struct pci_dev *pdev);
81 static struct ata_port_operations ahci_vt8251_ops = {
82 .inherits = &ahci_ops,
83 .hardreset = ahci_vt8251_hardreset,
86 static struct ata_port_operations ahci_p5wdh_ops = {
87 .inherits = &ahci_ops,
88 .hardreset = ahci_p5wdh_hardreset,
91 static struct ata_port_operations ahci_sb600_ops = {
92 .inherits = &ahci_ops,
93 .softreset = ahci_sb600_softreset,
94 .pmp_softreset = ahci_sb600_softreset,
97 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
99 static const struct ata_port_info ahci_port_info[] = {
102 .flags = AHCI_FLAG_COMMON,
103 .pio_mask = ATA_PIO4,
104 .udma_mask = ATA_UDMA6,
105 .port_ops = &ahci_ops,
107 [board_ahci_vt8251] =
109 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
110 .flags = AHCI_FLAG_COMMON,
111 .pio_mask = ATA_PIO4,
112 .udma_mask = ATA_UDMA6,
113 .port_ops = &ahci_vt8251_ops,
115 [board_ahci_ign_iferr] =
117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
125 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
126 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
127 AHCI_HFLAG_32BIT_ONLY),
128 .flags = AHCI_FLAG_COMMON,
129 .pio_mask = ATA_PIO4,
130 .udma_mask = ATA_UDMA6,
131 .port_ops = &ahci_sb600_ops,
135 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
136 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
137 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
138 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_sb700] = /* for SB700 and SB800 */
145 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_sb600_ops,
153 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
161 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
167 [board_ahci_yesncq] =
169 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
170 .flags = AHCI_FLAG_COMMON,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
175 [board_ahci_nosntf] =
177 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
185 static const struct pci_device_id ahci_pci_tbl[] = {
187 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
188 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
189 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
190 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
191 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
192 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
193 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
194 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
195 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
196 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
197 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
198 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
199 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
200 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
201 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
202 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
203 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
204 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
205 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
206 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
207 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
208 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
209 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
210 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
211 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
212 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
214 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
215 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
216 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
217 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
218 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
219 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
220 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
221 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
222 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
223 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
224 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
225 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
226 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
228 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
229 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
230 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
231 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
232 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
234 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
235 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
236 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
239 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
240 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
241 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
242 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
243 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
244 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
245 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
248 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
249 /* AMD is using RAID class only for ahci controllers */
250 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
251 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
254 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
255 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
258 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
259 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
260 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
261 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
262 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
263 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
264 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
265 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
266 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
267 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
268 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
269 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
270 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
271 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
272 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
273 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
274 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
275 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
276 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
277 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
278 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq }, /* Linux ID */
279 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_yesncq }, /* Linux ID */
280 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_yesncq }, /* Linux ID */
281 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_yesncq }, /* Linux ID */
282 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_yesncq }, /* Linux ID */
283 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_yesncq }, /* Linux ID */
284 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_yesncq }, /* Linux ID */
285 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_yesncq }, /* Linux ID */
286 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_yesncq }, /* Linux ID */
287 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_yesncq }, /* Linux ID */
288 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_yesncq }, /* Linux ID */
289 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_yesncq }, /* Linux ID */
290 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_yesncq }, /* Linux ID */
291 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_yesncq }, /* Linux ID */
292 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_yesncq }, /* Linux ID */
293 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_yesncq }, /* Linux ID */
294 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
295 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
296 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
297 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
298 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
299 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
300 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
301 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
302 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
303 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
304 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
305 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
306 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
307 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
308 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
309 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
310 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
311 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
312 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
313 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
314 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
315 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
316 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
317 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
318 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
319 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
320 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
321 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
322 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
323 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
324 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
325 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
326 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
327 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
328 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
329 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
330 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
331 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
332 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
333 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
334 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
335 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
336 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
337 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
338 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
339 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
340 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
341 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
344 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
345 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
346 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
349 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
350 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
353 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
355 /* Generic, PCI class code for AHCI */
356 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
357 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
359 { } /* terminate list */
363 static struct pci_driver ahci_pci_driver = {
365 .id_table = ahci_pci_tbl,
366 .probe = ahci_init_one,
367 .remove = ata_pci_remove_one,
369 .suspend = ahci_pci_device_suspend,
370 .resume = ahci_pci_device_resume,
374 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
375 static int marvell_enable;
377 static int marvell_enable = 1;
379 module_param(marvell_enable, int, 0644);
380 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
383 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
384 struct ahci_host_priv *hpriv)
386 unsigned int force_port_map = 0;
387 unsigned int mask_port_map = 0;
389 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
390 dev_info(&pdev->dev, "JMB361 has only one port\n");
395 * Temporary Marvell 6145 hack: PATA port presence
396 * is asserted through the standard AHCI port
397 * presence register, as bit 4 (counting from 0)
399 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
400 if (pdev->device == 0x6121)
405 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
408 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
412 static int ahci_pci_reset_controller(struct ata_host *host)
414 struct pci_dev *pdev = to_pci_dev(host->dev);
416 ahci_reset_controller(host);
418 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
419 struct ahci_host_priv *hpriv = host->private_data;
423 pci_read_config_word(pdev, 0x92, &tmp16);
424 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
425 tmp16 |= hpriv->port_map;
426 pci_write_config_word(pdev, 0x92, tmp16);
433 static void ahci_pci_init_controller(struct ata_host *host)
435 struct ahci_host_priv *hpriv = host->private_data;
436 struct pci_dev *pdev = to_pci_dev(host->dev);
437 void __iomem *port_mmio;
441 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
442 if (pdev->device == 0x6121)
446 port_mmio = __ahci_port_base(host, mv);
448 writel(0, port_mmio + PORT_IRQ_MASK);
451 tmp = readl(port_mmio + PORT_IRQ_STAT);
452 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
454 writel(tmp, port_mmio + PORT_IRQ_STAT);
457 ahci_init_controller(host);
460 static int ahci_sb600_check_ready(struct ata_link *link)
462 void __iomem *port_mmio = ahci_port_base(link->ap);
463 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
464 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
467 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
468 * which can save timeout delay.
470 if (irq_status & PORT_IRQ_BAD_PMP)
473 return ata_check_ready(status);
476 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
477 unsigned long deadline)
479 struct ata_port *ap = link->ap;
480 void __iomem *port_mmio = ahci_port_base(ap);
481 int pmp = sata_srst_pmp(link);
487 rc = ahci_do_softreset(link, class, pmp, deadline,
488 ahci_sb600_check_ready);
491 * Soft reset fails on some ATI chips with IPMS set when PMP
492 * is enabled but SATA HDD/ODD is connected to SATA port,
493 * do soft reset again to port 0.
496 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
497 if (irq_sts & PORT_IRQ_BAD_PMP) {
498 ata_link_printk(link, KERN_WARNING,
499 "applying SB600 PMP SRST workaround "
501 rc = ahci_do_softreset(link, class, 0, deadline,
509 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
510 unsigned long deadline)
512 struct ata_port *ap = link->ap;
518 ahci_stop_engine(ap);
520 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
521 deadline, &online, NULL);
523 ahci_start_engine(ap);
525 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
527 /* vt8251 doesn't clear BSY on signature FIS reception,
528 * request follow-up softreset.
530 return online ? -EAGAIN : rc;
533 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
534 unsigned long deadline)
536 struct ata_port *ap = link->ap;
537 struct ahci_port_priv *pp = ap->private_data;
538 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
539 struct ata_taskfile tf;
543 ahci_stop_engine(ap);
545 /* clear D2H reception area to properly wait for D2H FIS */
546 ata_tf_init(link->device, &tf);
548 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
550 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
551 deadline, &online, NULL);
553 ahci_start_engine(ap);
555 /* The pseudo configuration device on SIMG4726 attached to
556 * ASUS P5W-DH Deluxe doesn't send signature FIS after
557 * hardreset if no device is attached to the first downstream
558 * port && the pseudo device locks up on SRST w/ PMP==0. To
559 * work around this, wait for !BSY only briefly. If BSY isn't
560 * cleared, perform CLO and proceed to IDENTIFY (achieved by
561 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
563 * Wait for two seconds. Devices attached to downstream port
564 * which can't process the following IDENTIFY after this will
565 * have to be reset again. For most cases, this should
566 * suffice while making probing snappish enough.
569 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
572 ahci_kick_engine(ap);
578 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
580 struct ata_host *host = dev_get_drvdata(&pdev->dev);
581 struct ahci_host_priv *hpriv = host->private_data;
582 void __iomem *mmio = hpriv->mmio;
585 if (mesg.event & PM_EVENT_SUSPEND &&
586 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
587 dev_printk(KERN_ERR, &pdev->dev,
588 "BIOS update required for suspend/resume\n");
592 if (mesg.event & PM_EVENT_SLEEP) {
593 /* AHCI spec rev1.1 section 8.3.3:
594 * Software must disable interrupts prior to requesting a
595 * transition of the HBA to D3 state.
597 ctl = readl(mmio + HOST_CTL);
599 writel(ctl, mmio + HOST_CTL);
600 readl(mmio + HOST_CTL); /* flush */
603 return ata_pci_device_suspend(pdev, mesg);
606 static int ahci_pci_device_resume(struct pci_dev *pdev)
608 struct ata_host *host = dev_get_drvdata(&pdev->dev);
611 rc = ata_pci_device_do_resume(pdev);
615 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
616 rc = ahci_pci_reset_controller(host);
620 ahci_pci_init_controller(host);
623 ata_host_resume(host);
629 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
634 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
635 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
637 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
639 dev_printk(KERN_ERR, &pdev->dev,
640 "64-bit DMA enable failed\n");
645 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
647 dev_printk(KERN_ERR, &pdev->dev,
648 "32-bit DMA enable failed\n");
651 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
653 dev_printk(KERN_ERR, &pdev->dev,
654 "32-bit consistent DMA enable failed\n");
661 static void ahci_pci_print_info(struct ata_host *host)
663 struct pci_dev *pdev = to_pci_dev(host->dev);
667 pci_read_config_word(pdev, 0x0a, &cc);
668 if (cc == PCI_CLASS_STORAGE_IDE)
670 else if (cc == PCI_CLASS_STORAGE_SATA)
672 else if (cc == PCI_CLASS_STORAGE_RAID)
677 ahci_print_info(host, scc_s);
680 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
681 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
682 * support PMP and the 4726 either directly exports the device
683 * attached to the first downstream port or acts as a hardware storage
684 * controller and emulate a single ATA device (can be RAID 0/1 or some
685 * other configuration).
687 * When there's no device attached to the first downstream port of the
688 * 4726, "Config Disk" appears, which is a pseudo ATA device to
689 * configure the 4726. However, ATA emulation of the device is very
690 * lame. It doesn't send signature D2H Reg FIS after the initial
691 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
693 * The following function works around the problem by always using
694 * hardreset on the port and not depending on receiving signature FIS
695 * afterward. If signature FIS isn't received soon, ATA class is
696 * assumed without follow-up softreset.
698 static void ahci_p5wdh_workaround(struct ata_host *host)
700 static struct dmi_system_id sysids[] = {
702 .ident = "P5W DH Deluxe",
704 DMI_MATCH(DMI_SYS_VENDOR,
705 "ASUSTEK COMPUTER INC"),
706 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
711 struct pci_dev *pdev = to_pci_dev(host->dev);
713 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
714 dmi_check_system(sysids)) {
715 struct ata_port *ap = host->ports[1];
717 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
718 "Deluxe on-board SIMG4726 workaround\n");
720 ap->ops = &ahci_p5wdh_ops;
721 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
725 /* only some SB600 ahci controllers can do 64bit DMA */
726 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
728 static const struct dmi_system_id sysids[] = {
730 * The oldest version known to be broken is 0901 and
731 * working is 1501 which was released on 2007-10-26.
732 * Enable 64bit DMA on 1501 and anything newer.
734 * Please read bko#9412 for more info.
737 .ident = "ASUS M2A-VM",
739 DMI_MATCH(DMI_BOARD_VENDOR,
740 "ASUSTeK Computer INC."),
741 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
743 .driver_data = "20071026", /* yyyymmdd */
746 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
749 * BIOS versions earlier than 1.5 had the Manufacturer DMI
750 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
751 * This spelling mistake was fixed in BIOS version 1.5, so
752 * 1.5 and later have the Manufacturer as
753 * "MICRO-STAR INTERNATIONAL CO.,LTD".
754 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
756 * BIOS versions earlier than 1.9 had a Board Product Name
757 * DMI field of "MS-7376". This was changed to be
758 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
759 * match on DMI_BOARD_NAME of "MS-7376".
762 .ident = "MSI K9A2 Platinum",
764 DMI_MATCH(DMI_BOARD_VENDOR,
766 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
771 const struct dmi_system_id *match;
772 int year, month, date;
775 match = dmi_first_match(sysids);
776 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
780 if (!match->driver_data)
783 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
784 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
786 if (strcmp(buf, match->driver_data) >= 0)
789 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
790 "forcing 32bit DMA, update BIOS\n", match->ident);
795 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
800 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
802 static const struct dmi_system_id broken_systems[] = {
804 .ident = "HP Compaq nx6310",
806 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
807 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
809 /* PCI slot number of the controller */
810 .driver_data = (void *)0x1FUL,
813 .ident = "HP Compaq 6720s",
815 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
816 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
818 /* PCI slot number of the controller */
819 .driver_data = (void *)0x1FUL,
822 { } /* terminate list */
824 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
827 unsigned long slot = (unsigned long)dmi->driver_data;
828 /* apply the quirk only to on-board controllers */
829 return slot == PCI_SLOT(pdev->devfn);
835 static bool ahci_broken_suspend(struct pci_dev *pdev)
837 static const struct dmi_system_id sysids[] = {
839 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
840 * to the harddisk doesn't become online after
841 * resuming from STR. Warn and fail suspend.
843 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
845 * Use dates instead of versions to match as HP is
846 * apparently recycling both product and version
849 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
854 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
855 DMI_MATCH(DMI_PRODUCT_NAME,
856 "HP Pavilion dv4 Notebook PC"),
858 .driver_data = "20090105", /* F.30 */
863 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
864 DMI_MATCH(DMI_PRODUCT_NAME,
865 "HP Pavilion dv5 Notebook PC"),
867 .driver_data = "20090506", /* F.16 */
872 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
873 DMI_MATCH(DMI_PRODUCT_NAME,
874 "HP Pavilion dv6 Notebook PC"),
876 .driver_data = "20090423", /* F.21 */
881 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
882 DMI_MATCH(DMI_PRODUCT_NAME,
883 "HP HDX18 Notebook PC"),
885 .driver_data = "20090430", /* F.23 */
888 * Acer eMachines G725 has the same problem. BIOS
889 * V1.03 is known to be broken. V3.04 is known to
890 * work. Inbetween, there are V1.06, V2.06 and V3.03
891 * that we don't have much idea about. For now,
892 * blacklist anything older than V3.04.
894 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
899 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
900 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
902 .driver_data = "20091216", /* V3.04 */
904 { } /* terminate list */
906 const struct dmi_system_id *dmi = dmi_first_match(sysids);
907 int year, month, date;
910 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
913 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
914 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
916 return strcmp(buf, dmi->driver_data) < 0;
919 static bool ahci_broken_online(struct pci_dev *pdev)
921 #define ENCODE_BUSDEVFN(bus, slot, func) \
922 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
923 static const struct dmi_system_id sysids[] = {
925 * There are several gigabyte boards which use
926 * SIMG5723s configured as hardware RAID. Certain
927 * 5723 firmware revisions shipped there keep the link
928 * online but fail to answer properly to SRST or
929 * IDENTIFY when no device is attached downstream
930 * causing libata to retry quite a few times leading
931 * to excessive detection delay.
933 * As these firmwares respond to the second reset try
934 * with invalid device signature, considering unknown
935 * sig as offline works around the problem acceptably.
940 DMI_MATCH(DMI_BOARD_VENDOR,
941 "Gigabyte Technology Co., Ltd."),
942 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
944 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
949 DMI_MATCH(DMI_BOARD_VENDOR,
950 "Gigabyte Technology Co., Ltd."),
951 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
953 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
955 { } /* terminate list */
957 #undef ENCODE_BUSDEVFN
958 const struct dmi_system_id *dmi = dmi_first_match(sysids);
964 val = (unsigned long)dmi->driver_data;
966 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
969 #ifdef CONFIG_ATA_ACPI
970 static void ahci_gtf_filter_workaround(struct ata_host *host)
972 static const struct dmi_system_id sysids[] = {
974 * Aspire 3810T issues a bunch of SATA enable commands
975 * via _GTF including an invalid one and one which is
976 * rejected by the device. Among the successful ones
977 * is FPDMA non-zero offset enable which when enabled
978 * only on the drive side leads to NCQ command
979 * failures. Filter it out.
982 .ident = "Aspire 3810T",
984 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
985 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
987 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
991 const struct dmi_system_id *dmi = dmi_first_match(sysids);
998 filter = (unsigned long)dmi->driver_data;
999 dev_printk(KERN_INFO, host->dev,
1000 "applying extra ACPI _GTF filter 0x%x for %s\n",
1001 filter, dmi->ident);
1003 for (i = 0; i < host->n_ports; i++) {
1004 struct ata_port *ap = host->ports[i];
1005 struct ata_link *link;
1006 struct ata_device *dev;
1008 ata_for_each_link(link, ap, EDGE)
1009 ata_for_each_dev(dev, link, ALL)
1010 dev->gtf_filter |= filter;
1014 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1018 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1020 static int printed_version;
1021 unsigned int board_id = ent->driver_data;
1022 struct ata_port_info pi = ahci_port_info[board_id];
1023 const struct ata_port_info *ppi[] = { &pi, NULL };
1024 struct device *dev = &pdev->dev;
1025 struct ahci_host_priv *hpriv;
1026 struct ata_host *host;
1031 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1033 if (!printed_version++)
1034 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1036 /* The AHCI driver can only drive the SATA ports, the PATA driver
1037 can drive them all so if both drivers are selected make sure
1038 AHCI stays out of the way */
1039 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1042 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1043 * At the moment, we can only use the AHCI mode. Let the users know
1044 * that for SAS drives they're out of luck.
1046 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1047 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1048 "can only drive SATA devices with this driver\n");
1050 /* acquire resources */
1051 rc = pcim_enable_device(pdev);
1055 /* AHCI controllers often implement SFF compatible interface.
1056 * Grab all PCI BARs just in case.
1058 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1060 pcim_pin_device(pdev);
1064 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1065 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1068 /* ICH6s share the same PCI ID for both piix and ahci
1069 * modes. Enabling ahci mode while MAP indicates
1070 * combined mode is a bad idea. Yield to ata_piix.
1072 pci_read_config_byte(pdev, ICH_MAP, &map);
1074 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1075 "combined mode, can't enable AHCI mode\n");
1080 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1083 hpriv->flags |= (unsigned long)pi.private_data;
1085 /* MCP65 revision A1 and A2 can't do MSI */
1086 if (board_id == board_ahci_mcp65 &&
1087 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1088 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1090 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1091 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1092 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1094 /* only some SB600s can do 64bit DMA */
1095 if (ahci_sb600_enable_64bit(pdev))
1096 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1098 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1101 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1103 /* save initial config */
1104 ahci_pci_save_initial_config(pdev, hpriv);
1107 if (hpriv->cap & HOST_CAP_NCQ) {
1108 pi.flags |= ATA_FLAG_NCQ;
1109 /* Auto-activate optimization is supposed to be supported on
1110 all AHCI controllers indicating NCQ support, but it seems
1111 to be broken at least on some NVIDIA MCP79 chipsets.
1112 Until we get info on which NVIDIA chipsets don't have this
1113 issue, if any, disable AA on all NVIDIA AHCIs. */
1114 if (pdev->vendor != PCI_VENDOR_ID_NVIDIA)
1115 pi.flags |= ATA_FLAG_FPDMA_AA;
1118 if (hpriv->cap & HOST_CAP_PMP)
1119 pi.flags |= ATA_FLAG_PMP;
1121 ahci_set_em_messages(hpriv, &pi);
1123 if (ahci_broken_system_poweroff(pdev)) {
1124 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1125 dev_info(&pdev->dev,
1126 "quirky BIOS, skipping spindown on poweroff\n");
1129 if (ahci_broken_suspend(pdev)) {
1130 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1131 dev_printk(KERN_WARNING, &pdev->dev,
1132 "BIOS update required for suspend/resume\n");
1135 if (ahci_broken_online(pdev)) {
1136 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1137 dev_info(&pdev->dev,
1138 "online status unreliable, applying workaround\n");
1141 /* CAP.NP sometimes indicate the index of the last enabled
1142 * port, at other times, that of the last possible port, so
1143 * determining the maximum port number requires looking at
1144 * both CAP.NP and port_map.
1146 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1148 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1151 host->private_data = hpriv;
1153 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1154 host->flags |= ATA_HOST_PARALLEL_SCAN;
1156 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1158 if (pi.flags & ATA_FLAG_EM)
1159 ahci_reset_em(host);
1161 for (i = 0; i < host->n_ports; i++) {
1162 struct ata_port *ap = host->ports[i];
1164 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1165 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1166 0x100 + ap->port_no * 0x80, "port");
1168 /* set initial link pm policy */
1169 ap->pm_policy = NOT_AVAILABLE;
1171 /* set enclosure management message type */
1172 if (ap->flags & ATA_FLAG_EM)
1173 ap->em_message_type = ahci_em_messages;
1176 /* disabled/not-implemented port */
1177 if (!(hpriv->port_map & (1 << i)))
1178 ap->ops = &ata_dummy_port_ops;
1181 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1182 ahci_p5wdh_workaround(host);
1184 /* apply gtf filter quirk */
1185 ahci_gtf_filter_workaround(host);
1187 /* initialize adapter */
1188 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1192 rc = ahci_pci_reset_controller(host);
1196 ahci_pci_init_controller(host);
1197 ahci_pci_print_info(host);
1199 pci_set_master(pdev);
1200 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1204 static int __init ahci_init(void)
1206 return pci_register_driver(&ahci_pci_driver);
1209 static void __exit ahci_exit(void)
1211 pci_unregister_driver(&ahci_pci_driver);
1215 MODULE_AUTHOR("Jeff Garzik");
1216 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1217 MODULE_LICENSE("GPL");
1218 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1219 MODULE_VERSION(DRV_VERSION);
1221 module_init(ahci_init);
1222 module_exit(ahci_exit);