2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
52 /* Enclosure Management Control */
53 #define EM_CTRL_MSG_TYPE 0x000f0000
55 /* Enclosure Management LED Message Type */
56 #define EM_MSG_LED_HBA_PORT 0x0000000f
57 #define EM_MSG_LED_PMP_SLOT 0x0000ff00
58 #define EM_MSG_LED_VALUE 0xffff0000
59 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60 #define EM_MSG_LED_VALUE_OFF 0xfff80000
61 #define EM_MSG_LED_VALUE_ON 0x00010000
63 static int ahci_skip_host_reset;
64 static int ahci_ignore_sss;
66 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
69 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
72 static int ahci_enable_alpm(struct ata_port *ap,
74 static void ahci_disable_alpm(struct ata_port *ap);
75 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
78 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
84 AHCI_MAX_SG = 168, /* hardware max is 64K */
85 AHCI_DMA_BOUNDARY = 0xffffffff,
88 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
90 AHCI_CMD_TBL_CDB = 0x40,
91 AHCI_CMD_TBL_HDR_SZ = 0x80,
92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
96 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
98 (AHCI_RX_FIS_SZ * 16),
99 AHCI_IRQ_ON_SG = (1 << 31),
100 AHCI_CMD_ATAPI = (1 << 5),
101 AHCI_CMD_WRITE = (1 << 6),
102 AHCI_CMD_PREFETCH = (1 << 7),
103 AHCI_CMD_RESET = (1 << 8),
104 AHCI_CMD_CLR_BUSY = (1 << 10),
106 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
107 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
108 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
111 board_ahci_vt8251 = 1,
112 board_ahci_ign_iferr = 2,
113 board_ahci_sb600 = 3,
115 board_ahci_sb700 = 5, /* for SB700 and SB800 */
116 board_ahci_mcp65 = 6,
117 board_ahci_nopmp = 7,
118 board_ahci_yesncq = 8,
119 board_ahci_nosntf = 9,
121 /* global controller registers */
122 HOST_CAP = 0x00, /* host capabilities */
123 HOST_CTL = 0x04, /* global host control */
124 HOST_IRQ_STAT = 0x08, /* interrupt status */
125 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
126 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
127 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
128 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
129 HOST_CAP2 = 0x24, /* host capabilities, extended */
132 HOST_RESET = (1 << 0), /* reset controller; self-clear */
133 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
134 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
137 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
138 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
139 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
140 HOST_CAP_PART = (1 << 13), /* Partial state capable */
141 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
142 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
143 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
144 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
145 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
146 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
147 HOST_CAP_LED = (1 << 25), /* Supports activity LED */
148 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
149 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
150 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
151 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
152 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
153 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
156 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
157 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
158 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
160 /* registers for each SATA port */
161 PORT_LST_ADDR = 0x00, /* command list DMA addr */
162 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
163 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
164 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
165 PORT_IRQ_STAT = 0x10, /* interrupt status */
166 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
167 PORT_CMD = 0x18, /* port command */
168 PORT_TFDATA = 0x20, /* taskfile data */
169 PORT_SIG = 0x24, /* device TF signature */
170 PORT_CMD_ISSUE = 0x38, /* command issue */
171 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
172 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
173 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
174 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
175 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
176 PORT_FBS = 0x40, /* FIS-based Switching */
178 /* PORT_IRQ_{STAT,MASK} bits */
179 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
180 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
181 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
182 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
183 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
184 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
185 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
186 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
188 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
189 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
190 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
191 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
192 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
193 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
194 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
195 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
196 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
198 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
204 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
206 PORT_IRQ_HBUS_DATA_ERR,
207 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
208 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
209 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
212 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
213 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
214 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
215 PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
216 PORT_CMD_PMP = (1 << 17), /* PMP attached */
217 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
218 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
219 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
220 PORT_CMD_CLO = (1 << 3), /* Command list override */
221 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
222 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
223 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
225 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
226 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
227 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
228 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
230 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
231 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
232 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
233 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
234 PORT_FBS_SDE = (1 << 2), /* FBS single device error */
235 PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
236 PORT_FBS_EN = (1 << 0), /* Enable FBS */
238 /* hpriv->flags bits */
239 AHCI_HFLAG_NO_NCQ = (1 << 0),
240 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
241 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
242 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
243 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
244 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
245 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
246 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
247 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
248 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
249 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
250 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
252 AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
256 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
257 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
258 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
261 ICH_MAP = 0x90, /* ICH MAP register */
268 EM_CTL_RST = (1 << 9), /* Reset */
269 EM_CTL_TM = (1 << 8), /* Transmit Message */
270 EM_CTL_ALHD = (1 << 26), /* Activity LED */
273 struct ahci_cmd_hdr {
288 struct ahci_em_priv {
289 enum sw_activity blink_policy;
290 struct timer_list timer;
291 unsigned long saved_activity;
292 unsigned long activity;
293 unsigned long led_state;
296 struct ahci_host_priv {
297 unsigned int flags; /* AHCI_HFLAG_* */
298 u32 cap; /* cap to use */
299 u32 cap2; /* cap2 to use */
300 u32 port_map; /* port map to use */
301 u32 saved_cap; /* saved initial cap */
302 u32 saved_cap2; /* saved initial cap2 */
303 u32 saved_port_map; /* saved initial port_map */
304 u32 em_loc; /* enclosure management location */
307 struct ahci_port_priv {
308 struct ata_link *active_link;
309 struct ahci_cmd_hdr *cmd_slot;
310 dma_addr_t cmd_slot_dma;
312 dma_addr_t cmd_tbl_dma;
314 dma_addr_t rx_fis_dma;
315 /* for NCQ spurious interrupt analysis */
316 unsigned int ncq_saw_d2h:1;
317 unsigned int ncq_saw_dmas:1;
318 unsigned int ncq_saw_sdb:1;
319 u32 intr_mask; /* interrupts to enable */
320 bool fbs_supported; /* set iff FBS is supported */
321 bool fbs_enabled; /* set iff FBS is enabled */
322 int fbs_last_dev; /* save FBS.DEV of last FIS */
323 /* enclosure management info per PM slot */
324 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
327 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
328 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
329 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
330 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
331 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
332 static int ahci_port_start(struct ata_port *ap);
333 static void ahci_port_stop(struct ata_port *ap);
334 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
335 static void ahci_qc_prep(struct ata_queued_cmd *qc);
336 static void ahci_freeze(struct ata_port *ap);
337 static void ahci_thaw(struct ata_port *ap);
338 static void ahci_enable_fbs(struct ata_port *ap);
339 static void ahci_disable_fbs(struct ata_port *ap);
340 static void ahci_pmp_attach(struct ata_port *ap);
341 static void ahci_pmp_detach(struct ata_port *ap);
342 static int ahci_softreset(struct ata_link *link, unsigned int *class,
343 unsigned long deadline);
344 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
345 unsigned long deadline);
346 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
347 unsigned long deadline);
348 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
349 unsigned long deadline);
350 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
351 unsigned long deadline);
352 static void ahci_postreset(struct ata_link *link, unsigned int *class);
353 static void ahci_error_handler(struct ata_port *ap);
354 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
355 static int ahci_port_resume(struct ata_port *ap);
356 static void ahci_dev_config(struct ata_device *dev);
357 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
360 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
361 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
362 static int ahci_pci_device_resume(struct pci_dev *pdev);
364 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
365 static ssize_t ahci_activity_store(struct ata_device *dev,
366 enum sw_activity val);
367 static void ahci_init_sw_activity(struct ata_link *link);
369 static ssize_t ahci_show_host_caps(struct device *dev,
370 struct device_attribute *attr, char *buf);
371 static ssize_t ahci_show_host_cap2(struct device *dev,
372 struct device_attribute *attr, char *buf);
373 static ssize_t ahci_show_host_version(struct device *dev,
374 struct device_attribute *attr, char *buf);
375 static ssize_t ahci_show_port_cmd(struct device *dev,
376 struct device_attribute *attr, char *buf);
378 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
379 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
380 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
381 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
383 static struct device_attribute *ahci_shost_attrs[] = {
384 &dev_attr_link_power_management_policy,
385 &dev_attr_em_message_type,
386 &dev_attr_em_message,
387 &dev_attr_ahci_host_caps,
388 &dev_attr_ahci_host_cap2,
389 &dev_attr_ahci_host_version,
390 &dev_attr_ahci_port_cmd,
394 static struct device_attribute *ahci_sdev_attrs[] = {
395 &dev_attr_sw_activity,
396 &dev_attr_unload_heads,
400 static struct scsi_host_template ahci_sht = {
401 ATA_NCQ_SHT(DRV_NAME),
402 .can_queue = AHCI_MAX_CMDS - 1,
403 .sg_tablesize = AHCI_MAX_SG,
404 .dma_boundary = AHCI_DMA_BOUNDARY,
405 .shost_attrs = ahci_shost_attrs,
406 .sdev_attrs = ahci_sdev_attrs,
409 static struct ata_port_operations ahci_ops = {
410 .inherits = &sata_pmp_port_ops,
412 .qc_defer = ahci_pmp_qc_defer,
413 .qc_prep = ahci_qc_prep,
414 .qc_issue = ahci_qc_issue,
415 .qc_fill_rtf = ahci_qc_fill_rtf,
417 .freeze = ahci_freeze,
419 .softreset = ahci_softreset,
420 .hardreset = ahci_hardreset,
421 .postreset = ahci_postreset,
422 .pmp_softreset = ahci_softreset,
423 .error_handler = ahci_error_handler,
424 .post_internal_cmd = ahci_post_internal_cmd,
425 .dev_config = ahci_dev_config,
427 .scr_read = ahci_scr_read,
428 .scr_write = ahci_scr_write,
429 .pmp_attach = ahci_pmp_attach,
430 .pmp_detach = ahci_pmp_detach,
432 .enable_pm = ahci_enable_alpm,
433 .disable_pm = ahci_disable_alpm,
434 .em_show = ahci_led_show,
435 .em_store = ahci_led_store,
436 .sw_activity_show = ahci_activity_show,
437 .sw_activity_store = ahci_activity_store,
439 .port_suspend = ahci_port_suspend,
440 .port_resume = ahci_port_resume,
442 .port_start = ahci_port_start,
443 .port_stop = ahci_port_stop,
446 static struct ata_port_operations ahci_vt8251_ops = {
447 .inherits = &ahci_ops,
448 .hardreset = ahci_vt8251_hardreset,
451 static struct ata_port_operations ahci_p5wdh_ops = {
452 .inherits = &ahci_ops,
453 .hardreset = ahci_p5wdh_hardreset,
456 static struct ata_port_operations ahci_sb600_ops = {
457 .inherits = &ahci_ops,
458 .softreset = ahci_sb600_softreset,
459 .pmp_softreset = ahci_sb600_softreset,
462 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
464 static const struct ata_port_info ahci_port_info[] = {
467 .flags = AHCI_FLAG_COMMON,
468 .pio_mask = ATA_PIO4,
469 .udma_mask = ATA_UDMA6,
470 .port_ops = &ahci_ops,
472 [board_ahci_vt8251] =
474 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
475 .flags = AHCI_FLAG_COMMON,
476 .pio_mask = ATA_PIO4,
477 .udma_mask = ATA_UDMA6,
478 .port_ops = &ahci_vt8251_ops,
480 [board_ahci_ign_iferr] =
482 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
483 .flags = AHCI_FLAG_COMMON,
484 .pio_mask = ATA_PIO4,
485 .udma_mask = ATA_UDMA6,
486 .port_ops = &ahci_ops,
490 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
491 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
492 AHCI_HFLAG_32BIT_ONLY),
493 .flags = AHCI_FLAG_COMMON,
494 .pio_mask = ATA_PIO4,
495 .udma_mask = ATA_UDMA6,
496 .port_ops = &ahci_sb600_ops,
500 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
501 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
502 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
503 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
504 .pio_mask = ATA_PIO4,
505 .udma_mask = ATA_UDMA6,
506 .port_ops = &ahci_ops,
508 [board_ahci_sb700] = /* for SB700 and SB800 */
510 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
511 .flags = AHCI_FLAG_COMMON,
512 .pio_mask = ATA_PIO4,
513 .udma_mask = ATA_UDMA6,
514 .port_ops = &ahci_sb600_ops,
518 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
519 .flags = AHCI_FLAG_COMMON,
520 .pio_mask = ATA_PIO4,
521 .udma_mask = ATA_UDMA6,
522 .port_ops = &ahci_ops,
526 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
527 .flags = AHCI_FLAG_COMMON,
528 .pio_mask = ATA_PIO4,
529 .udma_mask = ATA_UDMA6,
530 .port_ops = &ahci_ops,
532 [board_ahci_yesncq] =
534 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
535 .flags = AHCI_FLAG_COMMON,
536 .pio_mask = ATA_PIO4,
537 .udma_mask = ATA_UDMA6,
538 .port_ops = &ahci_ops,
540 [board_ahci_nosntf] =
542 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
543 .flags = AHCI_FLAG_COMMON,
544 .pio_mask = ATA_PIO4,
545 .udma_mask = ATA_UDMA6,
546 .port_ops = &ahci_ops,
550 static const struct pci_device_id ahci_pci_tbl[] = {
552 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
553 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
554 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
555 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
556 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
557 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
558 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
559 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
560 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
561 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
562 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
563 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
564 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
565 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
566 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
567 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
568 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
569 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
570 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
571 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
572 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
573 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
574 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
575 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
576 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
577 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
578 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
579 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
580 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
581 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
582 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
583 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
584 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
585 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
586 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
587 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
588 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
589 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
590 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
591 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
592 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
593 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
594 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
595 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
596 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
597 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
599 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
600 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
601 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
604 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
605 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
606 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
607 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
608 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
609 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
610 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
613 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
614 /* AMD is using RAID class only for ahci controllers */
615 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
616 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
619 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
620 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
623 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
624 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
625 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
626 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
627 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
628 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
629 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
630 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
631 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
632 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
633 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
634 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
635 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
636 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
637 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
638 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
639 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
640 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
641 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
642 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
643 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq }, /* Linux ID */
644 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_yesncq }, /* Linux ID */
645 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_yesncq }, /* Linux ID */
646 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_yesncq }, /* Linux ID */
647 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_yesncq }, /* Linux ID */
648 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_yesncq }, /* Linux ID */
649 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_yesncq }, /* Linux ID */
650 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_yesncq }, /* Linux ID */
651 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_yesncq }, /* Linux ID */
652 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_yesncq }, /* Linux ID */
653 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_yesncq }, /* Linux ID */
654 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_yesncq }, /* Linux ID */
655 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_yesncq }, /* Linux ID */
656 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_yesncq }, /* Linux ID */
657 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_yesncq }, /* Linux ID */
658 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_yesncq }, /* Linux ID */
659 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
660 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
661 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
662 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
663 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
664 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
665 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
666 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
667 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
668 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
669 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
670 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
671 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
672 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
673 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
674 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
675 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
676 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
677 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
678 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
679 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
680 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
681 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
682 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
683 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
684 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
685 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
686 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
687 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
688 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
689 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
690 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
691 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
692 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
693 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
694 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
695 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
696 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
697 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
698 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
699 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
700 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
701 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
702 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
703 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
704 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
705 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
706 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
709 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
710 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
711 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
714 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
715 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
718 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
720 /* Generic, PCI class code for AHCI */
721 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
722 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
724 { } /* terminate list */
728 static struct pci_driver ahci_pci_driver = {
730 .id_table = ahci_pci_tbl,
731 .probe = ahci_init_one,
732 .remove = ata_pci_remove_one,
734 .suspend = ahci_pci_device_suspend,
735 .resume = ahci_pci_device_resume,
739 static int ahci_em_messages = 1;
740 module_param(ahci_em_messages, int, 0444);
741 /* add other LED protocol types when they become supported */
742 MODULE_PARM_DESC(ahci_em_messages,
743 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
745 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
746 static int marvell_enable;
748 static int marvell_enable = 1;
750 module_param(marvell_enable, int, 0644);
751 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
754 static inline int ahci_nr_ports(u32 cap)
756 return (cap & 0x1f) + 1;
759 static inline void __iomem *__ahci_port_base(struct ata_host *host,
760 unsigned int port_no)
762 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
764 return mmio + 0x100 + (port_no * 0x80);
767 static inline void __iomem *ahci_port_base(struct ata_port *ap)
769 return __ahci_port_base(ap->host, ap->port_no);
772 static void ahci_enable_ahci(void __iomem *mmio)
777 /* turn on AHCI_EN */
778 tmp = readl(mmio + HOST_CTL);
779 if (tmp & HOST_AHCI_EN)
782 /* Some controllers need AHCI_EN to be written multiple times.
783 * Try a few times before giving up.
785 for (i = 0; i < 5; i++) {
787 writel(tmp, mmio + HOST_CTL);
788 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
789 if (tmp & HOST_AHCI_EN)
797 static ssize_t ahci_show_host_caps(struct device *dev,
798 struct device_attribute *attr, char *buf)
800 struct Scsi_Host *shost = class_to_shost(dev);
801 struct ata_port *ap = ata_shost_to_port(shost);
802 struct ahci_host_priv *hpriv = ap->host->private_data;
804 return sprintf(buf, "%x\n", hpriv->cap);
807 static ssize_t ahci_show_host_cap2(struct device *dev,
808 struct device_attribute *attr, char *buf)
810 struct Scsi_Host *shost = class_to_shost(dev);
811 struct ata_port *ap = ata_shost_to_port(shost);
812 struct ahci_host_priv *hpriv = ap->host->private_data;
814 return sprintf(buf, "%x\n", hpriv->cap2);
817 static ssize_t ahci_show_host_version(struct device *dev,
818 struct device_attribute *attr, char *buf)
820 struct Scsi_Host *shost = class_to_shost(dev);
821 struct ata_port *ap = ata_shost_to_port(shost);
822 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
824 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
827 static ssize_t ahci_show_port_cmd(struct device *dev,
828 struct device_attribute *attr, char *buf)
830 struct Scsi_Host *shost = class_to_shost(dev);
831 struct ata_port *ap = ata_shost_to_port(shost);
832 void __iomem *port_mmio = ahci_port_base(ap);
834 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
838 * ahci_save_initial_config - Save and fixup initial config values
839 * @pdev: target PCI device
840 * @hpriv: host private area to store config values
842 * Some registers containing configuration info might be setup by
843 * BIOS and might be cleared on reset. This function saves the
844 * initial values of those registers into @hpriv such that they
845 * can be restored after controller reset.
847 * If inconsistent, config values are fixed up by this function.
852 static void ahci_save_initial_config(struct pci_dev *pdev,
853 struct ahci_host_priv *hpriv)
855 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
856 u32 cap, cap2, vers, port_map;
860 /* make sure AHCI mode is enabled before accessing CAP */
861 ahci_enable_ahci(mmio);
863 /* Values prefixed with saved_ are written back to host after
864 * reset. Values without are used for driver operation.
866 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
867 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
869 /* CAP2 register is only defined for AHCI 1.2 and later */
870 vers = readl(mmio + HOST_VERSION);
871 if ((vers >> 16) > 1 ||
872 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
873 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
875 hpriv->saved_cap2 = cap2 = 0;
877 /* some chips have errata preventing 64bit use */
878 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
879 dev_printk(KERN_INFO, &pdev->dev,
880 "controller can't do 64bit DMA, forcing 32bit\n");
884 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
885 dev_printk(KERN_INFO, &pdev->dev,
886 "controller can't do NCQ, turning off CAP_NCQ\n");
887 cap &= ~HOST_CAP_NCQ;
890 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
891 dev_printk(KERN_INFO, &pdev->dev,
892 "controller can do NCQ, turning on CAP_NCQ\n");
896 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
897 dev_printk(KERN_INFO, &pdev->dev,
898 "controller can't do PMP, turning off CAP_PMP\n");
899 cap &= ~HOST_CAP_PMP;
902 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
903 dev_printk(KERN_INFO, &pdev->dev,
904 "controller can't do SNTF, turning off CAP_SNTF\n");
905 cap &= ~HOST_CAP_SNTF;
908 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
910 dev_printk(KERN_INFO, &pdev->dev,
911 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
917 * Temporary Marvell 6145 hack: PATA port presence
918 * is asserted through the standard AHCI port
919 * presence register, as bit 4 (counting from 0)
921 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
922 if (pdev->device == 0x6121)
926 dev_printk(KERN_ERR, &pdev->dev,
927 "MV_AHCI HACK: port_map %x -> %x\n",
930 dev_printk(KERN_ERR, &pdev->dev,
931 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
936 /* cross check port_map and cap.n_ports */
940 for (i = 0; i < AHCI_MAX_PORTS; i++)
941 if (port_map & (1 << i))
944 /* If PI has more ports than n_ports, whine, clear
945 * port_map and let it be generated from n_ports.
947 if (map_ports > ahci_nr_ports(cap)) {
948 dev_printk(KERN_WARNING, &pdev->dev,
949 "implemented port map (0x%x) contains more "
950 "ports than nr_ports (%u), using nr_ports\n",
951 port_map, ahci_nr_ports(cap));
956 /* fabricate port_map from cap.nr_ports */
958 port_map = (1 << ahci_nr_ports(cap)) - 1;
959 dev_printk(KERN_WARNING, &pdev->dev,
960 "forcing PORTS_IMPL to 0x%x\n", port_map);
962 /* write the fixed up value to the PI register */
963 hpriv->saved_port_map = port_map;
966 /* record values to use during operation */
969 hpriv->port_map = port_map;
973 * ahci_restore_initial_config - Restore initial config
974 * @host: target ATA host
976 * Restore initial config stored by ahci_save_initial_config().
981 static void ahci_restore_initial_config(struct ata_host *host)
983 struct ahci_host_priv *hpriv = host->private_data;
984 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
986 writel(hpriv->saved_cap, mmio + HOST_CAP);
987 if (hpriv->saved_cap2)
988 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
989 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
990 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
993 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
995 static const int offset[] = {
996 [SCR_STATUS] = PORT_SCR_STAT,
997 [SCR_CONTROL] = PORT_SCR_CTL,
998 [SCR_ERROR] = PORT_SCR_ERR,
999 [SCR_ACTIVE] = PORT_SCR_ACT,
1000 [SCR_NOTIFICATION] = PORT_SCR_NTF,
1002 struct ahci_host_priv *hpriv = ap->host->private_data;
1004 if (sc_reg < ARRAY_SIZE(offset) &&
1005 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
1006 return offset[sc_reg];
1010 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
1012 void __iomem *port_mmio = ahci_port_base(link->ap);
1013 int offset = ahci_scr_offset(link->ap, sc_reg);
1016 *val = readl(port_mmio + offset);
1022 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
1024 void __iomem *port_mmio = ahci_port_base(link->ap);
1025 int offset = ahci_scr_offset(link->ap, sc_reg);
1028 writel(val, port_mmio + offset);
1034 static void ahci_start_engine(struct ata_port *ap)
1036 void __iomem *port_mmio = ahci_port_base(ap);
1040 tmp = readl(port_mmio + PORT_CMD);
1041 tmp |= PORT_CMD_START;
1042 writel(tmp, port_mmio + PORT_CMD);
1043 readl(port_mmio + PORT_CMD); /* flush */
1046 static int ahci_stop_engine(struct ata_port *ap)
1048 void __iomem *port_mmio = ahci_port_base(ap);
1051 tmp = readl(port_mmio + PORT_CMD);
1053 /* check if the HBA is idle */
1054 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
1057 /* setting HBA to idle */
1058 tmp &= ~PORT_CMD_START;
1059 writel(tmp, port_mmio + PORT_CMD);
1061 /* wait for engine to stop. This could be as long as 500 msec */
1062 tmp = ata_wait_register(port_mmio + PORT_CMD,
1063 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
1064 if (tmp & PORT_CMD_LIST_ON)
1070 static void ahci_start_fis_rx(struct ata_port *ap)
1072 void __iomem *port_mmio = ahci_port_base(ap);
1073 struct ahci_host_priv *hpriv = ap->host->private_data;
1074 struct ahci_port_priv *pp = ap->private_data;
1077 /* set FIS registers */
1078 if (hpriv->cap & HOST_CAP_64)
1079 writel((pp->cmd_slot_dma >> 16) >> 16,
1080 port_mmio + PORT_LST_ADDR_HI);
1081 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
1083 if (hpriv->cap & HOST_CAP_64)
1084 writel((pp->rx_fis_dma >> 16) >> 16,
1085 port_mmio + PORT_FIS_ADDR_HI);
1086 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
1088 /* enable FIS reception */
1089 tmp = readl(port_mmio + PORT_CMD);
1090 tmp |= PORT_CMD_FIS_RX;
1091 writel(tmp, port_mmio + PORT_CMD);
1094 readl(port_mmio + PORT_CMD);
1097 static int ahci_stop_fis_rx(struct ata_port *ap)
1099 void __iomem *port_mmio = ahci_port_base(ap);
1102 /* disable FIS reception */
1103 tmp = readl(port_mmio + PORT_CMD);
1104 tmp &= ~PORT_CMD_FIS_RX;
1105 writel(tmp, port_mmio + PORT_CMD);
1107 /* wait for completion, spec says 500ms, give it 1000 */
1108 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
1109 PORT_CMD_FIS_ON, 10, 1000);
1110 if (tmp & PORT_CMD_FIS_ON)
1116 static void ahci_power_up(struct ata_port *ap)
1118 struct ahci_host_priv *hpriv = ap->host->private_data;
1119 void __iomem *port_mmio = ahci_port_base(ap);
1122 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1124 /* spin up device */
1125 if (hpriv->cap & HOST_CAP_SSS) {
1126 cmd |= PORT_CMD_SPIN_UP;
1127 writel(cmd, port_mmio + PORT_CMD);
1131 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
1134 static void ahci_disable_alpm(struct ata_port *ap)
1136 struct ahci_host_priv *hpriv = ap->host->private_data;
1137 void __iomem *port_mmio = ahci_port_base(ap);
1139 struct ahci_port_priv *pp = ap->private_data;
1141 /* IPM bits should be disabled by libata-core */
1142 /* get the existing command bits */
1143 cmd = readl(port_mmio + PORT_CMD);
1145 /* disable ALPM and ASP */
1146 cmd &= ~PORT_CMD_ASP;
1147 cmd &= ~PORT_CMD_ALPE;
1149 /* force the interface back to active */
1150 cmd |= PORT_CMD_ICC_ACTIVE;
1152 /* write out new cmd value */
1153 writel(cmd, port_mmio + PORT_CMD);
1154 cmd = readl(port_mmio + PORT_CMD);
1156 /* wait 10ms to be sure we've come out of any low power state */
1159 /* clear out any PhyRdy stuff from interrupt status */
1160 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1162 /* go ahead and clean out PhyRdy Change from Serror too */
1163 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1166 * Clear flag to indicate that we should ignore all PhyRdy
1169 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1172 * Enable interrupts on Phy Ready.
1174 pp->intr_mask |= PORT_IRQ_PHYRDY;
1175 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1178 * don't change the link pm policy - we can be called
1179 * just to turn of link pm temporarily
1183 static int ahci_enable_alpm(struct ata_port *ap,
1184 enum link_pm policy)
1186 struct ahci_host_priv *hpriv = ap->host->private_data;
1187 void __iomem *port_mmio = ahci_port_base(ap);
1189 struct ahci_port_priv *pp = ap->private_data;
1192 /* Make sure the host is capable of link power management */
1193 if (!(hpriv->cap & HOST_CAP_ALPM))
1197 case MAX_PERFORMANCE:
1200 * if we came here with NOT_AVAILABLE,
1201 * it just means this is the first time we
1202 * have tried to enable - default to max performance,
1203 * and let the user go to lower power modes on request.
1205 ahci_disable_alpm(ap);
1208 /* configure HBA to enter SLUMBER */
1212 /* configure HBA to enter PARTIAL */
1220 * Disable interrupts on Phy Ready. This keeps us from
1221 * getting woken up due to spurious phy ready interrupts
1222 * TBD - Hot plug should be done via polling now, is
1223 * that even supported?
1225 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1226 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1229 * Set a flag to indicate that we should ignore all PhyRdy
1230 * state changes since these can happen now whenever we
1233 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1235 /* get the existing command bits */
1236 cmd = readl(port_mmio + PORT_CMD);
1239 * Set ASP based on Policy
1244 * Setting this bit will instruct the HBA to aggressively
1245 * enter a lower power link state when it's appropriate and
1246 * based on the value set above for ASP
1248 cmd |= PORT_CMD_ALPE;
1250 /* write out new cmd value */
1251 writel(cmd, port_mmio + PORT_CMD);
1252 cmd = readl(port_mmio + PORT_CMD);
1254 /* IPM bits should be set by libata-core */
1259 static void ahci_power_down(struct ata_port *ap)
1261 struct ahci_host_priv *hpriv = ap->host->private_data;
1262 void __iomem *port_mmio = ahci_port_base(ap);
1265 if (!(hpriv->cap & HOST_CAP_SSS))
1268 /* put device into listen mode, first set PxSCTL.DET to 0 */
1269 scontrol = readl(port_mmio + PORT_SCR_CTL);
1271 writel(scontrol, port_mmio + PORT_SCR_CTL);
1273 /* then set PxCMD.SUD to 0 */
1274 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1275 cmd &= ~PORT_CMD_SPIN_UP;
1276 writel(cmd, port_mmio + PORT_CMD);
1280 static void ahci_start_port(struct ata_port *ap)
1282 struct ahci_port_priv *pp = ap->private_data;
1283 struct ata_link *link;
1284 struct ahci_em_priv *emp;
1288 /* enable FIS reception */
1289 ahci_start_fis_rx(ap);
1292 ahci_start_engine(ap);
1295 if (ap->flags & ATA_FLAG_EM) {
1296 ata_for_each_link(link, ap, EDGE) {
1297 emp = &pp->em_priv[link->pmp];
1299 /* EM Transmit bit maybe busy during init */
1300 for (i = 0; i < EM_MAX_RETRY; i++) {
1301 rc = ahci_transmit_led_message(ap,
1312 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1313 ata_for_each_link(link, ap, EDGE)
1314 ahci_init_sw_activity(link);
1318 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1323 rc = ahci_stop_engine(ap);
1325 *emsg = "failed to stop engine";
1329 /* disable FIS reception */
1330 rc = ahci_stop_fis_rx(ap);
1332 *emsg = "failed stop FIS RX";
1339 static int ahci_reset_controller(struct ata_host *host)
1341 struct pci_dev *pdev = to_pci_dev(host->dev);
1342 struct ahci_host_priv *hpriv = host->private_data;
1343 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1346 /* we must be in AHCI mode, before using anything
1347 * AHCI-specific, such as HOST_RESET.
1349 ahci_enable_ahci(mmio);
1351 /* global controller reset */
1352 if (!ahci_skip_host_reset) {
1353 tmp = readl(mmio + HOST_CTL);
1354 if ((tmp & HOST_RESET) == 0) {
1355 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1356 readl(mmio + HOST_CTL); /* flush */
1360 * to perform host reset, OS should set HOST_RESET
1361 * and poll until this bit is read to be "0".
1362 * reset must complete within 1 second, or
1363 * the hardware should be considered fried.
1365 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1366 HOST_RESET, 10, 1000);
1368 if (tmp & HOST_RESET) {
1369 dev_printk(KERN_ERR, host->dev,
1370 "controller reset failed (0x%x)\n", tmp);
1374 /* turn on AHCI mode */
1375 ahci_enable_ahci(mmio);
1377 /* Some registers might be cleared on reset. Restore
1380 ahci_restore_initial_config(host);
1382 dev_printk(KERN_INFO, host->dev,
1383 "skipping global host reset\n");
1385 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1389 pci_read_config_word(pdev, 0x92, &tmp16);
1390 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1391 tmp16 |= hpriv->port_map;
1392 pci_write_config_word(pdev, 0x92, tmp16);
1399 static void ahci_sw_activity(struct ata_link *link)
1401 struct ata_port *ap = link->ap;
1402 struct ahci_port_priv *pp = ap->private_data;
1403 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1405 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1409 if (!timer_pending(&emp->timer))
1410 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1413 static void ahci_sw_activity_blink(unsigned long arg)
1415 struct ata_link *link = (struct ata_link *)arg;
1416 struct ata_port *ap = link->ap;
1417 struct ahci_port_priv *pp = ap->private_data;
1418 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1419 unsigned long led_message = emp->led_state;
1420 u32 activity_led_state;
1421 unsigned long flags;
1423 led_message &= EM_MSG_LED_VALUE;
1424 led_message |= ap->port_no | (link->pmp << 8);
1426 /* check to see if we've had activity. If so,
1427 * toggle state of LED and reset timer. If not,
1428 * turn LED to desired idle state.
1430 spin_lock_irqsave(ap->lock, flags);
1431 if (emp->saved_activity != emp->activity) {
1432 emp->saved_activity = emp->activity;
1433 /* get the current LED state */
1434 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1436 if (activity_led_state)
1437 activity_led_state = 0;
1439 activity_led_state = 1;
1441 /* clear old state */
1442 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1445 led_message |= (activity_led_state << 16);
1446 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1448 /* switch to idle */
1449 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1450 if (emp->blink_policy == BLINK_OFF)
1451 led_message |= (1 << 16);
1453 spin_unlock_irqrestore(ap->lock, flags);
1454 ahci_transmit_led_message(ap, led_message, 4);
1457 static void ahci_init_sw_activity(struct ata_link *link)
1459 struct ata_port *ap = link->ap;
1460 struct ahci_port_priv *pp = ap->private_data;
1461 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1463 /* init activity stats, setup timer */
1464 emp->saved_activity = emp->activity = 0;
1465 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1467 /* check our blink policy and set flag for link if it's enabled */
1468 if (emp->blink_policy)
1469 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1472 static int ahci_reset_em(struct ata_host *host)
1474 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1477 em_ctl = readl(mmio + HOST_EM_CTL);
1478 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1481 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1485 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1488 struct ahci_host_priv *hpriv = ap->host->private_data;
1489 struct ahci_port_priv *pp = ap->private_data;
1490 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1492 u32 message[] = {0, 0};
1493 unsigned long flags;
1495 struct ahci_em_priv *emp;
1497 /* get the slot number from the message */
1498 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1499 if (pmp < EM_MAX_SLOTS)
1500 emp = &pp->em_priv[pmp];
1504 spin_lock_irqsave(ap->lock, flags);
1507 * if we are still busy transmitting a previous message,
1510 em_ctl = readl(mmio + HOST_EM_CTL);
1511 if (em_ctl & EM_CTL_TM) {
1512 spin_unlock_irqrestore(ap->lock, flags);
1517 * create message header - this is all zero except for
1518 * the message size, which is 4 bytes.
1520 message[0] |= (4 << 8);
1522 /* ignore 0:4 of byte zero, fill in port info yourself */
1523 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1525 /* write message to EM_LOC */
1526 writel(message[0], mmio + hpriv->em_loc);
1527 writel(message[1], mmio + hpriv->em_loc+4);
1529 /* save off new led state for port/slot */
1530 emp->led_state = state;
1533 * tell hardware to transmit the message
1535 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1537 spin_unlock_irqrestore(ap->lock, flags);
1541 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1543 struct ahci_port_priv *pp = ap->private_data;
1544 struct ata_link *link;
1545 struct ahci_em_priv *emp;
1548 ata_for_each_link(link, ap, EDGE) {
1549 emp = &pp->em_priv[link->pmp];
1550 rc += sprintf(buf, "%lx\n", emp->led_state);
1555 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1560 struct ahci_port_priv *pp = ap->private_data;
1561 struct ahci_em_priv *emp;
1563 state = simple_strtoul(buf, NULL, 0);
1565 /* get the slot number from the message */
1566 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1567 if (pmp < EM_MAX_SLOTS)
1568 emp = &pp->em_priv[pmp];
1572 /* mask off the activity bits if we are in sw_activity
1573 * mode, user should turn off sw_activity before setting
1574 * activity led through em_message
1576 if (emp->blink_policy)
1577 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1579 return ahci_transmit_led_message(ap, state, size);
1582 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1584 struct ata_link *link = dev->link;
1585 struct ata_port *ap = link->ap;
1586 struct ahci_port_priv *pp = ap->private_data;
1587 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1588 u32 port_led_state = emp->led_state;
1590 /* save the desired Activity LED behavior */
1593 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1595 /* set the LED to OFF */
1596 port_led_state &= EM_MSG_LED_VALUE_OFF;
1597 port_led_state |= (ap->port_no | (link->pmp << 8));
1598 ahci_transmit_led_message(ap, port_led_state, 4);
1600 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1601 if (val == BLINK_OFF) {
1602 /* set LED to ON for idle */
1603 port_led_state &= EM_MSG_LED_VALUE_OFF;
1604 port_led_state |= (ap->port_no | (link->pmp << 8));
1605 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1606 ahci_transmit_led_message(ap, port_led_state, 4);
1609 emp->blink_policy = val;
1613 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1615 struct ata_link *link = dev->link;
1616 struct ata_port *ap = link->ap;
1617 struct ahci_port_priv *pp = ap->private_data;
1618 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1620 /* display the saved value of activity behavior for this
1623 return sprintf(buf, "%d\n", emp->blink_policy);
1626 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1627 int port_no, void __iomem *mmio,
1628 void __iomem *port_mmio)
1630 const char *emsg = NULL;
1634 /* make sure port is not active */
1635 rc = ahci_deinit_port(ap, &emsg);
1637 dev_printk(KERN_WARNING, &pdev->dev,
1638 "%s (%d)\n", emsg, rc);
1641 tmp = readl(port_mmio + PORT_SCR_ERR);
1642 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1643 writel(tmp, port_mmio + PORT_SCR_ERR);
1645 /* clear port IRQ */
1646 tmp = readl(port_mmio + PORT_IRQ_STAT);
1647 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1649 writel(tmp, port_mmio + PORT_IRQ_STAT);
1651 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1654 static void ahci_init_controller(struct ata_host *host)
1656 struct ahci_host_priv *hpriv = host->private_data;
1657 struct pci_dev *pdev = to_pci_dev(host->dev);
1658 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1660 void __iomem *port_mmio;
1664 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1665 if (pdev->device == 0x6121)
1669 port_mmio = __ahci_port_base(host, mv);
1671 writel(0, port_mmio + PORT_IRQ_MASK);
1673 /* clear port IRQ */
1674 tmp = readl(port_mmio + PORT_IRQ_STAT);
1675 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1677 writel(tmp, port_mmio + PORT_IRQ_STAT);
1680 for (i = 0; i < host->n_ports; i++) {
1681 struct ata_port *ap = host->ports[i];
1683 port_mmio = ahci_port_base(ap);
1684 if (ata_port_is_dummy(ap))
1687 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1690 tmp = readl(mmio + HOST_CTL);
1691 VPRINTK("HOST_CTL 0x%x\n", tmp);
1692 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1693 tmp = readl(mmio + HOST_CTL);
1694 VPRINTK("HOST_CTL 0x%x\n", tmp);
1697 static void ahci_dev_config(struct ata_device *dev)
1699 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1701 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1702 dev->max_sectors = 255;
1703 ata_dev_printk(dev, KERN_INFO,
1704 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1708 static unsigned int ahci_dev_classify(struct ata_port *ap)
1710 void __iomem *port_mmio = ahci_port_base(ap);
1711 struct ata_taskfile tf;
1714 tmp = readl(port_mmio + PORT_SIG);
1715 tf.lbah = (tmp >> 24) & 0xff;
1716 tf.lbam = (tmp >> 16) & 0xff;
1717 tf.lbal = (tmp >> 8) & 0xff;
1718 tf.nsect = (tmp) & 0xff;
1720 return ata_dev_classify(&tf);
1723 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1726 dma_addr_t cmd_tbl_dma;
1728 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1730 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1731 pp->cmd_slot[tag].status = 0;
1732 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1733 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1736 static int ahci_kick_engine(struct ata_port *ap)
1738 void __iomem *port_mmio = ahci_port_base(ap);
1739 struct ahci_host_priv *hpriv = ap->host->private_data;
1740 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1745 rc = ahci_stop_engine(ap);
1750 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1752 busy = status & (ATA_BUSY | ATA_DRQ);
1753 if (!busy && !sata_pmp_attached(ap)) {
1758 if (!(hpriv->cap & HOST_CAP_CLO)) {
1764 tmp = readl(port_mmio + PORT_CMD);
1765 tmp |= PORT_CMD_CLO;
1766 writel(tmp, port_mmio + PORT_CMD);
1769 tmp = ata_wait_register(port_mmio + PORT_CMD,
1770 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1771 if (tmp & PORT_CMD_CLO)
1774 /* restart engine */
1776 ahci_start_engine(ap);
1780 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1781 struct ata_taskfile *tf, int is_cmd, u16 flags,
1782 unsigned long timeout_msec)
1784 const u32 cmd_fis_len = 5; /* five dwords */
1785 struct ahci_port_priv *pp = ap->private_data;
1786 void __iomem *port_mmio = ahci_port_base(ap);
1787 u8 *fis = pp->cmd_tbl;
1790 /* prep the command */
1791 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1792 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1795 writel(1, port_mmio + PORT_CMD_ISSUE);
1798 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1801 ahci_kick_engine(ap);
1805 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1810 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1811 int pmp, unsigned long deadline,
1812 int (*check_ready)(struct ata_link *link))
1814 struct ata_port *ap = link->ap;
1815 struct ahci_host_priv *hpriv = ap->host->private_data;
1816 const char *reason = NULL;
1817 unsigned long now, msecs;
1818 struct ata_taskfile tf;
1823 /* prepare for SRST (AHCI-1.1 10.4.1) */
1824 rc = ahci_kick_engine(ap);
1825 if (rc && rc != -EOPNOTSUPP)
1826 ata_link_printk(link, KERN_WARNING,
1827 "failed to reset engine (errno=%d)\n", rc);
1829 ata_tf_init(link->device, &tf);
1831 /* issue the first D2H Register FIS */
1834 if (time_after(now, deadline))
1835 msecs = jiffies_to_msecs(deadline - now);
1838 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1839 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1841 reason = "1st FIS failed";
1845 /* spec says at least 5us, but be generous and sleep for 1ms */
1848 /* issue the second D2H Register FIS */
1849 tf.ctl &= ~ATA_SRST;
1850 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1852 /* wait for link to become ready */
1853 rc = ata_wait_after_reset(link, deadline, check_ready);
1854 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1856 * Workaround for cases where link online status can't
1857 * be trusted. Treat device readiness timeout as link
1860 ata_link_printk(link, KERN_INFO,
1861 "device not ready, treating as offline\n");
1862 *class = ATA_DEV_NONE;
1864 /* link occupied, -ENODEV too is an error */
1865 reason = "device not ready";
1868 *class = ahci_dev_classify(ap);
1870 DPRINTK("EXIT, class=%u\n", *class);
1874 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1878 static int ahci_check_ready(struct ata_link *link)
1880 void __iomem *port_mmio = ahci_port_base(link->ap);
1881 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1883 return ata_check_ready(status);
1886 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1887 unsigned long deadline)
1889 int pmp = sata_srst_pmp(link);
1893 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1896 static int ahci_sb600_check_ready(struct ata_link *link)
1898 void __iomem *port_mmio = ahci_port_base(link->ap);
1899 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1900 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1903 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1904 * which can save timeout delay.
1906 if (irq_status & PORT_IRQ_BAD_PMP)
1909 return ata_check_ready(status);
1912 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1913 unsigned long deadline)
1915 struct ata_port *ap = link->ap;
1916 void __iomem *port_mmio = ahci_port_base(ap);
1917 int pmp = sata_srst_pmp(link);
1923 rc = ahci_do_softreset(link, class, pmp, deadline,
1924 ahci_sb600_check_ready);
1927 * Soft reset fails on some ATI chips with IPMS set when PMP
1928 * is enabled but SATA HDD/ODD is connected to SATA port,
1929 * do soft reset again to port 0.
1932 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1933 if (irq_sts & PORT_IRQ_BAD_PMP) {
1934 ata_link_printk(link, KERN_WARNING,
1935 "applying SB600 PMP SRST workaround "
1937 rc = ahci_do_softreset(link, class, 0, deadline,
1945 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1946 unsigned long deadline)
1948 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1949 struct ata_port *ap = link->ap;
1950 struct ahci_port_priv *pp = ap->private_data;
1951 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1952 struct ata_taskfile tf;
1958 ahci_stop_engine(ap);
1960 /* clear D2H reception area to properly wait for D2H FIS */
1961 ata_tf_init(link->device, &tf);
1963 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1965 rc = sata_link_hardreset(link, timing, deadline, &online,
1968 ahci_start_engine(ap);
1971 *class = ahci_dev_classify(ap);
1973 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1977 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1978 unsigned long deadline)
1980 struct ata_port *ap = link->ap;
1986 ahci_stop_engine(ap);
1988 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1989 deadline, &online, NULL);
1991 ahci_start_engine(ap);
1993 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1995 /* vt8251 doesn't clear BSY on signature FIS reception,
1996 * request follow-up softreset.
1998 return online ? -EAGAIN : rc;
2001 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
2002 unsigned long deadline)
2004 struct ata_port *ap = link->ap;
2005 struct ahci_port_priv *pp = ap->private_data;
2006 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2007 struct ata_taskfile tf;
2011 ahci_stop_engine(ap);
2013 /* clear D2H reception area to properly wait for D2H FIS */
2014 ata_tf_init(link->device, &tf);
2016 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
2018 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
2019 deadline, &online, NULL);
2021 ahci_start_engine(ap);
2023 /* The pseudo configuration device on SIMG4726 attached to
2024 * ASUS P5W-DH Deluxe doesn't send signature FIS after
2025 * hardreset if no device is attached to the first downstream
2026 * port && the pseudo device locks up on SRST w/ PMP==0. To
2027 * work around this, wait for !BSY only briefly. If BSY isn't
2028 * cleared, perform CLO and proceed to IDENTIFY (achieved by
2029 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
2031 * Wait for two seconds. Devices attached to downstream port
2032 * which can't process the following IDENTIFY after this will
2033 * have to be reset again. For most cases, this should
2034 * suffice while making probing snappish enough.
2037 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
2040 ahci_kick_engine(ap);
2045 static void ahci_postreset(struct ata_link *link, unsigned int *class)
2047 struct ata_port *ap = link->ap;
2048 void __iomem *port_mmio = ahci_port_base(ap);
2051 ata_std_postreset(link, class);
2053 /* Make sure port's ATAPI bit is set appropriately */
2054 new_tmp = tmp = readl(port_mmio + PORT_CMD);
2055 if (*class == ATA_DEV_ATAPI)
2056 new_tmp |= PORT_CMD_ATAPI;
2058 new_tmp &= ~PORT_CMD_ATAPI;
2059 if (new_tmp != tmp) {
2060 writel(new_tmp, port_mmio + PORT_CMD);
2061 readl(port_mmio + PORT_CMD); /* flush */
2065 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
2067 struct scatterlist *sg;
2068 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
2074 * Next, the S/G list.
2076 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2077 dma_addr_t addr = sg_dma_address(sg);
2078 u32 sg_len = sg_dma_len(sg);
2080 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
2081 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
2082 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
2088 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
2090 struct ata_port *ap = qc->ap;
2091 struct ahci_port_priv *pp = ap->private_data;
2093 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
2094 return ata_std_qc_defer(qc);
2096 return sata_pmp_qc_defer_cmd_switch(qc);
2099 static void ahci_qc_prep(struct ata_queued_cmd *qc)
2101 struct ata_port *ap = qc->ap;
2102 struct ahci_port_priv *pp = ap->private_data;
2103 int is_atapi = ata_is_atapi(qc->tf.protocol);
2106 const u32 cmd_fis_len = 5; /* five dwords */
2107 unsigned int n_elem;
2110 * Fill in command table information. First, the header,
2111 * a SATA Register - Host to Device command FIS.
2113 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
2115 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
2117 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
2118 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
2122 if (qc->flags & ATA_QCFLAG_DMAMAP)
2123 n_elem = ahci_fill_sg(qc, cmd_tbl);
2126 * Fill in command slot information.
2128 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
2129 if (qc->tf.flags & ATA_TFLAG_WRITE)
2130 opts |= AHCI_CMD_WRITE;
2132 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
2134 ahci_fill_cmd_slot(pp, qc->tag, opts);
2137 static void ahci_fbs_dec_intr(struct ata_port *ap)
2139 struct ahci_port_priv *pp = ap->private_data;
2140 void __iomem *port_mmio = ahci_port_base(ap);
2141 u32 fbs = readl(port_mmio + PORT_FBS);
2145 BUG_ON(!pp->fbs_enabled);
2147 /* time to wait for DEC is not specified by AHCI spec,
2148 * add a retry loop for safety.
2150 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
2151 fbs = readl(port_mmio + PORT_FBS);
2152 while ((fbs & PORT_FBS_DEC) && retries--) {
2154 fbs = readl(port_mmio + PORT_FBS);
2157 if (fbs & PORT_FBS_DEC)
2158 dev_printk(KERN_ERR, ap->host->dev,
2159 "failed to clear device error\n");
2162 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
2164 struct ahci_host_priv *hpriv = ap->host->private_data;
2165 struct ahci_port_priv *pp = ap->private_data;
2166 struct ata_eh_info *host_ehi = &ap->link.eh_info;
2167 struct ata_link *link = NULL;
2168 struct ata_queued_cmd *active_qc;
2169 struct ata_eh_info *active_ehi;
2170 bool fbs_need_dec = false;
2173 /* determine active link with error */
2174 if (pp->fbs_enabled) {
2175 void __iomem *port_mmio = ahci_port_base(ap);
2176 u32 fbs = readl(port_mmio + PORT_FBS);
2177 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
2179 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
2180 ata_link_online(&ap->pmp_link[pmp])) {
2181 link = &ap->pmp_link[pmp];
2182 fbs_need_dec = true;
2186 ata_for_each_link(link, ap, EDGE)
2187 if (ata_link_active(link))
2193 active_qc = ata_qc_from_tag(ap, link->active_tag);
2194 active_ehi = &link->eh_info;
2196 /* record irq stat */
2197 ata_ehi_clear_desc(host_ehi);
2198 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
2200 /* AHCI needs SError cleared; otherwise, it might lock up */
2201 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2202 ahci_scr_write(&ap->link, SCR_ERROR, serror);
2203 host_ehi->serror |= serror;
2205 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
2206 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
2207 irq_stat &= ~PORT_IRQ_IF_ERR;
2209 if (irq_stat & PORT_IRQ_TF_ERR) {
2210 /* If qc is active, charge it; otherwise, the active
2211 * link. There's no active qc on NCQ errors. It will
2212 * be determined by EH by reading log page 10h.
2215 active_qc->err_mask |= AC_ERR_DEV;
2217 active_ehi->err_mask |= AC_ERR_DEV;
2219 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
2220 host_ehi->serror &= ~SERR_INTERNAL;
2223 if (irq_stat & PORT_IRQ_UNK_FIS) {
2224 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2226 active_ehi->err_mask |= AC_ERR_HSM;
2227 active_ehi->action |= ATA_EH_RESET;
2228 ata_ehi_push_desc(active_ehi,
2229 "unknown FIS %08x %08x %08x %08x" ,
2230 unk[0], unk[1], unk[2], unk[3]);
2233 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
2234 active_ehi->err_mask |= AC_ERR_HSM;
2235 active_ehi->action |= ATA_EH_RESET;
2236 ata_ehi_push_desc(active_ehi, "incorrect PMP");
2239 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2240 host_ehi->err_mask |= AC_ERR_HOST_BUS;
2241 host_ehi->action |= ATA_EH_RESET;
2242 ata_ehi_push_desc(host_ehi, "host bus error");
2245 if (irq_stat & PORT_IRQ_IF_ERR) {
2247 active_ehi->err_mask |= AC_ERR_DEV;
2249 host_ehi->err_mask |= AC_ERR_ATA_BUS;
2250 host_ehi->action |= ATA_EH_RESET;
2253 ata_ehi_push_desc(host_ehi, "interface fatal error");
2256 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2257 ata_ehi_hotplugged(host_ehi);
2258 ata_ehi_push_desc(host_ehi, "%s",
2259 irq_stat & PORT_IRQ_CONNECT ?
2260 "connection status changed" : "PHY RDY changed");
2263 /* okay, let's hand over to EH */
2265 if (irq_stat & PORT_IRQ_FREEZE)
2266 ata_port_freeze(ap);
2267 else if (fbs_need_dec) {
2268 ata_link_abort(link);
2269 ahci_fbs_dec_intr(ap);
2274 static void ahci_port_intr(struct ata_port *ap)
2276 void __iomem *port_mmio = ahci_port_base(ap);
2277 struct ata_eh_info *ehi = &ap->link.eh_info;
2278 struct ahci_port_priv *pp = ap->private_data;
2279 struct ahci_host_priv *hpriv = ap->host->private_data;
2280 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2281 u32 status, qc_active = 0;
2284 status = readl(port_mmio + PORT_IRQ_STAT);
2285 writel(status, port_mmio + PORT_IRQ_STAT);
2287 /* ignore BAD_PMP while resetting */
2288 if (unlikely(resetting))
2289 status &= ~PORT_IRQ_BAD_PMP;
2291 /* If we are getting PhyRdy, this is
2292 * just a power state change, we should
2293 * clear out this, plus the PhyRdy/Comm
2294 * Wake bits from Serror
2296 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2297 (status & PORT_IRQ_PHYRDY)) {
2298 status &= ~PORT_IRQ_PHYRDY;
2299 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
2302 if (unlikely(status & PORT_IRQ_ERROR)) {
2303 ahci_error_intr(ap, status);
2307 if (status & PORT_IRQ_SDB_FIS) {
2308 /* If SNotification is available, leave notification
2309 * handling to sata_async_notification(). If not,
2310 * emulate it by snooping SDB FIS RX area.
2312 * Snooping FIS RX area is probably cheaper than
2313 * poking SNotification but some constrollers which
2314 * implement SNotification, ICH9 for example, don't
2315 * store AN SDB FIS into receive area.
2317 if (hpriv->cap & HOST_CAP_SNTF)
2318 sata_async_notification(ap);
2320 /* If the 'N' bit in word 0 of the FIS is set,
2321 * we just received asynchronous notification.
2322 * Tell libata about it.
2324 * Lack of SNotification should not appear in
2325 * ahci 1.2, so the workaround is unnecessary
2326 * when FBS is enabled.
2328 if (pp->fbs_enabled)
2331 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2332 u32 f0 = le32_to_cpu(f[0]);
2334 sata_async_notification(ap);
2339 /* pp->active_link is not reliable once FBS is enabled, both
2340 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
2341 * NCQ and non-NCQ commands may be in flight at the same time.
2343 if (pp->fbs_enabled) {
2344 if (ap->qc_active) {
2345 qc_active = readl(port_mmio + PORT_SCR_ACT);
2346 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
2349 /* pp->active_link is valid iff any command is in flight */
2350 if (ap->qc_active && pp->active_link->sactive)
2351 qc_active = readl(port_mmio + PORT_SCR_ACT);
2353 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2356 rc = ata_qc_complete_multiple(ap, qc_active);
2358 /* while resetting, invalid completions are expected */
2359 if (unlikely(rc < 0 && !resetting)) {
2360 ehi->err_mask |= AC_ERR_HSM;
2361 ehi->action |= ATA_EH_RESET;
2362 ata_port_freeze(ap);
2366 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2368 struct ata_host *host = dev_instance;
2369 struct ahci_host_priv *hpriv;
2370 unsigned int i, handled = 0;
2372 u32 irq_stat, irq_masked;
2376 hpriv = host->private_data;
2377 mmio = host->iomap[AHCI_PCI_BAR];
2379 /* sigh. 0xffffffff is a valid return from h/w */
2380 irq_stat = readl(mmio + HOST_IRQ_STAT);
2384 irq_masked = irq_stat & hpriv->port_map;
2386 spin_lock(&host->lock);
2388 for (i = 0; i < host->n_ports; i++) {
2389 struct ata_port *ap;
2391 if (!(irq_masked & (1 << i)))
2394 ap = host->ports[i];
2397 VPRINTK("port %u\n", i);
2399 VPRINTK("port %u (no irq)\n", i);
2400 if (ata_ratelimit())
2401 dev_printk(KERN_WARNING, host->dev,
2402 "interrupt on disabled port %u\n", i);
2408 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2409 * it should be cleared after all the port events are cleared;
2410 * otherwise, it will raise a spurious interrupt after each
2411 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2414 * Also, use the unmasked value to clear interrupt as spurious
2415 * pending event on a dummy port might cause screaming IRQ.
2417 writel(irq_stat, mmio + HOST_IRQ_STAT);
2419 spin_unlock(&host->lock);
2423 return IRQ_RETVAL(handled);
2426 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2428 struct ata_port *ap = qc->ap;
2429 void __iomem *port_mmio = ahci_port_base(ap);
2430 struct ahci_port_priv *pp = ap->private_data;
2432 /* Keep track of the currently active link. It will be used
2433 * in completion path to determine whether NCQ phase is in
2436 pp->active_link = qc->dev->link;
2438 if (qc->tf.protocol == ATA_PROT_NCQ)
2439 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2441 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2442 u32 fbs = readl(port_mmio + PORT_FBS);
2443 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2444 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2445 writel(fbs, port_mmio + PORT_FBS);
2446 pp->fbs_last_dev = qc->dev->link->pmp;
2449 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2451 ahci_sw_activity(qc->dev->link);
2456 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2458 struct ahci_port_priv *pp = qc->ap->private_data;
2459 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2461 if (pp->fbs_enabled)
2462 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2464 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2468 static void ahci_freeze(struct ata_port *ap)
2470 void __iomem *port_mmio = ahci_port_base(ap);
2473 writel(0, port_mmio + PORT_IRQ_MASK);
2476 static void ahci_thaw(struct ata_port *ap)
2478 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2479 void __iomem *port_mmio = ahci_port_base(ap);
2481 struct ahci_port_priv *pp = ap->private_data;
2484 tmp = readl(port_mmio + PORT_IRQ_STAT);
2485 writel(tmp, port_mmio + PORT_IRQ_STAT);
2486 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2488 /* turn IRQ back on */
2489 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2492 static void ahci_error_handler(struct ata_port *ap)
2494 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2495 /* restart engine */
2496 ahci_stop_engine(ap);
2497 ahci_start_engine(ap);
2500 sata_pmp_error_handler(ap);
2503 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2505 struct ata_port *ap = qc->ap;
2507 /* make DMA engine forget about the failed command */
2508 if (qc->flags & ATA_QCFLAG_FAILED)
2509 ahci_kick_engine(ap);
2512 static void ahci_enable_fbs(struct ata_port *ap)
2514 struct ahci_port_priv *pp = ap->private_data;
2515 void __iomem *port_mmio = ahci_port_base(ap);
2519 if (!pp->fbs_supported)
2522 fbs = readl(port_mmio + PORT_FBS);
2523 if (fbs & PORT_FBS_EN) {
2524 pp->fbs_enabled = true;
2525 pp->fbs_last_dev = -1; /* initialization */
2529 rc = ahci_stop_engine(ap);
2533 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2534 fbs = readl(port_mmio + PORT_FBS);
2535 if (fbs & PORT_FBS_EN) {
2536 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
2537 pp->fbs_enabled = true;
2538 pp->fbs_last_dev = -1; /* initialization */
2540 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
2542 ahci_start_engine(ap);
2545 static void ahci_disable_fbs(struct ata_port *ap)
2547 struct ahci_port_priv *pp = ap->private_data;
2548 void __iomem *port_mmio = ahci_port_base(ap);
2552 if (!pp->fbs_supported)
2555 fbs = readl(port_mmio + PORT_FBS);
2556 if ((fbs & PORT_FBS_EN) == 0) {
2557 pp->fbs_enabled = false;
2561 rc = ahci_stop_engine(ap);
2565 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2566 fbs = readl(port_mmio + PORT_FBS);
2567 if (fbs & PORT_FBS_EN)
2568 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
2570 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
2571 pp->fbs_enabled = false;
2574 ahci_start_engine(ap);
2577 static void ahci_pmp_attach(struct ata_port *ap)
2579 void __iomem *port_mmio = ahci_port_base(ap);
2580 struct ahci_port_priv *pp = ap->private_data;
2583 cmd = readl(port_mmio + PORT_CMD);
2584 cmd |= PORT_CMD_PMP;
2585 writel(cmd, port_mmio + PORT_CMD);
2587 ahci_enable_fbs(ap);
2589 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2590 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2593 static void ahci_pmp_detach(struct ata_port *ap)
2595 void __iomem *port_mmio = ahci_port_base(ap);
2596 struct ahci_port_priv *pp = ap->private_data;
2599 ahci_disable_fbs(ap);
2601 cmd = readl(port_mmio + PORT_CMD);
2602 cmd &= ~PORT_CMD_PMP;
2603 writel(cmd, port_mmio + PORT_CMD);
2605 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2606 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2609 static int ahci_port_resume(struct ata_port *ap)
2612 ahci_start_port(ap);
2614 if (sata_pmp_attached(ap))
2615 ahci_pmp_attach(ap);
2617 ahci_pmp_detach(ap);
2623 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2625 const char *emsg = NULL;
2628 rc = ahci_deinit_port(ap, &emsg);
2630 ahci_power_down(ap);
2632 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2633 ahci_start_port(ap);
2639 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2641 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2642 struct ahci_host_priv *hpriv = host->private_data;
2643 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2646 if (mesg.event & PM_EVENT_SUSPEND &&
2647 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2648 dev_printk(KERN_ERR, &pdev->dev,
2649 "BIOS update required for suspend/resume\n");
2653 if (mesg.event & PM_EVENT_SLEEP) {
2654 /* AHCI spec rev1.1 section 8.3.3:
2655 * Software must disable interrupts prior to requesting a
2656 * transition of the HBA to D3 state.
2658 ctl = readl(mmio + HOST_CTL);
2659 ctl &= ~HOST_IRQ_EN;
2660 writel(ctl, mmio + HOST_CTL);
2661 readl(mmio + HOST_CTL); /* flush */
2664 return ata_pci_device_suspend(pdev, mesg);
2667 static int ahci_pci_device_resume(struct pci_dev *pdev)
2669 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2672 rc = ata_pci_device_do_resume(pdev);
2676 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2677 rc = ahci_reset_controller(host);
2681 ahci_init_controller(host);
2684 ata_host_resume(host);
2690 static int ahci_port_start(struct ata_port *ap)
2692 struct ahci_host_priv *hpriv = ap->host->private_data;
2693 struct device *dev = ap->host->dev;
2694 struct ahci_port_priv *pp;
2697 size_t dma_sz, rx_fis_sz;
2699 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2703 /* check FBS capability */
2704 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2705 void __iomem *port_mmio = ahci_port_base(ap);
2706 u32 cmd = readl(port_mmio + PORT_CMD);
2707 if (cmd & PORT_CMD_FBSCP)
2708 pp->fbs_supported = true;
2710 dev_printk(KERN_WARNING, dev,
2711 "The port is not capable of FBS\n");
2714 if (pp->fbs_supported) {
2715 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2716 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2718 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2719 rx_fis_sz = AHCI_RX_FIS_SZ;
2722 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2725 memset(mem, 0, dma_sz);
2728 * First item in chunk of DMA memory: 32-slot command table,
2729 * 32 bytes each in size
2732 pp->cmd_slot_dma = mem_dma;
2734 mem += AHCI_CMD_SLOT_SZ;
2735 mem_dma += AHCI_CMD_SLOT_SZ;
2738 * Second item: Received-FIS area
2741 pp->rx_fis_dma = mem_dma;
2744 mem_dma += rx_fis_sz;
2747 * Third item: data area for storing a single command
2748 * and its scatter-gather table
2751 pp->cmd_tbl_dma = mem_dma;
2754 * Save off initial list of interrupts to be enabled.
2755 * This could be changed later
2757 pp->intr_mask = DEF_PORT_IRQ;
2759 ap->private_data = pp;
2761 /* engage engines, captain */
2762 return ahci_port_resume(ap);
2765 static void ahci_port_stop(struct ata_port *ap)
2767 const char *emsg = NULL;
2770 /* de-initialize port */
2771 rc = ahci_deinit_port(ap, &emsg);
2773 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2776 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2781 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2782 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2784 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2786 dev_printk(KERN_ERR, &pdev->dev,
2787 "64-bit DMA enable failed\n");
2792 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2794 dev_printk(KERN_ERR, &pdev->dev,
2795 "32-bit DMA enable failed\n");
2798 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2800 dev_printk(KERN_ERR, &pdev->dev,
2801 "32-bit consistent DMA enable failed\n");
2808 static void ahci_print_info(struct ata_host *host)
2810 struct ahci_host_priv *hpriv = host->private_data;
2811 struct pci_dev *pdev = to_pci_dev(host->dev);
2812 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2813 u32 vers, cap, cap2, impl, speed;
2814 const char *speed_s;
2818 vers = readl(mmio + HOST_VERSION);
2821 impl = hpriv->port_map;
2823 speed = (cap >> 20) & 0xf;
2826 else if (speed == 2)
2828 else if (speed == 3)
2833 pci_read_config_word(pdev, 0x0a, &cc);
2834 if (cc == PCI_CLASS_STORAGE_IDE)
2836 else if (cc == PCI_CLASS_STORAGE_SATA)
2838 else if (cc == PCI_CLASS_STORAGE_RAID)
2843 dev_printk(KERN_INFO, &pdev->dev,
2844 "AHCI %02x%02x.%02x%02x "
2845 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2848 (vers >> 24) & 0xff,
2849 (vers >> 16) & 0xff,
2853 ((cap >> 8) & 0x1f) + 1,
2859 dev_printk(KERN_INFO, &pdev->dev,
2866 cap & HOST_CAP_64 ? "64bit " : "",
2867 cap & HOST_CAP_NCQ ? "ncq " : "",
2868 cap & HOST_CAP_SNTF ? "sntf " : "",
2869 cap & HOST_CAP_MPS ? "ilck " : "",
2870 cap & HOST_CAP_SSS ? "stag " : "",
2871 cap & HOST_CAP_ALPM ? "pm " : "",
2872 cap & HOST_CAP_LED ? "led " : "",
2873 cap & HOST_CAP_CLO ? "clo " : "",
2874 cap & HOST_CAP_ONLY ? "only " : "",
2875 cap & HOST_CAP_PMP ? "pmp " : "",
2876 cap & HOST_CAP_FBS ? "fbs " : "",
2877 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2878 cap & HOST_CAP_SSC ? "slum " : "",
2879 cap & HOST_CAP_PART ? "part " : "",
2880 cap & HOST_CAP_CCC ? "ccc " : "",
2881 cap & HOST_CAP_EMS ? "ems " : "",
2882 cap & HOST_CAP_SXS ? "sxs " : "",
2883 cap2 & HOST_CAP2_APST ? "apst " : "",
2884 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2885 cap2 & HOST_CAP2_BOH ? "boh " : ""
2889 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2890 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2891 * support PMP and the 4726 either directly exports the device
2892 * attached to the first downstream port or acts as a hardware storage
2893 * controller and emulate a single ATA device (can be RAID 0/1 or some
2894 * other configuration).
2896 * When there's no device attached to the first downstream port of the
2897 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2898 * configure the 4726. However, ATA emulation of the device is very
2899 * lame. It doesn't send signature D2H Reg FIS after the initial
2900 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2902 * The following function works around the problem by always using
2903 * hardreset on the port and not depending on receiving signature FIS
2904 * afterward. If signature FIS isn't received soon, ATA class is
2905 * assumed without follow-up softreset.
2907 static void ahci_p5wdh_workaround(struct ata_host *host)
2909 static struct dmi_system_id sysids[] = {
2911 .ident = "P5W DH Deluxe",
2913 DMI_MATCH(DMI_SYS_VENDOR,
2914 "ASUSTEK COMPUTER INC"),
2915 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2920 struct pci_dev *pdev = to_pci_dev(host->dev);
2922 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2923 dmi_check_system(sysids)) {
2924 struct ata_port *ap = host->ports[1];
2926 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2927 "Deluxe on-board SIMG4726 workaround\n");
2929 ap->ops = &ahci_p5wdh_ops;
2930 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2934 /* only some SB600 ahci controllers can do 64bit DMA */
2935 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
2937 static const struct dmi_system_id sysids[] = {
2939 * The oldest version known to be broken is 0901 and
2940 * working is 1501 which was released on 2007-10-26.
2941 * Enable 64bit DMA on 1501 and anything newer.
2943 * Please read bko#9412 for more info.
2946 .ident = "ASUS M2A-VM",
2948 DMI_MATCH(DMI_BOARD_VENDOR,
2949 "ASUSTeK Computer INC."),
2950 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2952 .driver_data = "20071026", /* yyyymmdd */
2955 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
2956 * support 64bit DMA.
2958 * BIOS versions earlier than 1.5 had the Manufacturer DMI
2959 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
2960 * This spelling mistake was fixed in BIOS version 1.5, so
2961 * 1.5 and later have the Manufacturer as
2962 * "MICRO-STAR INTERNATIONAL CO.,LTD".
2963 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
2965 * BIOS versions earlier than 1.9 had a Board Product Name
2966 * DMI field of "MS-7376". This was changed to be
2967 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
2968 * match on DMI_BOARD_NAME of "MS-7376".
2971 .ident = "MSI K9A2 Platinum",
2973 DMI_MATCH(DMI_BOARD_VENDOR,
2974 "MICRO-STAR INTER"),
2975 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
2980 const struct dmi_system_id *match;
2981 int year, month, date;
2984 match = dmi_first_match(sysids);
2985 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
2989 if (!match->driver_data)
2992 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2993 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
2995 if (strcmp(buf, match->driver_data) >= 0)
2998 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
2999 "forcing 32bit DMA, update BIOS\n", match->ident);
3004 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
3009 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
3011 static const struct dmi_system_id broken_systems[] = {
3013 .ident = "HP Compaq nx6310",
3015 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3016 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
3018 /* PCI slot number of the controller */
3019 .driver_data = (void *)0x1FUL,
3022 .ident = "HP Compaq 6720s",
3024 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3025 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
3027 /* PCI slot number of the controller */
3028 .driver_data = (void *)0x1FUL,
3031 { } /* terminate list */
3033 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
3036 unsigned long slot = (unsigned long)dmi->driver_data;
3037 /* apply the quirk only to on-board controllers */
3038 return slot == PCI_SLOT(pdev->devfn);
3044 static bool ahci_broken_suspend(struct pci_dev *pdev)
3046 static const struct dmi_system_id sysids[] = {
3048 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
3049 * to the harddisk doesn't become online after
3050 * resuming from STR. Warn and fail suspend.
3052 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
3054 * Use dates instead of versions to match as HP is
3055 * apparently recycling both product and version
3058 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
3063 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3064 DMI_MATCH(DMI_PRODUCT_NAME,
3065 "HP Pavilion dv4 Notebook PC"),
3067 .driver_data = "20090105", /* F.30 */
3072 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3073 DMI_MATCH(DMI_PRODUCT_NAME,
3074 "HP Pavilion dv5 Notebook PC"),
3076 .driver_data = "20090506", /* F.16 */
3081 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3082 DMI_MATCH(DMI_PRODUCT_NAME,
3083 "HP Pavilion dv6 Notebook PC"),
3085 .driver_data = "20090423", /* F.21 */
3090 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3091 DMI_MATCH(DMI_PRODUCT_NAME,
3092 "HP HDX18 Notebook PC"),
3094 .driver_data = "20090430", /* F.23 */
3097 * Acer eMachines G725 has the same problem. BIOS
3098 * V1.03 is known to be broken. V3.04 is known to
3099 * work. Inbetween, there are V1.06, V2.06 and V3.03
3100 * that we don't have much idea about. For now,
3101 * blacklist anything older than V3.04.
3103 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
3108 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
3109 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
3111 .driver_data = "20091216", /* V3.04 */
3113 { } /* terminate list */
3115 const struct dmi_system_id *dmi = dmi_first_match(sysids);
3116 int year, month, date;
3119 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
3122 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
3123 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
3125 return strcmp(buf, dmi->driver_data) < 0;
3128 static bool ahci_broken_online(struct pci_dev *pdev)
3130 #define ENCODE_BUSDEVFN(bus, slot, func) \
3131 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
3132 static const struct dmi_system_id sysids[] = {
3134 * There are several gigabyte boards which use
3135 * SIMG5723s configured as hardware RAID. Certain
3136 * 5723 firmware revisions shipped there keep the link
3137 * online but fail to answer properly to SRST or
3138 * IDENTIFY when no device is attached downstream
3139 * causing libata to retry quite a few times leading
3140 * to excessive detection delay.
3142 * As these firmwares respond to the second reset try
3143 * with invalid device signature, considering unknown
3144 * sig as offline works around the problem acceptably.
3147 .ident = "EP45-DQ6",
3149 DMI_MATCH(DMI_BOARD_VENDOR,
3150 "Gigabyte Technology Co., Ltd."),
3151 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
3153 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
3156 .ident = "EP45-DS5",
3158 DMI_MATCH(DMI_BOARD_VENDOR,
3159 "Gigabyte Technology Co., Ltd."),
3160 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
3162 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
3164 { } /* terminate list */
3166 #undef ENCODE_BUSDEVFN
3167 const struct dmi_system_id *dmi = dmi_first_match(sysids);
3173 val = (unsigned long)dmi->driver_data;
3175 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
3178 #ifdef CONFIG_ATA_ACPI
3179 static void ahci_gtf_filter_workaround(struct ata_host *host)
3181 static const struct dmi_system_id sysids[] = {
3183 * Aspire 3810T issues a bunch of SATA enable commands
3184 * via _GTF including an invalid one and one which is
3185 * rejected by the device. Among the successful ones
3186 * is FPDMA non-zero offset enable which when enabled
3187 * only on the drive side leads to NCQ command
3188 * failures. Filter it out.
3191 .ident = "Aspire 3810T",
3193 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
3194 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
3196 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
3200 const struct dmi_system_id *dmi = dmi_first_match(sysids);
3201 unsigned int filter;
3207 filter = (unsigned long)dmi->driver_data;
3208 dev_printk(KERN_INFO, host->dev,
3209 "applying extra ACPI _GTF filter 0x%x for %s\n",
3210 filter, dmi->ident);
3212 for (i = 0; i < host->n_ports; i++) {
3213 struct ata_port *ap = host->ports[i];
3214 struct ata_link *link;
3215 struct ata_device *dev;
3217 ata_for_each_link(link, ap, EDGE)
3218 ata_for_each_dev(dev, link, ALL)
3219 dev->gtf_filter |= filter;
3223 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
3227 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3229 static int printed_version;
3230 unsigned int board_id = ent->driver_data;
3231 struct ata_port_info pi = ahci_port_info[board_id];
3232 const struct ata_port_info *ppi[] = { &pi, NULL };
3233 struct device *dev = &pdev->dev;
3234 struct ahci_host_priv *hpriv;
3235 struct ata_host *host;
3240 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
3242 if (!printed_version++)
3243 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
3245 /* The AHCI driver can only drive the SATA ports, the PATA driver
3246 can drive them all so if both drivers are selected make sure
3247 AHCI stays out of the way */
3248 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
3251 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
3252 * At the moment, we can only use the AHCI mode. Let the users know
3253 * that for SAS drives they're out of luck.
3255 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
3256 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
3257 "can only drive SATA devices with this driver\n");
3259 /* acquire resources */
3260 rc = pcim_enable_device(pdev);
3264 /* AHCI controllers often implement SFF compatible interface.
3265 * Grab all PCI BARs just in case.
3267 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
3269 pcim_pin_device(pdev);
3273 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
3274 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
3277 /* ICH6s share the same PCI ID for both piix and ahci
3278 * modes. Enabling ahci mode while MAP indicates
3279 * combined mode is a bad idea. Yield to ata_piix.
3281 pci_read_config_byte(pdev, ICH_MAP, &map);
3283 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
3284 "combined mode, can't enable AHCI mode\n");
3289 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
3292 hpriv->flags |= (unsigned long)pi.private_data;
3294 /* MCP65 revision A1 and A2 can't do MSI */
3295 if (board_id == board_ahci_mcp65 &&
3296 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
3297 hpriv->flags |= AHCI_HFLAG_NO_MSI;
3299 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
3300 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
3301 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
3303 /* only some SB600s can do 64bit DMA */
3304 if (ahci_sb600_enable_64bit(pdev))
3305 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
3307 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
3310 /* save initial config */
3311 ahci_save_initial_config(pdev, hpriv);
3314 if (hpriv->cap & HOST_CAP_NCQ) {
3315 pi.flags |= ATA_FLAG_NCQ;
3316 /* Auto-activate optimization is supposed to be supported on
3317 all AHCI controllers indicating NCQ support, but it seems
3318 to be broken at least on some NVIDIA MCP79 chipsets.
3319 Until we get info on which NVIDIA chipsets don't have this
3320 issue, if any, disable AA on all NVIDIA AHCIs. */
3321 if (pdev->vendor != PCI_VENDOR_ID_NVIDIA)
3322 pi.flags |= ATA_FLAG_FPDMA_AA;
3325 if (hpriv->cap & HOST_CAP_PMP)
3326 pi.flags |= ATA_FLAG_PMP;
3328 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
3330 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
3331 u32 em_loc = readl(mmio + HOST_EM_LOC);
3332 u32 em_ctl = readl(mmio + HOST_EM_CTL);
3334 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
3336 /* we only support LED message type right now */
3337 if ((messages & 0x01) && (ahci_em_messages == 1)) {
3339 hpriv->em_loc = ((em_loc >> 16) * 4);
3340 pi.flags |= ATA_FLAG_EM;
3341 if (!(em_ctl & EM_CTL_ALHD))
3342 pi.flags |= ATA_FLAG_SW_ACTIVITY;
3346 if (ahci_broken_system_poweroff(pdev)) {
3347 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
3348 dev_info(&pdev->dev,
3349 "quirky BIOS, skipping spindown on poweroff\n");
3352 if (ahci_broken_suspend(pdev)) {
3353 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
3354 dev_printk(KERN_WARNING, &pdev->dev,
3355 "BIOS update required for suspend/resume\n");
3358 if (ahci_broken_online(pdev)) {
3359 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
3360 dev_info(&pdev->dev,
3361 "online status unreliable, applying workaround\n");
3364 /* CAP.NP sometimes indicate the index of the last enabled
3365 * port, at other times, that of the last possible port, so
3366 * determining the maximum port number requires looking at
3367 * both CAP.NP and port_map.
3369 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
3371 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3374 host->iomap = pcim_iomap_table(pdev);
3375 host->private_data = hpriv;
3377 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
3378 host->flags |= ATA_HOST_PARALLEL_SCAN;
3380 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
3382 if (pi.flags & ATA_FLAG_EM)
3383 ahci_reset_em(host);
3385 for (i = 0; i < host->n_ports; i++) {
3386 struct ata_port *ap = host->ports[i];
3388 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
3389 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
3390 0x100 + ap->port_no * 0x80, "port");
3392 /* set initial link pm policy */
3393 ap->pm_policy = NOT_AVAILABLE;
3395 /* set enclosure management message type */
3396 if (ap->flags & ATA_FLAG_EM)
3397 ap->em_message_type = ahci_em_messages;
3400 /* disabled/not-implemented port */
3401 if (!(hpriv->port_map & (1 << i)))
3402 ap->ops = &ata_dummy_port_ops;
3405 /* apply workaround for ASUS P5W DH Deluxe mainboard */
3406 ahci_p5wdh_workaround(host);
3408 /* apply gtf filter quirk */
3409 ahci_gtf_filter_workaround(host);
3411 /* initialize adapter */
3412 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
3416 rc = ahci_reset_controller(host);
3420 ahci_init_controller(host);
3421 ahci_print_info(host);
3423 pci_set_master(pdev);
3424 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
3428 static int __init ahci_init(void)
3430 return pci_register_driver(&ahci_pci_driver);
3433 static void __exit ahci_exit(void)
3435 pci_unregister_driver(&ahci_pci_driver);
3439 MODULE_AUTHOR("Jeff Garzik");
3440 MODULE_DESCRIPTION("AHCI SATA low-level driver");
3441 MODULE_LICENSE("GPL");
3442 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
3443 MODULE_VERSION(DRV_VERSION);
3445 module_init(ahci_init);
3446 module_exit(ahci_exit);