2 * Broadcom SATA3 AHCI Controller Driver
4 * Copyright © 2009-2015 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/ahci_platform.h>
18 #include <linux/compiler.h>
19 #include <linux/device.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/libata.h>
25 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/string.h>
32 #define DRV_NAME "brcm-ahci"
34 #define SATA_TOP_CTRL_VERSION 0x0
35 #define SATA_TOP_CTRL_BUS_CTRL 0x4
36 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
37 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
38 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
39 #define PIODATA_ENDIAN_SHIFT 6
40 #define ENDIAN_SWAP_NONE 0
41 #define ENDIAN_SWAP_FULL 2
42 #define OVERRIDE_HWINIT BIT(16)
43 #define SATA_TOP_CTRL_TP_CTRL 0x8
44 #define SATA_TOP_CTRL_PHY_CTRL 0xc
45 #define SATA_TOP_CTRL_PHY_CTRL_1 0x0
46 #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
47 #define SATA_TOP_CTRL_PHY_CTRL_2 0x4
48 #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0)
49 #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1)
50 #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
51 #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
52 #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
53 #define SATA_TOP_CTRL_PHY_OFFS 0x8
54 #define SATA_TOP_MAX_PHYS 2
56 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
57 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
58 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
59 #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
65 #define BUS_CTRL_ENDIAN_CONF \
66 ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \
67 (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \
68 (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
70 enum brcm_ahci_quirks {
71 BRCM_AHCI_QUIRK_NO_NCQ = BIT(0),
72 BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1),
75 struct brcm_ahci_priv {
77 void __iomem *top_ctrl;
82 static const struct ata_port_info ahci_brcm_port_info = {
83 .flags = AHCI_FLAG_COMMON,
85 .udma_mask = ATA_UDMA6,
86 .port_ops = &ahci_platform_ops,
89 static inline u32 brcm_sata_readreg(void __iomem *addr)
92 * MIPS endianness is configured by boot strap, which also reverses all
93 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
96 * Other architectures (e.g., ARM) either do not support big endian, or
97 * else leave I/O in little endian mode.
99 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
100 return __raw_readl(addr);
102 return readl_relaxed(addr);
105 static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
107 /* See brcm_sata_readreg() comments */
108 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
109 __raw_writel(val, addr);
111 writel_relaxed(val, addr);
114 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
116 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
117 (port * SATA_TOP_CTRL_PHY_OFFS);
121 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
124 /* clear PHY_DEFAULT_POWER_STATE */
125 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
126 reg = brcm_sata_readreg(p);
127 reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
128 brcm_sata_writereg(reg, p);
130 /* reset the PHY digital logic */
131 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
132 reg = brcm_sata_readreg(p);
133 reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
134 SATA_TOP_CTRL_2_SW_RST_RX);
135 reg |= SATA_TOP_CTRL_2_SW_RST_TX;
136 brcm_sata_writereg(reg, p);
137 reg = brcm_sata_readreg(p);
138 reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
139 brcm_sata_writereg(reg, p);
140 reg = brcm_sata_readreg(p);
141 reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
142 brcm_sata_writereg(reg, p);
143 (void)brcm_sata_readreg(p);
146 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
148 void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
149 (port * SATA_TOP_CTRL_PHY_OFFS);
153 if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
156 /* power-off the PHY digital logic */
157 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
158 reg = brcm_sata_readreg(p);
159 reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
160 SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
161 SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
162 brcm_sata_writereg(reg, p);
164 /* set PHY_DEFAULT_POWER_STATE */
165 p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
166 reg = brcm_sata_readreg(p);
167 reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
168 brcm_sata_writereg(reg, p);
171 static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
175 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
176 if (priv->port_mask & BIT(i))
177 brcm_sata_phy_enable(priv, i);
180 static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
184 for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
185 if (priv->port_mask & BIT(i))
186 brcm_sata_phy_disable(priv, i);
189 static u32 brcm_ahci_get_portmask(struct platform_device *pdev,
190 struct brcm_ahci_priv *priv)
193 struct resource *res;
196 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
197 ahci = devm_ioremap_resource(&pdev->dev, res);
201 impl = readl(ahci + HOST_PORTS_IMPL);
203 if (fls(impl) > SATA_TOP_MAX_PHYS)
204 dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
207 dev_info(priv->dev, "no ports found\n");
209 devm_iounmap(&pdev->dev, ahci);
210 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
215 static void brcm_sata_init(struct brcm_ahci_priv *priv)
217 /* Configure endianness */
218 brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF,
219 priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
222 #ifdef CONFIG_PM_SLEEP
223 static int brcm_ahci_suspend(struct device *dev)
225 struct ata_host *host = dev_get_drvdata(dev);
226 struct ahci_host_priv *hpriv = host->private_data;
227 struct brcm_ahci_priv *priv = hpriv->plat_data;
230 ret = ahci_platform_suspend(dev);
231 brcm_sata_phys_disable(priv);
235 static int brcm_ahci_resume(struct device *dev)
237 struct ata_host *host = dev_get_drvdata(dev);
238 struct ahci_host_priv *hpriv = host->private_data;
239 struct brcm_ahci_priv *priv = hpriv->plat_data;
241 brcm_sata_init(priv);
242 brcm_sata_phys_enable(priv);
243 return ahci_platform_resume(dev);
247 static struct scsi_host_template ahci_platform_sht = {
251 static int brcm_ahci_probe(struct platform_device *pdev)
253 struct device *dev = &pdev->dev;
254 struct brcm_ahci_priv *priv;
255 struct ahci_host_priv *hpriv;
256 struct resource *res;
259 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
264 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
265 priv->top_ctrl = devm_ioremap_resource(dev, res);
266 if (IS_ERR(priv->top_ctrl))
267 return PTR_ERR(priv->top_ctrl);
269 if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) {
270 priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
271 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
274 brcm_sata_init(priv);
276 priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
277 if (!priv->port_mask)
280 brcm_sata_phys_enable(priv);
282 hpriv = ahci_platform_get_resources(pdev);
284 return PTR_ERR(hpriv);
285 hpriv->plat_data = priv;
287 ret = ahci_platform_enable_resources(hpriv);
291 if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
292 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
294 ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
299 dev_info(dev, "Broadcom AHCI SATA3 registered\n");
304 static int brcm_ahci_remove(struct platform_device *pdev)
306 struct ata_host *host = dev_get_drvdata(&pdev->dev);
307 struct ahci_host_priv *hpriv = host->private_data;
308 struct brcm_ahci_priv *priv = hpriv->plat_data;
311 ret = ata_platform_remove_one(pdev);
315 brcm_sata_phys_disable(priv);
320 static const struct of_device_id ahci_of_match[] = {
321 {.compatible = "brcm,bcm7425-ahci"},
322 {.compatible = "brcm,bcm7445-ahci"},
325 MODULE_DEVICE_TABLE(of, ahci_of_match);
327 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
329 static struct platform_driver brcm_ahci_driver = {
330 .probe = brcm_ahci_probe,
331 .remove = brcm_ahci_remove,
334 .of_match_table = ahci_of_match,
335 .pm = &ahci_brcm_pm_ops,
338 module_platform_driver(brcm_ahci_driver);
340 MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
341 MODULE_AUTHOR("Brian Norris");
342 MODULE_LICENSE("GPL");
343 MODULE_ALIAS("platform:sata-brcmstb");