2 * Freescale QorIQ AHCI SATA platform driver
4 * Copyright 2015 Freescale, Inc.
5 * Tang Yuantian <Yuantian.Tang@freescale.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
13 #include <linux/kernel.h>
14 #include <linux/module.h>
16 #include <linux/ahci_platform.h>
17 #include <linux/device.h>
18 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/libata.h>
25 #define DRV_NAME "ahci-qoriq"
27 /* port register definition */
28 #define PORT_PHY1 0xA8
29 #define PORT_PHY2 0xAC
30 #define PORT_PHY3 0xB0
31 #define PORT_PHY4 0xB4
32 #define PORT_PHY5 0xB8
33 #define PORT_AXICC 0xBC
34 #define PORT_TRANS 0xC8
36 /* port register default value */
37 #define AHCI_PORT_PHY_1_CFG 0xa003fffe
38 #define AHCI_PORT_TRANS_CFG 0x08000029
39 #define AHCI_PORT_AXICC_CFG 0x3fffffff
42 #define LS1021A_PORT_PHY2 0x28183414
43 #define LS1021A_PORT_PHY3 0x0e080e06
44 #define LS1021A_PORT_PHY4 0x064a080b
45 #define LS1021A_PORT_PHY5 0x2aa86470
46 #define LS1021A_AXICC_ADDR 0xC0
48 #define SATA_ECC_DISABLE 0x00020000
49 #define ECC_DIS_ARMV8_CH2 0x80000000
51 enum ahci_qoriq_type {
59 struct ahci_qoriq_priv {
60 struct ccsr_ahci *reg_base;
61 enum ahci_qoriq_type type;
62 void __iomem *ecc_addr;
66 static const struct of_device_id ahci_qoriq_of_match[] = {
67 { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
68 { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
69 { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
70 { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
71 { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
74 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
76 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
77 unsigned long deadline)
79 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
80 void __iomem *port_mmio = ahci_port_base(link->ap);
81 u32 px_cmd, px_is, px_val;
82 struct ata_port *ap = link->ap;
83 struct ahci_port_priv *pp = ap->private_data;
84 struct ahci_host_priv *hpriv = ap->host->private_data;
85 struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
86 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
87 struct ata_taskfile tf;
90 bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
97 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
98 * A-009042: The device detection initialization sequence
99 * mistakenly resets some registers.
101 * Workaround for this is:
102 * The software should read and store PxCMD and PxIS values
103 * before issuing the device detection initialization sequence.
104 * After the sequence is complete, software should restore the
105 * PxCMD and PxIS with the stored values.
107 if (ls1021a_workaround) {
108 px_cmd = readl(port_mmio + PORT_CMD);
109 px_is = readl(port_mmio + PORT_IRQ_STAT);
112 /* clear D2H reception area to properly wait for D2H FIS */
113 ata_tf_init(link->device, &tf);
114 tf.command = ATA_BUSY;
115 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
117 rc = sata_link_hardreset(link, timing, deadline, &online,
120 /* restore the PxCMD and PxIS on ls1021 */
121 if (ls1021a_workaround) {
122 px_val = readl(port_mmio + PORT_CMD);
123 if (px_val != px_cmd)
124 writel(px_cmd, port_mmio + PORT_CMD);
126 px_val = readl(port_mmio + PORT_IRQ_STAT);
128 writel(px_is, port_mmio + PORT_IRQ_STAT);
131 hpriv->start_engine(ap);
134 *class = ahci_dev_classify(ap);
136 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
140 static struct ata_port_operations ahci_qoriq_ops = {
141 .inherits = &ahci_ops,
142 .hardreset = ahci_qoriq_hardreset,
145 static const struct ata_port_info ahci_qoriq_port_info = {
146 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_qoriq_ops,
152 static struct scsi_host_template ahci_qoriq_sht = {
156 static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
158 struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
159 void __iomem *reg_base = hpriv->mmio;
161 switch (qpriv->type) {
163 if (!qpriv->ecc_addr)
165 writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
166 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
167 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
168 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
169 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
170 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
171 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
172 if (qpriv->is_dmacoherent)
173 writel(AHCI_PORT_AXICC_CFG,
174 reg_base + LS1021A_AXICC_ADDR);
178 if (!qpriv->ecc_addr)
180 writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
181 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
182 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
183 if (qpriv->is_dmacoherent)
184 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
188 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
189 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
190 if (qpriv->is_dmacoherent)
191 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
195 if (!qpriv->ecc_addr)
197 writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
198 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
199 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
200 if (qpriv->is_dmacoherent)
201 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
205 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
206 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
207 if (qpriv->is_dmacoherent)
208 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
215 static int ahci_qoriq_probe(struct platform_device *pdev)
217 struct device_node *np = pdev->dev.of_node;
218 struct device *dev = &pdev->dev;
219 struct ahci_host_priv *hpriv;
220 struct ahci_qoriq_priv *qoriq_priv;
221 const struct of_device_id *of_id;
222 struct resource *res;
225 hpriv = ahci_platform_get_resources(pdev);
227 return PTR_ERR(hpriv);
229 of_id = of_match_node(ahci_qoriq_of_match, np);
233 qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
237 qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
239 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
242 qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
243 if (IS_ERR(qoriq_priv->ecc_addr))
244 return PTR_ERR(qoriq_priv->ecc_addr);
246 qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
248 rc = ahci_platform_enable_resources(hpriv);
252 hpriv->plat_data = qoriq_priv;
253 rc = ahci_qoriq_phy_init(hpriv);
255 goto disable_resources;
257 rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
260 goto disable_resources;
265 ahci_platform_disable_resources(hpriv);
270 #ifdef CONFIG_PM_SLEEP
271 static int ahci_qoriq_resume(struct device *dev)
273 struct ata_host *host = dev_get_drvdata(dev);
274 struct ahci_host_priv *hpriv = host->private_data;
277 rc = ahci_platform_enable_resources(hpriv);
281 rc = ahci_qoriq_phy_init(hpriv);
283 goto disable_resources;
285 rc = ahci_platform_resume_host(dev);
287 goto disable_resources;
289 /* We resumed so update PM runtime state */
290 pm_runtime_disable(dev);
291 pm_runtime_set_active(dev);
292 pm_runtime_enable(dev);
297 ahci_platform_disable_resources(hpriv);
303 static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
306 static struct platform_driver ahci_qoriq_driver = {
307 .probe = ahci_qoriq_probe,
308 .remove = ata_platform_remove_one,
311 .of_match_table = ahci_qoriq_of_match,
312 .pm = &ahci_qoriq_pm_ops,
315 module_platform_driver(ahci_qoriq_driver);
317 MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
318 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
319 MODULE_LICENSE("GPL");